| /external/llvm/lib/CodeGen/ |
| LiveIntervalUnion.cpp | 150 LiveInterval *VReg = LiveUnionI.value();
151 if (VReg != RecentReg && !isSeenInterference(VReg)) {
152 RecentReg = VReg;
153 InterferingVRegs.push_back(VReg);
|
| CallingConvLower.cpp | 246 unsigned VReg = MF.addLiveIn(PReg, RC);
247 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT));
|
| LiveRangeEdit.cpp | 35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
37 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
39 LiveInterval &LI = LIS.createEmptyInterval(VReg);
44 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
46 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
48 return VReg;
352 unsigned VReg = LI->reg;
354 TheDelegate->LRE_WillShrinkVirtReg(VReg);
364 if (VReg == RegsBeingSpilled[i]) {
379 unsigned Original = VRM ? VRM->getOriginal(VReg) : 0
[all...] |
| MIRPrinter.cpp | 207 yaml::VirtualRegisterDefinition VReg;
208 VReg.ID = I;
209 VReg.Class =
213 printReg(PreferredReg, VReg.PreferredRegister, TRI);
214 MF.VirtualRegisters.push_back(VReg);
|
| MachineFunction.cpp | 469 unsigned VReg = MRI.getLiveInVirtReg(PReg);
470 if (VReg) {
471 const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg);
481 return VReg;
483 VReg = MRI.createVirtualRegister(RC);
484 MRI.addLiveIn(PReg, VReg);
485 return VReg;
[all...] |
| RegAllocPBQP.cpp | 126 /// \brief Finds the initial set of vreg intervals to allocate.
132 /// \brief Spill the given VReg.
133 void spillVReg(unsigned VReg, SmallVectorImpl<unsigned> &NewIntervals,
298 unsigned VReg = G.getNodeMetadata(NId).getVReg();
299 LiveInterval &LI = LIS.getInterval(VReg);
566 unsigned VReg = Worklist.back();
569 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
570 LiveInterval &VRegLI = LIS.getInterval(VReg);
576 // Compute an initial allowed set for the current vreg.
607 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller)
[all...] |
| SplitKit.cpp | [all...] |
| TailDuplication.cpp | 246 unsigned VReg = SSAUpdateVRs[i];
247 SSAUpdate.Initialize(VReg);
251 MachineInstr *DefMI = MRI->getVRegDef(VReg);
255 SSAUpdate.AddAvailableValue(DefBB, VReg);
260 SSAUpdateVals.find(VReg);
268 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
[all...] |
| LiveIntervalAnalysis.cpp | 489 unsigned VReg = LI.reg;
490 if (MRI->shouldTrackSubRegLiveness(VReg)) {
493 MI->setRegisterDefReadUndef(VReg);
510 MI->addRegisterDead(VReg, TRI);
513 // the liverange then we rewrite it to use a different VReg to not violate
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegNumbering.cpp | 91 unsigned VReg = TargetRegisterInfo::index2VirtReg(VRegIdx);
93 if (MFI.isVRegStackified(VReg)) {
94 MFI.setWAReg(VReg, INT32_MIN | NumStackRegs++);
98 if (MRI.use_empty(VReg))
100 if (MFI.getWAReg(VReg) == WebAssemblyFunctionInfo::UnusedReg)
101 MFI.setWAReg(VReg, NumArgRegs + CurReg++);
|
| WebAssemblyRegColoring.cpp | 62 // Compute the total spill weight for VReg.
65 unsigned VReg) {
67 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg))
99 unsigned VReg = TargetRegisterInfo::index2VirtReg(i);
100 if (MFI.isVRegStackified(VReg))
103 if (MRI->use_empty(VReg))
106 LiveInterval *LI = &Liveness->getInterval(VReg);
108 LI->weight = computeWeight(MRI, MBFI, VReg);
160 DEBUG(dbgs() << "Assigning vreg"
161 << TargetRegisterInfo::virtReg2Index(LI->reg) << " to vreg"
[all...] |
| WebAssemblyRegStackify.cpp | 240 unsigned VReg = MO.getReg();
243 if (!TargetRegisterInfo::isVirtualRegister(VReg))
246 if (MFI.isVRegStackified(VReg)) {
248 Stack.push_back(VReg);
250 assert(Stack.pop_back_val() == VReg);
|
| WebAssemblyAsmPrinter.cpp | 173 unsigned VReg = TargetRegisterInfo::index2VirtReg(Idx);
174 unsigned WAReg = MFI->getWAReg(VReg);
184 Local.addOperand(MCOperand::createImm(getRegType(VReg).SimpleTy));
|
| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| NVPTXInstPrinter.cpp | 66 unsigned VReg = RegNo & 0x0FFFFFFF;
67 OS << VReg;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 100 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
101 // the CopyToReg'd destination register instead of creating a new vreg.
217 // is a vreg in the same register class, use the CopyToReg'd destination
218 // register instead of creating a new vreg.
288 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
291 if (!VReg) {
294 VReg = MRI->createVirtualRegister(RC);
297 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
298 return VReg;
321 unsigned VReg = getVR(Op, VRBaseMap)
[all...] |
| FunctionLoweringInfo.cpp | 353 /// consecutive vreg numbers and return the first assigned number.
519 unsigned &VReg = I.first->second;
521 VReg = MRI.createVirtualRegister(RC);
522 assert(VReg && "null vreg in exception pointer table!");
523 return VReg;
|
| SelectionDAGISel.cpp | 536 DEBUG(dbgs() << "Dropping debug info for dead vreg"
540 // If Reg is live-in then update debug info to track its copy in a vreg.
558 // If this vreg is directly copied into an exported register then
689 // If this is a CopyToReg with a vreg dest, process it.
[all...] |
| /external/llvm/lib/CodeGen/MIRParser/ |
| MIRParser.cpp | 349 for (const auto &VReg : YamlMF.VirtualRegisters) {
350 const auto *RC = getRegClass(MF, VReg.Class.Value);
352 return error(VReg.Class.SourceRange.Start,
354 VReg.Class.Value + "'");
356 if (!PFS.VirtualRegisterSlots.insert(std::make_pair(VReg.ID.Value, Reg))
358 return error(VReg.ID.SourceRange.Start,
360 Twine(VReg.ID.Value) + "'");
361 if (!VReg.PreferredRegister.Value.empty()) {
364 VReg.PreferredRegister.Value, PFS,
366 return error(Error, VReg.PreferredRegister.SourceRange)
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 219 unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass);
220 RegInfo.addLiveIn(VA.getLocReg(), VReg);
221 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
546 // control-flow pattern. The incoming instruction knows the destination vreg
|
| /external/v8/test/unittests/compiler/ |
| instruction-sequence-unittest.h | 23 struct VReg {
24 VReg() : value_(kNoValue) {}
25 VReg(PhiInstruction* phi) : value_(phi->virtual_register()) {} // NOLINT
26 explicit VReg(int value) : value_(value) {}
30 typedef std::pair<VReg, VReg> VRegPair;
51 TestOperand(TestOperandType type, VReg vreg, int value = kNoValue)
52 : type_(type), vreg_(vreg), value_(value) {}
55 VReg vreg_
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 166 ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT)
167 : VReg(VReg), PReg(PReg), VT(VT) {}
168 unsigned VReg;
|
| RegAllocPBQP.h | 79 /// \brief Holds a vector of the allowed physical regs for a vreg.
154 void setNodeIdForVReg(unsigned VReg, GraphBase::NodeId NId) {
155 VRegToNodeId[VReg] = NId;
158 GraphBase::NodeId getNodeIdForVReg(unsigned VReg) const {
159 auto VRegItr = VRegToNodeId.find(VReg);
165 void eraseNodeIdForVReg(unsigned VReg) {
166 VRegToNodeId.erase(VReg);
195 VReg(0)
205 OptUnsafeEdges(new unsigned[NumOpts]), VReg(Other.VReg),
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonStoreWidening.cpp | 448 // Create vreg = A2_tfrsi #Acc; mem[hw] = vreg
451 unsigned VReg = MF->getRegInfo().createVirtualRegister(RC);
452 MachineInstr *TfrI = BuildMI(*MF, DL, TfrD, VReg)
466 .addReg(VReg, RegState::Kill);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 463 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
464 RegInfo.addLiveIn(VA.getLocReg(), VReg);
465 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
