| /external/llvm/lib/Target/SystemZ/ |
| SystemZSelectionDAGInfo.cpp | 181 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL,
183 return ROTL;
|
| SystemZISelDAGToDAG.cpp | 109 // (or (rotl Input, Rotate), ~Mask)
113 // (and (rotl Input, Rotate), Mask)
792 case ISD::ROTL: {
844 // Treat (shl X, count) as (rotl X, size-count) as long as the bottom
849 // Treat (shl X, count) as (and (rotl X, count), ~0<<count).
871 // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top
876 // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count),
[all...] |
| /external/boringssl/src/decrepit/cast/ |
| cast.c | 85 #define ROTL(a, n) (_lrotl(a, n))
87 #define ROTL(a, n) ((((a) << (n)) | ((a) >> ((-(n))&31))) & 0xffffffffL)
94 t = ROTL(t, (key[n * 2 + 1])); \
|
| /external/dbus/dbus/ |
| dbus-sha.c | 125 #define ROTL(n,X) ( ( ( X ) << n ) | ( ( X ) >> ( 32 - n ) ) )
141 #define expand(W,i) ( W[ i & 15 ] = ROTL( 1, ( W[ i & 15 ] ^ W[ (i - 14) & 15 ] ^ \
147 a' = e + ROTL( 5, a ) + f( b, c, d ) + k + data;
149 c' = ROTL( 30, b );
159 ( e += ROTL( 5, a ) + f( b, c, d ) + k + data, b = ROTL( 30, b ) )
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 336 SHL, SRA, SRL, ROTL, ROTR,
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 43 setOperationAction(ISD::ROTL, MVT::i32, Custom);
250 case ISD::ROTL: return LowerROTL(Op, DAG);
|
| /external/vboot_reference/firmware/2lib/ |
| 2sha256.c | 44 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
|
| 2sha512.c | 44 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
|
| /external/vboot_reference/firmware/lib/cryptolib/ |
| sha256.c | 45 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
|
| sha512.c | 45 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| rx-parse.y | 162 %token RACW REIT REVL REVW RMPA ROLC RORC ROTL ROTR ROUND RTE RTFI RTS RTSD
734 | ROTL { sub_op = 6; } op_shift_rot
752 | ROTL '#' EXPR ',' REG
870 /* 000:SHLR, 001:SHAR, 010:SHLL, 011:-, 100:ROTR, 101:REVW, 110:ROTL, 111:REVL */
1071 OPC(ROTL),
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 175 setOperationAction(ISD::ROTL, MVT::i64, Legal);
178 setOperationAction(ISD::ROTL, MVT::i64, Expand);
182 setOperationAction(ISD::ROTL, MVT::i32, Legal);
185 setOperationAction(ISD::ROTL, MVT::i32, Expand);
189 setOperationAction(ISD::ROTL, MVT::i16, Expand);
191 setOperationAction(ISD::ROTL, MVT::i8, Expand);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 97 setOperationAction(ISD::ROTL, MVT::i8, Expand);
99 setOperationAction(ISD::ROTL, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 194 case ISD::ROTL: return "rotl";
|
| LegalizeVectorOps.cpp | 281 case ISD::ROTL:
[all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 133 setOperationAction(ISD::ROTL, MVT::i64, Expand);
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 151 {ISD::BSWAP, ISD::ROTL, ISD::ROTR, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
|
| /external/mmc-utils/3rdparty/hmac_sha/ |
| sha2.c | 48 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 502 } else if (Opcode == ISD::ROTL) {
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_ppc_toIR.c | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 264 // The hardware supports 32-bit ROTR, but not ROTL.
265 setOperationAction(ISD::ROTL, MVT::i32, Expand);
266 setOperationAction(ISD::ROTL, MVT::i64, Expand);
306 setOperationAction(ISD::ROTL, VT, Expand);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 111 setOperationAction(ISD::ROTL , MVT::i32, Expand);
[all...] |
