| /external/llvm/lib/Target/Hexagon/ |
| HexagonBitTracker.cpp | 107 const MachineOperand &MO = MI->getOperand(i);
108 if (MO.isReg())
109 Vector[i] = BT::RegisterRef(MO);
130 const MachineOperand &MO = MI->getOperand(i);
131 if (!MO.isReg() || !MO.isDef())
134 assert(MO.getSubReg() == 0);
169 const MachineOperand &MO = MI->getOperand(i);
170 if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() |
[all...] |
| HexagonGenPredicate.cpp | 42 Register(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {}
335 for (ConstMIOperands Mo(DefI); Mo.isValid(); ++Mo)
336 if (Mo->isReg() && Mo->isUse())
337 WorkQ.push(Register(Mo->getReg()));
357 MachineOperand &MO = MI->getOperand(i)
[all...] |
| HexagonStoreWidening.cpp | 108 const MachineOperand &MO = MI->getOperand(0);
109 assert(MO.isReg() && "Expecting register operand");
110 return MO.getReg();
121 const MachineOperand &MO = MI->getOperand(1);
122 assert(MO.isImm() && "Expecting immediate offset");
123 return MO.getImm();
|
| /external/llvm/lib/CodeGen/ |
| PrologEpilogInserter.cpp | [all...] |
| RegAllocFast.cpp | 216 /// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
219 bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) {
222 if (StackSlotForVirtReg[MO.getReg()] != -1)
225 // Check that the use/def chain has exactly one operand - MO.
226 MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(MO.getReg());
227 if (&*I != &MO)
235 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
236 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
237 if (MO.getReg() == LR.PhysReg)
238 MO.setIsKill()
[all...] |
| SplitKit.cpp | 130 for (MachineOperand &MO : MRI.use_nodbg_operands(CurLI->reg))
131 if (!MO.isUndef())
132 UseSlots.push_back(LIS.getInstructionIndex(MO.getParent()).getRegSlot());
[all...] |
| StackColoring.cpp | 253 const MachineOperand &MO = MI.getOperand(0);
254 unsigned Slot = MO.getIndex();
392 const MachineOperand &Mo = MI->getOperand(0);
393 int Slot = Mo.getIndex();
534 for (MachineOperand &MO : I.operands()) {
535 if (!MO.isFI())
537 int FromSlot = MO.getIndex();
568 MO.setIndex(ToSlot);
595 for (const MachineOperand &MO : I.operands()) {
596 if (!MO.isFI()
[all...] |
| TailDuplication.cpp | 433 MachineOperand &MO = NewMI->getOperand(i);
434 if (!MO.isReg())
436 unsigned Reg = MO.getReg();
439 if (MO.isDef()) {
442 MO.setReg(NewReg);
449 MO.setReg(VI->second);
452 MO.setIsKill(false);
477 MachineOperand &MO = II->getOperand(i+1);
478 if (MO.getMBB() == FromBB) {
492 MachineOperand &MO = II->getOperand(i+1)
[all...] |
| TargetLoweringBase.cpp | [all...] |
| InlineSpiller.cpp | 873 MachineOperand &MO = MI->getOperand(i);
874 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
875 MO.setIsUndef();
[all...] |
| LiveDebugVariables.cpp | 595 for (MachineOperand &MO : MRI.use_nodbg_operands(LI->reg)) {
596 MachineInstr *MI = MO.getParent();
598 if (MO.getSubReg() || !MI->isCopy())
805 MachineOperand MO = MachineOperand::CreateReg(LI->reg, false);
806 MO.setSubReg(locations[OldLocNo].getSubReg());
807 NewLocNo = getLocationNo(MO);
[all...] |
| LiveIntervalAnalysis.cpp | 236 for (const MachineOperand &MO : MI.operands()) {
237 if (!MO.isRegMask())
240 RegMaskBits.push_back(MO.getRegMask());
538 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
539 MachineInstr *UseMI = MO.getParent();
543 unsigned SubReg = MO.getSubReg();
764 for (const MachineOperand &MO : MI->operands()) {
765 if (!MO.isReg() || MO.getReg() != Reg)
767 if (MO.isUse())
[all...] |
| MachineBasicBlock.cpp | 652 MachineOperand &MO = MI->getOperand(i);
653 if (MO.getMBB() == FromMBB)
654 MO.setMBB(this);
904 MachineOperand &MO = I->getOperand(ni);
905 unsigned Reg = MO.getReg();
907 if (MO.isUndef())
[all...] |
| MachineInstr.cpp | 263 hash_code llvm::hash_value(const MachineOperand &MO) {
264 switch (MO.getType()) {
267 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
269 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
271 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm())
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ControlFlowFinalizer.cpp | 286 const MachineOperand &MO = *I;
287 if (!MO.isReg())
289 if (MO.isDef()) {
290 unsigned Reg = MO.getReg();
298 if (MO.isUse()) {
299 unsigned Reg = MO.getReg();
404 MachineOperand &MO = BI->getOperand(i);
405 if (MO.isReg() && MO.isInternalRead())
406 MO.setIsInternalRead(false)
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
277 const MCOperand &MO = MI.getOperand(Op);
279 // We expect MO to be an immediate or an expression,
282 if (MO.isExpr()) {
283 const MCExpr *Expr = MO.getExpr();
294 unsigned SoImm = MO.getImm();
310 const MCOperand &MO = MI.getOperand(Op);
313 if (MO.isExpr()) {
314 const MCExpr *Expr = MO.getExpr();
326 return MO.getImm()
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 266 for (const MachineOperand &MO : CPSRDef->operands()) {
267 if (!MO.isReg() || MO.isUndef() || MO.isUse())
269 unsigned Reg = MO.getReg();
275 for (const MachineOperand &MO : Use->operands()) {
276 if (!MO.isReg() || MO.isUndef() || MO.isDef())
278 unsigned Reg = MO.getReg()
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCInstrInfo.cpp | 129 MCOperand const &MO) {
139 if (MO.isImm())
140 XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
141 else if (MO.isExpr())
142 XMI.addOperand(MCOperand::createExpr(MO.getExpr()));
203 MCOperand const &MO = MCI.getOperand(O);
207 (MO.isImm() || MO.isExpr()));
208 return (MO);
418 MCOperand const &MO = HexagonMCInstrInfo::getExtendableOperand(MCII, MCI)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 89 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
90 MCOp = MCInstLowering.LowerOperand(MO);
442 const MachineOperand &MO = MI->getOperand(OpNum);
448 if ((MO.getType()) != MachineOperand::MO_Immediate)
450 O << "0x" << Twine::utohexstr(MO.getImm());
453 if ((MO.getType()) != MachineOperand::MO_Immediate)
455 O << "0x" << Twine::utohexstr(MO.getImm() & 0xffff);
458 if ((MO.getType()) != MachineOperand::MO_Immediate)
460 O << MO.getImm();
463 if ((MO.getType()) != MachineOperand::MO_Immediate
[all...] |
| MipsDelaySlotFiller.cpp | 277 const MachineOperand &MO = Filler->getOperand(I);
280 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
367 const MachineOperand &MO = MI.getOperand(I);
369 if (MO.isReg() && MO.getReg())
370 HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef());
|
| MipsSEISelDAGToDAG.cpp | 109 MachineOperand &MO = *U;
111 MachineInstr *MI = MO.getParent();
120 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
123 MO.setReg(ZeroReg);
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyPEI.cpp | [all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 75 unsigned GetX86RegNum(const MCOperand &MO) const {
76 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
746 const MCOperand &MO = MI.getOperand(CurOp);
747 if (MO.isReg()) {
748 if (X86II::isX86_64ExtendedReg(MO.getReg()))
750 if (X86II::is32ExtendedReg(MO.getReg()))
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 57 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
236 const MCOperand &MO = MI.getOperand(OpIdx);
245 if (MO.isReg()) {
246 unsigned reg = MO.getReg();
264 if (MO.isReg()) {
265 EmitByte(getHWRegChan(MO.getReg()), OS);
273 (MO.isReg() &&
274 (MO.getReg() == AMDGPU::NEG_ONE || MO.getReg() == AMDGPU::NEG_HALF)))){
300 const MCOperand &MO = MI.getOperand(0)
[all...] |
