| /external/clang/lib/StaticAnalyzer/Checkers/ |
| IvarInvalidationChecker.cpp | 677 BinaryOperatorKind Opcode = BO->getOpcode();
678 if (Opcode != BO_Assign &&
679 Opcode != BO_EQ &&
680 Opcode != BO_NE)
688 if (Opcode != BO_Assign && isZero(BO->getLHS())) {
|
| /external/llvm/include/llvm/MC/ |
| MCExpr.h | 356 enum Opcode {
364 Opcode Op;
367 MCUnaryExpr(Opcode Op, const MCExpr *Expr)
374 static const MCUnaryExpr *create(Opcode Op, const MCExpr *Expr,
394 Opcode getOpcode() const { return Op; }
409 enum Opcode {
436 Opcode Op;
439 MCBinaryExpr(Opcode Op, const MCExpr *LHS, const MCExpr *RHS)
446 static const MCBinaryExpr *create(Opcode Op, const MCExpr *LHS,
530 Opcode getOpcode() const { return Op;
[all...] |
| MCInstrDesc.h | 140 unsigned short Opcode; // The opcode number
177 /// \brief Return the opcode number for this descriptor.
178 unsigned getOpcode() const { return Opcode; }
531 /// or zero if the encoding size cannot be known from the opcode.
|
| /external/llvm/lib/IR/ |
| ConstantsContext.h | 43 UnaryConstantExpr(unsigned Opcode, Constant *C, Type *Ty)
44 : ConstantExpr(Ty, Opcode, &Op<0>(), 1) {
60 BinaryConstantExpr(unsigned Opcode, Constant *C1, Constant *C2,
62 : ConstantExpr(C1->getType(), Opcode, &Op<0>(), 2) {
449 uint8_t Opcode;
456 ConstantExprKeyType(unsigned Opcode, ArrayRef<Constant *> Ops,
461 : Opcode(Opcode), SubclassOptionalData(SubclassOptionalData),
465 : Opcode(CE->getOpcode()),
471 : Opcode(CE->getOpcode())
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 46 const char *llvm::X86Disassembler::GetInstrName(unsigned Opcode,
49 return MII->getName(Opcode);
347 default: llvm_unreachable("unexpected opcode");
373 // Switch opcode to the one that doesn't get special printing.
381 default: llvm_unreachable("unexpected opcode");
405 // Switch opcode to the one that doesn't get special printing.
412 default: llvm_unreachable("unexpected opcode");
534 // Switch opcode to the one that doesn't get special printing.
677 uint32_t Opcode = mcInst.getOpcode();
678 bool IndexIs128 = (Opcode == X86::VGATHERDPDrm |
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 107 int Opcode = isImmU6(OpImm) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
108 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
129 int Opcode = isImmU6(OpImm) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
130 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
200 int Opcode = isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
201 BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg)
261 int Opcode = isImmU6(Adjusted) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
263 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
286 int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
288 BuildMI(MBB, MBBI, dl, TII.get(Opcode))
[all...] |
| /external/libchrome/sandbox/win/src/sidestep/ |
| mini_disassembler_types.h | 15 // This opcode is not used
17 // This disassembler does not recognize this opcode (error)
117 // Everything that's in an Opcode (see below) except the three
118 // alternative opcode structs for different prefixes.
121 // byte in the opcode.
124 // The opcode type
140 struct Opcode {
142 // byte in the opcode.
145 // The opcode type
158 // Alternative opcode info if certain prefixes are specified
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 55 unsigned Opcode = MI->getOpcode();
57 if (Opcode == AArch64::SYSxt)
64 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
65 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
71 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
72 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri)
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ControlFlowFinalizer.cpp | 56 bool requiresWorkAroundForInst(unsigned Opcode);
59 void pushBranch(unsigned Opcode, bool isWQM = false);
78 bool CFStack::requiresWorkAroundForInst(unsigned Opcode) {
79 if (Opcode == AMDGPU::CF_ALU_PUSH_BEFORE && ST->hasCaymanISA() &&
86 switch(Opcode) {
150 void CFStack::pushBranch(unsigned Opcode, bool isWQM) {
152 switch(Opcode) {
236 unsigned Opcode = 0;
240 Opcode = isEg ? AMDGPU::CF_TC_EG : AMDGPU::CF_TC_R600;
243 Opcode = isEg ? AMDGPU::CF_VC_EG : AMDGPU::CF_VC_R600
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 45 uint16_t WideOpc; // Wide opcode
46 uint16_t NarrowOpc1; // Narrow opcode to transform to
47 uint16_t NarrowOpc2; // Narrow opcode when it's two-address
108 // FIXME: Clean this up after splitting each Thumb load / store opcode
151 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
323 /// Old opcode has an optional def of CPSR.
326 // If old opcode does not implicitly define CPSR, then it's not ok since
386 llvm_unreachable("Unexpected Thumb2 load / store opcode!");
634 // source insn opcode. So for now, we hack a local entry record to use.
909 unsigned Opcode = MI->getOpcode()
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsDelaySlotFiller.cpp | 548 // For given opcode returns opcode of corresponding instruction with short
550 static int getEquivalentCallShort(int Opcode) {
551 switch (Opcode) {
602 // If instruction in delay slot is 16b change opcode to
614 unsigned Opcode = I->getOpcode();
616 switch (Opcode) {
698 unsigned Opcode = (*Slot).getOpcode();
700 (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch |
[all...] |
| MipsSEISelDAGToDAG.cpp | 706 unsigned Opcode = Node->getOpcode();
715 switch(Opcode) {
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 585 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
600 // VEX_R: opcode externsion equivalent to REX.R in
623 // VEX_W: opcode specific (use like REX.W, or used for
624 // opcode extension, or ignored, depending on the opcode byte)
630 // 0b00001: implied 0F leading opcode
631 // 0b00010: implied 0F 38 leading opcode bytes
632 // 0b00011: implied 0F 3A leading opcode bytes
652 // VEX_PP: opcode extension providing equivalent
[all...] |
| /external/llvm/tools/llvm-readobj/ |
| ARMEHABIPrinter.h | 96 uint8_t Opcode = Opcodes[OI++ ^ 3];
97 SW.startLine() << format("0x%02X ; vsp = vsp + %u\n", Opcode,
98 ((Opcode & 0x3f) << 2) + 4);
101 uint8_t Opcode = Opcodes[OI++ ^ 3];
102 SW.startLine() << format("0x%02X ; vsp = vsp - %u\n", Opcode,
103 ((Opcode & 0x3f) << 2) + 4);
119 uint8_t Opcode = Opcodes[OI++ ^ 3];
120 SW.startLine() << format("0x%02X ; reserved (ARM MOVrr)\n", Opcode);
123 uint8_t Opcode = Opcodes[OI++ ^ 3];
124 SW.startLine() << format("0x%02X ; reserved (WiMMX MOVrr)\n", Opcode);
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_opcodes.h | 243 rc_opcode Opcode;
269 static inline const struct rc_opcode_info * rc_get_opcode_info(rc_opcode opcode)
271 assert((unsigned int)opcode < MAX_RC_OPCODE);
272 assert(rc_opcodes[opcode].Opcode == opcode);
274 return &rc_opcodes[opcode];
|
| /external/llvm/examples/Kaleidoscope/Chapter6/ |
| toy.cpp | 148 char Opcode;
152 UnaryExprAST(char Opcode, std::unique_ptr<ExprAST> Operand)
153 : Opcode(Opcode), Operand(std::move(Operand)) {}
648 Function *F = getFunction(std::string("unary") + Opcode);
|
| /external/llvm/examples/Kaleidoscope/Chapter7/ |
| toy.cpp | 154 char Opcode;
158 UnaryExprAST(char Opcode, std::unique_ptr<ExprAST> Operand)
159 : Opcode(Opcode), Operand(std::move(Operand)) {}
730 Function *F = getFunction(std::string("unary") + Opcode);
[all...] |
| /external/llvm/examples/Kaleidoscope/MCJIT/cached/ |
| toy-jit.cpp | 152 char Opcode;
155 UnaryExprAST(char opcode, ExprAST *operand)
156 : Opcode(opcode), Operand(operand) {}
658 Function *F = TheHelper->getFunction(MakeLegalFunctionName(std::string("unary")+Opcode));
660 Function *F = TheModule->getFunction(std::string("unary")+Opcode);
[all...] |
| /external/llvm/examples/Kaleidoscope/MCJIT/lazy/ |
| toy-jit.cpp | 137 char Opcode;
140 UnaryExprAST(char opcode, ExprAST *operand)
141 : Opcode(opcode), Operand(operand) {}
643 Function *F = TheHelper->getFunction(MakeLegalFunctionName(std::string("unary")+Opcode));
645 Function *F = TheModule->getFunction(std::string("unary")+Opcode);
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineLICM.cpp | 110 // For each opcode, keep a list of potential CSE instructions.
[all...] |
| TargetInstrInfo.cpp | 451 llvm_unreachable("unexpected stackmap opcode");
590 // If only one operand has the same opcode and it's the second source operand,
722 unsigned Opcode = Root.getOpcode();
729 BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
733 BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 274 /// opcode to determine what register class is being generated.
297 unsigned Opcode = Node->getMachineOpcode();
298 if (Opcode == TargetOpcode::REG_SEQUENCE) {
307 const MCInstrDesc Desc = TII->get(Opcode);
[all...] |
| /external/llvm/lib/ExecutionEngine/RuntimeDyld/ |
| RuntimeDyldELF.cpp | [all...] |
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | 286 // Standard opcode lengths
425 uint64_t Temp, Opcode;
453 // If the line increment is out of range of a special opcode, we must encode
464 // Use DW_LNS_copy instead of a "line +0, addr +0" special opcode.
470 // Bias the opcode by the special opcode base.
475 // Try using a special opcode.
476 Opcode = Temp + AddrDelta * Params.DWARF2LineRange;
477 if (Opcode <= 255) {
478 OS << char(Opcode);
[all...] |
