| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 282 unsigned DestReg, unsigned SrcReg,
296 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
298 .addReg(SrcReg, getKillRegState(KillSrc));
299 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) {
304 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
306 .addReg(SrcReg, getKillRegState(KillSrc));
307 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
310 .addReg(SrcReg, getKillRegState(KillSrc));
317 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
321 .addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
| /external/mesa3d/src/mesa/program/ |
| prog_print.c | 594 const struct prog_src_register *srcReg,
598 const char *abs = srcReg->Abs ? "|" : "";
602 reg_string((gl_register_file) srcReg->File,
603 srcReg->Index, mode, srcReg->RelAddr, prog,
604 srcReg->HasIndex2, srcReg->RelAddr2, srcReg->Index2),
605 _mesa_swizzle_string(srcReg->Swizzle,
606 srcReg->Negate, GL_FALSE)
[all...] |
| prog_instruction.c | 46 inst[i].SrcReg[0].File = PROGRAM_UNDEFINED;
47 inst[i].SrcReg[0].Swizzle = SWIZZLE_NOOP;
48 inst[i].SrcReg[1].File = PROGRAM_UNDEFINED;
49 inst[i].SrcReg[1].Swizzle = SWIZZLE_NOOP;
50 inst[i].SrcReg[2].File = PROGRAM_UNDEFINED;
51 inst[i].SrcReg[2].Swizzle = SWIZZLE_NOOP;
318 if (inst->SrcReg[i].File == inst->DstReg.File &&
319 inst->SrcReg[i].Index == inst->DstReg.Index) {
325 GLuint swizzle = GET_SWZ(inst->SrcReg[i].Swizzle, chan);
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_wm_fp.c | 226 inst->SrcReg[0] = src0;
227 inst->SrcReg[1] = src1;
228 inst->SrcReg[2] = src2;
559 struct prog_src_register src0 = inst->SrcReg[0];
560 struct prog_src_register src1 = inst->SrcReg[1];
590 swz->SrcReg[0].Negate &= ~NEGATE_X;
623 struct prog_src_register src0 = inst->SrcReg[0];
649 swz->SrcReg[0].Negate = NEGATE_NONE;
688 struct prog_src_register src0 = inst->SrcReg[0];
701 out->SrcReg[0].Negate = NEGATE_NONE
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_dataflow_deadcode.c | 43 unsigned char SrcReg[3];
186 unsigned int newsrcmask = srcmasks[src] & ~insts->SrcReg[src];
187 insts->SrcReg[src] |= newsrcmask;
191 refmask |= 1 << GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan);
200 mark_used(s, inst->U.I.SrcReg[src].File, inst->U.I.SrcReg[src].Index, refmask);
202 if (inst->U.I.SrcReg[src].RelAddr)
260 ptr->U.I.SrcReg[src].File,
261 ptr->U.I.SrcReg[src].Index,
353 SET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan, RC_SWIZZLE_UNUSED)
[all...] |
| r500_fragprog.c | 56 var_list, inst_if->Type, &inst_if->U.I.SrcReg[0]);
99 if (GET_SWZ(inst_if->U.I.SrcReg[0].Swizzle, 0) == RC_SWIZZLE_X) {
113 inst_mov->U.I.SrcReg[0] = inst_if->U.I.SrcReg[0];
115 inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4(
116 inst_mov->U.I.SrcReg[0].Swizzle,
120 inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4(
121 inst_mov->U.I.SrcReg[0].Swizzle,
165 temp_src = writer->Inst->U.I.SrcReg[0];
166 writer->Inst->U.I.SrcReg[0]
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 181 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
193 SrcReg = MCI.getOperand(1).getReg();
197 if (HexagonMCInstrInfo::isIntReg(SrcReg) &&
198 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
202 if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
211 SrcReg = MCI.getOperand(1).getReg();
213 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
232 SrcReg = MCI.getOperand(1).getReg();
234 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
242 SrcReg = MCI.getOperand(1).getReg()
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrFormats.td | 30 def SrcReg : SourceMode<0>;
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
110 : IForm8<opcode, DstMem, SrcReg, Size4Bytes, outs, ins, asmstr, pattern>;
127 : IForm16<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
139 : IForm16<opcode, DstMem, SrcReg, Size4Bytes, outs, ins, asmstr, pattern>;
169 : IIForm8<opcode, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
186 : IIForm16<opcode, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
|
| MSP430InstrInfo.cpp | 39 unsigned SrcReg, bool isKill, int FrameIdx,
55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
91 unsigned DestReg, unsigned SrcReg,
94 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
96 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
102 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCMIPeephole.cpp | 59 // Find the "true" register represented by SrcReg (following chains
61 unsigned lookThruCopyLike(unsigned SrcReg);
193 // the original SrcReg unless it is the target of a copy-like
197 unsigned PPCMIPeephole::lookThruCopyLike(unsigned SrcReg) {
201 MachineInstr *MI = MRI->getVRegDef(SrcReg);
203 return SrcReg;
216 SrcReg = CopySrcReg;
|
| PPCFastISel.cpp | 159 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
163 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
174 unsigned SrcReg, bool IsSigned);
175 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
606 // Emit a store instruction to store SrcReg at Addr.
607 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
608 assert(SrcReg && "Nothing to store!");
612 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
647 bool IsVSSRC = isVSSRCRegister(SrcReg);
648 bool IsVSFRC = isVSFRCRegister(SrcReg);
[all...] |
| PPCInstrInfo.cpp | 248 unsigned &SrcReg, unsigned &DstReg,
254 SrcReg = MI.getOperand(1).getReg();
816 unsigned DestReg, unsigned SrcReg,
822 PPC::VSRCRegClass.contains(SrcReg)) {
826 if (VSXSelfCopyCrash && SrcReg == SuperReg)
831 PPC::VSRCRegClass.contains(SrcReg)) {
835 if (VSXSelfCopyCrash && SrcReg == SuperReg)
839 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
842 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
847 SrcReg = SuperReg
[all...] |
| PPCInstrInfo.h | 72 unsigned SrcReg, bool isKill, int FrameIdx,
153 unsigned &SrcReg, unsigned &DstReg,
186 unsigned DestReg, unsigned SrcReg,
191 unsigned SrcReg, bool isKill, int FrameIndex,
252 unsigned &SrcReg, unsigned &SrcReg2,
256 unsigned SrcReg, unsigned SrcReg2,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.h | 52 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
113 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
117 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
121 MachineBasicBlock::iterator MBBI, unsigned SrcReg,
155 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
157 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
162 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
198 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
203 DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
|
| /external/llvm/lib/CodeGen/ |
| PHIElimination.cpp | 361 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
364 isImplicitlyDefined(SrcReg, MRI);
365 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
381 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
395 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
401 .addReg(SrcReg, 0, SrcSubReg);
405 // We only need to update the LiveVariables kill of SrcReg if this was the
406 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
409 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
410 !LV->isLiveOut(SrcReg, opBlock))
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFInstrInfo.cpp | 36 unsigned DestReg, unsigned SrcReg,
38 if (BPF::GPRRegClass.contains(DestReg, SrcReg))
40 .addReg(SrcReg, getKillRegState(KillSrc));
47 unsigned SrcReg, bool IsKill, int FI,
56 .addReg(SrcReg, getKillRegState(IsKill))
|
| BPFInstrInfo.h | 34 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
38 MachineBasicBlock::iterator MBBI, unsigned SrcReg,
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.h | 44 * unsigned SrcReg, bool isKill, int FrameIndex,
54 unsigned DestReg, unsigned SrcReg, bool KillSrc) const override;
55 virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.cpp | 39 unsigned DestReg, unsigned SrcReg,
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
49 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 598 unsigned SrcReg, bool KillSrc) const {
600 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
601 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
604 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
605 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
608 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
611 DestReg).addReg(SrcReg).addReg(SrcReg);
615 Hexagon::IntRegsRegClass.contains(SrcReg)) {
617 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg))
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.h | 43 unsigned DestReg, unsigned SrcReg,
47 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/x86/ |
| vp9_subpixel_8t_intrin_ssse3.c | 49 __m128i addFilterReg64, filtersReg, srcReg, minReg;
73 srcReg = _mm_loadu_si128((__m128i *)(src_ptr-3));
76 srcRegFilt1= _mm_shuffle_epi8(srcReg, thirdFilters);
77 srcRegFilt2= _mm_shuffle_epi8(srcReg, forthFilters);
116 __m128i firstFilters, secondFilters, thirdFilters, forthFilters, srcReg;
148 srcReg = _mm_loadu_si128((__m128i *)(src_ptr-3));
151 srcRegFilt1= _mm_shuffle_epi8(srcReg, filt1Reg);
152 srcRegFilt2= _mm_shuffle_epi8(srcReg, filt2Reg);
159 srcRegFilt3= _mm_shuffle_epi8(srcReg, filt3Reg);
160 srcRegFilt4= _mm_shuffle_epi8(srcReg, filt4Reg)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.h | 132 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
154 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
156 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
171 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
175 unsigned SrcReg, bool isKill, int FrameIndex,
|
| SystemZInstrInfo.cpp | 126 unsigned SrcReg = MI->getOperand(1).getReg();
128 bool SrcIsHigh = isHighReg(SrcReg);
133 DestReg, SrcReg, SystemZ::LR, 32,
163 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
164 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
166 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
167 // KillSrc is true if this move is the last use of SrcReg.
171 unsigned SrcReg, unsigned LowLowOpcode,
175 bool SrcIsHigh = isHighReg(SrcReg);
184 .addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
| SystemZElimCompare.cpp | 201 unsigned SrcReg = getCompareSourceReg(Compare);
204 if (getRegReferences(MBBI, SrcReg))
341 unsigned SrcReg = getCompareSourceReg(Compare);
349 if (resultTests(MI, SrcReg)) {
364 SrcRefs |= getRegReferences(MI, SrcReg);
393 unsigned SrcReg = Compare->getOperand(0).getReg();
398 if (MBBI->modifiesRegister(SrcReg, TRI) ||
425 // Clear any intervening kills of SrcReg and SrcReg2.
428 MBBI->clearRegisterKills(SrcReg, TRI);
|
