| /external/llvm/lib/Target/X86/ |
| X86CallingConv.td | 68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
122 CCIfType<[v16f32, v8f64, v16i32, v8i64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
312 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
332 CCIfType<[v16i32, v8i64, v16f32, v8f64],
372 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
415 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
490 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
507 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
526 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64]
[all...] |
| X86TargetTransformInfo.cpp | 138 { ISD::SHL, MVT::v8i64, 1 },
139 { ISD::SRL, MVT::v8i64, 1 },
140 { ISD::SRA, MVT::v8i64, 1 },
537 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 },
540 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 },
544 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 },
547 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 },
557 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 },
558 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 },
568 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }
[all...] |
| X86InstrFragmentsSIMD.td | [all...] |
| X86ISelLowering.cpp | [all...] |
| X86InstrAVX512.td | 83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
376 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
381 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
386 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
387 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
388 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
389 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>
[all...] |
| X86RegisterInfo.td | 465 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 98 v8i64 = 48, // 8 x i64 enumerator in enum:llvm::MVT::SimpleValueType
260 SimpleTy == MVT::v8i64);
345 case v8i64:
392 case v8i64:
493 case v8i64:
629 if (NumElements == 8) return MVT::v8i64;
|
| ValueTypes.td | 75 def v8i64 : ValueType<512, 48>; // 8 x i64 vector value
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 205 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
206 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
207 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
208 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
395 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost },
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 91 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
92 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
93 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
94 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
278 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
|
| ARMRegisterInfo.td | 398 def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> {
|
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/test/CodeGen/X86/ |
| vector-lzcnt-512.ll | 9 %out = call <8 x i64> @llvm.ctlz.v8i64(<8 x i64> %in, i1 0)
18 %out = call <8 x i64> @llvm.ctlz.v8i64(<8 x i64> %in, i1 -1)
216 declare <8 x i64> @llvm.ctlz.v8i64(<8 x i64>, i1)
|
| vector-popcnt-512.ll | 42 %out = call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %in)
158 declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>)
|
| vector-tzcnt-512.ll | 42 %out = call <8 x i64> @llvm.cttz.v8i64(<8 x i64> %in, i1 0)
56 %out = call <8 x i64> @llvm.cttz.v8i64(<8 x i64> %in, i1 -1)
268 declare <8 x i64> @llvm.cttz.v8i64(<8 x i64>, i1)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonIntrinsicsV60.td | 97 def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))),
98 (v512i1 (V6_vandvrt(v8i64 VectorRegs:$src1),
117 def : Pat <(v8i64 (bitconvert (v512i1 VecPredRegs:$src1))),
118 (v8i64 (V6_vandqrt(v512i1 VecPredRegs:$src1),
[all...] |
| HexagonISelLowering.cpp | 197 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
337 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
410 LocVT == MVT::v16i32 || LocVT == MVT::v8i64 ||
544 return (ty == MVT::v8i64 || ty == MVT::v16i32 || ty == MVT::v32i16 ||
[all...] |
| HexagonRegisterInfo.td | 217 def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512,
|
| HexagonISelDAGToDAG.cpp | 405 } else if (LoadedVT == MVT::v16i32 || LoadedVT == MVT::v8i64 ||
526 else if (StoredVT == MVT::v16i32 || StoredVT == MVT::v8i64 ||
568 else if (StoredVT == MVT::v16i32 || StoredVT == MVT::v8i64 ||
[all...] |
| HexagonInstrInfoVector.td | 79 defm : bitconvert_vec<v8i64 , v16i32>;
|
| HexagonInstrInfoV60.td | [all...] |
| /external/llvm/test/CodeGen/AMDGPU/ |
| ctpop64.ll | 7 declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>) nounwind readnone
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 175 case MVT::v8i64: return "v8i64";
253 case MVT::v8i64: return VectorType::get(Type::getInt64Ty(Context), 8);
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 108 case MVT::v8i64: return "MVT::v8i64";
|
| /external/llvm/include/llvm/IR/ |
| Intrinsics.td | 197 def llvm_v8i64_ty : LLVMType<v8i64>; // 8 x i64
|
