| /external/llvm/test/CodeGen/AMDGPU/ |
| build_vector.ll | 10 ; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
11 ; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
26 ; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
27 ; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
28 ; SI-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
29 ; SI-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
|
| atomic_cmp_swap_local.ll | 6 ; GCN: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
11 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
12 ; GCN-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
24 ; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
25 ; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
30 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
31 ; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
32 ; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
63 ; GCN-DAG: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
64 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]
[all...] |
| i1-copy-phi.ll | 5 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
8 ; SI: v_mov_b32_e32 [[REG]], -1{{$}}
|
| trunc-store-i1.ll | 8 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
27 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
|
| imm.ll | 6 ; CHECK: v_mov_b32_e32 v[[LO_VGPR:[0-9]+]], 5
16 ; CHECK: v_mov_b32_e32 v[[HI_VGPR:[0-9]+]], 5
25 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
26 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x80000000
34 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
42 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
50 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
58 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}}
66 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}}
74 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}
[all...] |
| gep-address-space.ll | 7 ; CHECK: v_mov_b32_e32 [[PTR:v[0-9]+]], s{{[0-9]+}}
32 ; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
33 ; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
34 ; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
35 ; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
58 ; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
59 ; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
|
| indirect-addressing-si.ll | 8 ; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, 4.0
9 ; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40400000
10 ; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, 2.0
11 ; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, 1.0
28 ; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
29 ; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
30 ; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
31 ; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
44 ; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, 4.0
45 ; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x4040000
[all...] |
| coalescer_remat.ll | 10 ; CHECK: v_mov_b32_e32 v{{[0-9]+}}, 0
11 ; CHECK: v_mov_b32_e32 v{{[0-9]+}}, 0
12 ; CHECK: v_mov_b32_e32 v{{[0-9]+}}, 0
13 ; CHECK: v_mov_b32_e32 v{{[0-9]+}}, 0
|
| infinite-loop.ll | 5 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7
|
| si-literal-folding.ll | 5 ; CHECK-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0xbf4353f8
|
| llvm.r600.read.local.size.ll | 15 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
30 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
45 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
59 ; GCN-DAG: v_mov_b32_e32 [[VY:v[0-9]+]], [[Y]]
78 ; GCN-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
98 ; GCN-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
120 ; GCN-DAG: v_mov_b32_e32 [[VY:v[0-9]+]], [[Y]]
121 ; GCN-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
139 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
154 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]
[all...] |
| 32-bit-local-address-space.ll | 25 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
36 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
49 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
84 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
112 ; SI: v_mov_b32_e32 [[ADDR:v[0-9]+]], [[SADDR]]
121 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
122 ; SI: v_mov_b32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
133 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
|
| invariant-load-no-alias-store.ll | 11 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x1c8007b
23 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x1c8007b
|
| move-addr64-rsrc-dead-subreg-writes.ll | 13 ; GCN: v_mov_b32_e32 v[[VARG1LO:[0-9]+]], s[[ARG1LO]]
14 ; GCN-NEXT: v_mov_b32_e32 v[[VARG1HI:[0-9]+]], s[[ARG1HI]]
|
| subreg-coalescer-undef-use.ll | 10 ; CHECK-NEXT: v_mov_b32_e32 v0, s2
16 ; CHECK-NEXT: v_mov_b32_e32 v0, s6
|
| llvm.AMDGPU.fract.f64.ll | 10 ; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
11 ; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
27 ; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
28 ; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
45 ; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
46 ; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
|
| fneg-fabs.f64.ll | 47 ; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
60 ; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
62 ; SI-DAG: v_mov_b32_e32 v[[LO_V:[0-9]+]], s[[LO_X]]
72 ; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
84 ; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
|
| llvm.AMDGPU.bfe.i32.ll | 88 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
183 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
195 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
207 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
219 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
231 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
243 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
255 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0xffffff80
267 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f
279 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]],
[all...] |
| trunc.ll | 9 ; SI: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]
25 ; SI: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]
39 ; SI: v_mov_b32_e32
40 ; SI: v_mov_b32_e32
41 ; SI: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]
|
| use-sgpr-multiple-times.ll | 35 ; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
53 ; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
75 ; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
89 ; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
131 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000
142 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000
154 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000
170 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000
182 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000
198 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x4480000
[all...] |
| fcopysign.f64.ll | 13 ; GCN-DAG: v_mov_b32_e32 v[[VSIGN_HI:[0-9]+]], s[[SSIGN_HI]]
14 ; GCN-DAG: v_mov_b32_e32 v[[VMAG_HI:[0-9]+]], s[[SMAG_HI]]
17 ; GCN: v_mov_b32_e32 v[[VMAG_LO:[0-9]+]], s[[SMAG_LO]]
|
| work-item-intrinsics.ll | 29 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
45 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
60 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
75 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
90 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
105 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
130 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s2{{$}}
131 ; HSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s6{{$}}
156 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s3
157 ; GCN-HSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s
[all...] |
| llvm.AMDGPU.div_fixup.ll | 14 ; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
15 ; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
|
| llvm.AMDGPU.read.workdim.ll | 11 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
24 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
|
| address-space.ll | 10 ; CHECK: v_mov_b32_e32 [[VREG1:v[0-9]+]], [[SREG1]]
|
