1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Interface definition for SIRegisterInfo 12 // 13 //===----------------------------------------------------------------------===// 14 15 16 #ifndef LLVM_LIB_TARGET_R600_SIREGISTERINFO_H 17 #define LLVM_LIB_TARGET_R600_SIREGISTERINFO_H 18 19 #include "AMDGPURegisterInfo.h" 20 #include "AMDGPUSubtarget.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/Support/Debug.h" 23 24 namespace llvm { 25 26 struct SIRegisterInfo : public AMDGPURegisterInfo { 27 private: 28 void reserveRegisterTuples(BitVector &, unsigned Reg) const; 29 30 public: 31 SIRegisterInfo(); 32 33 /// Return the end register initially reserved for the scratch buffer in case 34 /// spilling is needed. 35 unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const; 36 37 /// Return the end register initially reserved for the scratch wave offset in 38 /// case spilling is needed. 39 unsigned reservedPrivateSegmentWaveByteOffsetReg( 40 const MachineFunction &MF) const; 41 42 BitVector getReservedRegs(const MachineFunction &MF) const override; 43 44 unsigned getRegPressureSetLimit(const MachineFunction &MF, 45 unsigned Idx) const override; 46 47 bool requiresRegisterScavenging(const MachineFunction &Fn) const override; 48 49 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, 50 unsigned FIOperandNum, 51 RegScavenger *RS) const override; 52 53 unsigned getHWRegIndex(unsigned Reg) const override; 54 55 /// \brief Return the 'base' register class for this register. 56 /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc. 57 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const; 58 59 /// \returns true if this class contains only SGPR registers 60 bool isSGPRClass(const TargetRegisterClass *RC) const { 61 return !hasVGPRs(RC); 62 } 63 64 /// \returns true if this class ID contains only SGPR registers 65 bool isSGPRClassID(unsigned RCID) const { 66 return isSGPRClass(getRegClass(RCID)); 67 } 68 69 bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const { 70 if (TargetRegisterInfo::isVirtualRegister(Reg)) 71 return isSGPRClass(MRI.getRegClass(Reg)); 72 return getPhysRegClass(Reg); 73 } 74 75 /// \returns true if this class contains VGPR registers. 76 bool hasVGPRs(const TargetRegisterClass *RC) const; 77 78 /// returns true if this is a pseudoregister class combination of VGPRs and 79 /// SGPRs for operand modeling. FIXME: We should set isAllocatable = 0 on 80 /// them. 81 static bool isPseudoRegClass(const TargetRegisterClass *RC) { 82 return RC == &AMDGPU::VS_32RegClass || RC == &AMDGPU::VS_64RegClass; 83 } 84 85 /// \returns A VGPR reg class with the same width as \p SRC 86 const TargetRegisterClass *getEquivalentVGPRClass( 87 const TargetRegisterClass *SRC) const; 88 89 /// \returns The register class that is used for a sub-register of \p RC for 90 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will 91 /// be returned. 92 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC, 93 unsigned SubIdx) const; 94 95 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, 96 unsigned DefSubReg, 97 const TargetRegisterClass *SrcRC, 98 unsigned SrcSubReg) const override; 99 100 /// \p Channel This is the register channel (e.g. a value from 0-16), not the 101 /// SubReg index. 102 /// \returns The sub-register of Reg that is in Channel. 103 unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC, 104 unsigned Channel) const; 105 106 /// \returns True if operands defined with this operand type can accept 107 /// a literal constant (i.e. any 32-bit immediate). 108 bool opCanUseLiteralConstant(unsigned OpType) const; 109 110 /// \returns True if operands defined with this operand type can accept 111 /// an inline constant. i.e. An integer value in the range (-16, 64) or 112 /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f. 113 bool opCanUseInlineConstant(unsigned OpType) const; 114 115 enum PreloadedValue { 116 // SGPRS: 117 PRIVATE_SEGMENT_BUFFER = 0, 118 DISPATCH_PTR = 1, 119 QUEUE_PTR = 2, 120 KERNARG_SEGMENT_PTR = 3, 121 WORKGROUP_ID_X = 10, 122 WORKGROUP_ID_Y = 11, 123 WORKGROUP_ID_Z = 12, 124 PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = 14, 125 126 // VGPRS: 127 FIRST_VGPR_VALUE = 15, 128 WORKITEM_ID_X = FIRST_VGPR_VALUE, 129 WORKITEM_ID_Y = 16, 130 WORKITEM_ID_Z = 17 131 }; 132 133 /// \brief Returns the physical register that \p Value is stored in. 134 unsigned getPreloadedValue(const MachineFunction &MF, 135 enum PreloadedValue Value) const; 136 137 /// \brief Give the maximum number of VGPRs that can be used by \p WaveCount 138 /// concurrent waves. 139 unsigned getNumVGPRsAllowed(unsigned WaveCount) const; 140 141 /// \brief Give the maximum number of SGPRs that can be used by \p WaveCount 142 /// concurrent waves. 143 unsigned getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen, 144 unsigned WaveCount) const; 145 146 unsigned findUnusedRegister(const MachineRegisterInfo &MRI, 147 const TargetRegisterClass *RC) const; 148 149 private: 150 void buildScratchLoadStore(MachineBasicBlock::iterator MI, 151 unsigned LoadStoreOp, unsigned Value, 152 unsigned ScratchRsrcReg, unsigned ScratchOffset, 153 int64_t Offset, RegScavenger *RS) const; 154 }; 155 156 } // End namespace llvm 157 158 #endif 159
