| /external/v8/test/cctest/ |
| test-disasm-arm.cc | 108 COMPARE(and_(r2, r3, Operand(r4), SetCC),
115 COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC),
119 COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs),
124 COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc),
128 COMPARE(sub(r5, r6, Operand(r10, LSL, 16), SetCC, mi),
135 COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC),
144 COMPARE(add(r7, r8, Operand(ip), SetCC),
146 COMPARE(add(r7, r8, Operand(ip, ASR, 31), SetCC, vs),
153 COMPARE(adc(r5, sp, Operand(ip), SetCC),
155 COMPARE(adc(r8, lr, Operand(ip, ASR, 31), SetCC, vc)
[all...] |
| test-assembler-ppc.cc | 1000 __ mov(r1, Operand(r1, ASR, 1), SetCC);
1005 __ mov(r2, Operand(r2, ASR, 1), SetCC);
1012 __ mov(r3, Operand(r1, ASR, 1), SetCC); // Set the carry.
1018 __ mov(r3, Operand(r2, ASR, 1), SetCC); // Unset the carry.
|
| test-assembler-arm.cc | 966 __ mov(r1, Operand(r1, ASR, 1), SetCC);
971 __ mov(r2, Operand(r2, ASR, 1), SetCC);
978 __ mov(r3, Operand(r1, ASR, 1), SetCC); // Set the carry.
984 __ mov(r3, Operand(r2, ASR, 1), SetCC); // Unset the carry.
[all...] |
| /external/v8/src/arm/ |
| builtins-arm.cc | 150 __ sub(r0, r0, Operand(1), SetCC);
242 __ sub(r0, r0, Operand(1), SetCC);
276 __ sub(r0, r0, Operand(1), SetCC);
341 __ sub(r0, r0, Operand(1), SetCC);
400 __ sub(r0, r0, Operand(1), SetCC);
585 __ sub(r4, r4, Operand(2), SetCC);
750 __ sub(r3, r3, Operand(Smi::FromInt(1)), SetCC);
[all...] |
| codegen-arm.cc | 79 __ sub(chars, chars, Operand(64), SetCC);
138 __ bic(temp1, chars, Operand(0x3), SetCC);
146 __ bic(temp2, chars, Operand(0x3), SetCC);
158 __ mov(chars, Operand(chars, LSL, 31), SetCC);
242 __ mov(chars, Operand(chars, LSL, 31), SetCC); // bit0 => ne, bit1 => cs
|
| macro-assembler-arm.cc | [all...] |
| code-stubs-arm.cc | 144 __ rsb(scratch, scratch, Operand(51), SetCC);
278 __ orr(r0, r3, Operand(r2), SetCC);
842 __ mov(scratch, Operand(scratch, ASR, 1), SetCC);
[all...] |
| constants-arm.h | 243 SetCC = 1 << 20, // Set condition code.
|
| macro-assembler-arm.h | [all...] |
| /external/v8/src/compiler/arm/ |
| code-generator-arm.cc | 35 return SetCC;
858 DCHECK_EQ(SetCC, i.OutputSBit());
862 DCHECK_EQ(SetCC, i.OutputSBit());
866 DCHECK_EQ(SetCC, i.OutputSBit());
870 DCHECK_EQ(SetCC, i.OutputSBit());
878 SBit::SetCC);
889 SBit::SetCC);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 229 // setcc operations results (slt, sgt, ...).
264 // Used by legalize types to correctly generate the setcc result.
265 // Without this, every float setcc comes with a AND/OR with the result,
268 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
282 setOperationAction(ISD::SETCC, MVT::f32, Custom);
283 setOperationAction(ISD::SETCC, MVT::f64, Custom);
546 // Creates and returns an FPCmp node from a setcc node.
547 // Returns Op if setcc is not a floating point comparison.
549 // must be a SETCC node
550 if (Op.getOpcode() != ISD::SETCC)
[all...] |
| MipsSEISelLowering.cpp | 79 setTargetDAGCombine(ISD::SETCC);
175 setOperationAction(ISD::SETCC, MVT::i32, Legal);
179 setOperationAction(ISD::SETCC, MVT::f32, Legal);
184 setOperationAction(ISD::SETCC, MVT::f64, Legal);
222 setOperationAction(ISD::SETCC, MVT::i64, Legal);
285 setOperationAction(ISD::SETCC, Ty, Legal);
322 setOperationAction(ISD::SETCC, Ty, Legal);
[all...] |
| /external/v8/src/regexp/arm/ |
| regexp-macro-assembler-arm.cc | 216 __ sub(r1, r1, r0, SetCC); // Length of capture.
359 __ sub(r1, r1, r0, SetCC); // Length to check.
656 __ sub(r0, sp, r0, SetCC);
719 __ sub(r2, r2, Operand(1), SetCC);
[all...] |
| /external/v8/src/crankshaft/arm/ |
| lithium-codegen-arm.cc | 798 __ sub(r1, r1, Operand(1), SetCC);
985 __ rsb(dividend, dividend, Operand::Zero(), SetCC);
[all...] |
| /external/v8/src/x87/ |
| disasm-x87.cc | 325 int SetCC(byte* data);
648 int DisassemblerX87::SetCC(byte* data) {
[all...] |
| /external/v8/src/ia32/ |
| disasm-ia32.cc | 388 int SetCC(byte* data);
712 int DisassemblerIA32::SetCC(byte* data) {
[all...] |
| /external/v8/src/x64/ |
| disasm-x64.cc | 477 int SetCC(byte* data);
869 int DisassemblerX64::SetCC(byte* data) {
[all...] |
| /external/v8/src/full-codegen/arm/ |
| full-codegen-arm.cc | 156 __ sub(r2, r2, Operand(1), SetCC);
355 __ sub(r3, r3, Operand(Smi::FromInt(delta)), SetCC);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 106 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
107 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
263 setTargetDAGCombine(ISD::SETCC);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 711 // Return true if this node is a setcc, or is a select_cc
713 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
718 if (N.getOpcode() == ISD::SETCC) {
740 /// Return true if this is a SetCC-equivalent operation with only one use.
[all...] |
| LegalizeIntegerTypes.cpp | 77 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
573 // Promote all the way up to the canonical SetCC type.
614 // Get the SETCC result using the canonical SETCC type.
615 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
620 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
[all...] |
| LegalizeDAG.cpp | 55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
421 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
422 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
423 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
424 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
425 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
426 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
427 setOperationAction(ISD::SETCC , MVT::f128 , Custom);
433 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 69 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
114 setOperationAction(ISD::SETCC, MVT::i32, Custom);
115 setOperationAction(ISD::SETCC, MVT::i64, Custom);
116 setOperationAction(ISD::SETCC, MVT::f32, Custom);
117 setOperationAction(ISD::SETCC, MVT::f64, Custom);
165 setOperationAction(ISD::SETCC, MVT::f128, Custom);
275 setOperationAction(ISD::SETCC, MVT::f16, Promote);
345 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
378 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
550 setOperationAction(ISD::SETCC, MVT::v1f64, Expand)
[all...] |
| /art/compiler/utils/x86_64/ |
| assembler_x86_64_test.cc | [all...] |
