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      1 //===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 // This pass replaces transfer instructions by combine instructions.
     10 // We walk along a basic block and look for two combinable instructions and try
     11 // to move them together. If we can move them next to each other we do so and
     12 // replace them with a combine instruction.
     13 //===----------------------------------------------------------------------===//
     14 #include "llvm/PassSupport.h"
     15 #include "Hexagon.h"
     16 #include "HexagonInstrInfo.h"
     17 #include "HexagonMachineFunctionInfo.h"
     18 #include "HexagonRegisterInfo.h"
     19 #include "HexagonSubtarget.h"
     20 #include "HexagonTargetMachine.h"
     21 #include "llvm/ADT/DenseMap.h"
     22 #include "llvm/ADT/DenseSet.h"
     23 #include "llvm/CodeGen/MachineBasicBlock.h"
     24 #include "llvm/CodeGen/MachineFunction.h"
     25 #include "llvm/CodeGen/MachineFunctionPass.h"
     26 #include "llvm/CodeGen/MachineInstr.h"
     27 #include "llvm/CodeGen/MachineInstrBuilder.h"
     28 #include "llvm/CodeGen/Passes.h"
     29 #include "llvm/Support/CodeGen.h"
     30 #include "llvm/Support/CommandLine.h"
     31 #include "llvm/Support/Debug.h"
     32 #include "llvm/Support/raw_ostream.h"
     33 #include "llvm/Target/TargetRegisterInfo.h"
     34 
     35 using namespace llvm;
     36 
     37 #define DEBUG_TYPE "hexagon-copy-combine"
     38 
     39 static
     40 cl::opt<bool> IsCombinesDisabled("disable-merge-into-combines",
     41                                  cl::Hidden, cl::ZeroOrMore,
     42                                  cl::init(false),
     43                                  cl::desc("Disable merging into combines"));
     44 static
     45 cl::opt<unsigned>
     46 MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store",
     47                    cl::Hidden, cl::init(4),
     48                    cl::desc("Maximum distance between a tfr feeding a store we "
     49                             "consider the store still to be newifiable"));
     50 
     51 namespace llvm {
     52   FunctionPass *createHexagonCopyToCombine();
     53   void initializeHexagonCopyToCombinePass(PassRegistry&);
     54 }
     55 
     56 
     57 namespace {
     58 
     59 class HexagonCopyToCombine : public MachineFunctionPass  {
     60   const HexagonInstrInfo *TII;
     61   const TargetRegisterInfo *TRI;
     62   bool ShouldCombineAggressively;
     63 
     64   DenseSet<MachineInstr *> PotentiallyNewifiableTFR;
     65 public:
     66   static char ID;
     67 
     68   HexagonCopyToCombine() : MachineFunctionPass(ID) {
     69     initializeHexagonCopyToCombinePass(*PassRegistry::getPassRegistry());
     70   }
     71 
     72   void getAnalysisUsage(AnalysisUsage &AU) const override {
     73     MachineFunctionPass::getAnalysisUsage(AU);
     74   }
     75 
     76   const char *getPassName() const override {
     77     return "Hexagon Copy-To-Combine Pass";
     78   }
     79 
     80   bool runOnMachineFunction(MachineFunction &Fn) override;
     81 
     82 private:
     83   MachineInstr *findPairable(MachineInstr *I1, bool &DoInsertAtI1);
     84 
     85   void findPotentialNewifiableTFRs(MachineBasicBlock &);
     86 
     87   void combine(MachineInstr *I1, MachineInstr *I2,
     88                MachineBasicBlock::iterator &MI, bool DoInsertAtI1);
     89 
     90   bool isSafeToMoveTogether(MachineInstr *I1, MachineInstr *I2,
     91                             unsigned I1DestReg, unsigned I2DestReg,
     92                             bool &DoInsertAtI1);
     93 
     94   void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
     95                      MachineOperand &HiOperand, MachineOperand &LoOperand);
     96 
     97   void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
     98                      MachineOperand &HiOperand, MachineOperand &LoOperand);
     99 
    100   void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
    101                      MachineOperand &HiOperand, MachineOperand &LoOperand);
    102 
    103   void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
    104                      MachineOperand &HiOperand, MachineOperand &LoOperand);
    105 };
    106 
    107 } // End anonymous namespace.
    108 
    109 char HexagonCopyToCombine::ID = 0;
    110 
    111 INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine",
    112                 "Hexagon Copy-To-Combine Pass", false, false)
    113 
    114 static bool isCombinableInstType(MachineInstr *MI,
    115                                  const HexagonInstrInfo *TII,
    116                                  bool ShouldCombineAggressively) {
    117   switch(MI->getOpcode()) {
    118   case Hexagon::A2_tfr: {
    119     // A COPY instruction can be combined if its arguments are IntRegs (32bit).
    120     const MachineOperand &Op0 = MI->getOperand(0);
    121     const MachineOperand &Op1 = MI->getOperand(1);
    122     assert(Op0.isReg() && Op1.isReg());
    123 
    124     unsigned DestReg = Op0.getReg();
    125     unsigned SrcReg = Op1.getReg();
    126     return Hexagon::IntRegsRegClass.contains(DestReg) &&
    127            Hexagon::IntRegsRegClass.contains(SrcReg);
    128   }
    129 
    130   case Hexagon::A2_tfrsi: {
    131     // A transfer-immediate can be combined if its argument is a signed 8bit
    132     // value.
    133     const MachineOperand &Op0 = MI->getOperand(0);
    134     const MachineOperand &Op1 = MI->getOperand(1);
    135     assert(Op0.isReg());
    136 
    137     unsigned DestReg = Op0.getReg();
    138     // Ensure that TargetFlags are MO_NO_FLAG for a global. This is a
    139     // workaround for an ABI bug that prevents GOT relocations on combine
    140     // instructions
    141     if (!Op1.isImm() && Op1.getTargetFlags() != HexagonII::MO_NO_FLAG)
    142       return false;
    143 
    144     // Only combine constant extended A2_tfrsi if we are in aggressive mode.
    145     bool NotExt = Op1.isImm() && isInt<8>(Op1.getImm());
    146     return Hexagon::IntRegsRegClass.contains(DestReg) &&
    147            (ShouldCombineAggressively || NotExt);
    148   }
    149 
    150   default:
    151     break;
    152   }
    153 
    154   return false;
    155 }
    156 
    157 template <unsigned N>
    158 static bool isGreaterThanNBitTFRI(const MachineInstr *I) {
    159   if (I->getOpcode() == Hexagon::TFRI64_V4 ||
    160       I->getOpcode() == Hexagon::A2_tfrsi) {
    161     const MachineOperand &Op = I->getOperand(1);
    162     return !Op.isImm() || !isInt<N>(Op.getImm());
    163   }
    164   return false;
    165 }
    166 
    167 /// areCombinableOperations - Returns true if the two instruction can be merge
    168 /// into a combine (ignoring register constraints).
    169 static bool areCombinableOperations(const TargetRegisterInfo *TRI,
    170                                     MachineInstr *HighRegInst,
    171                                     MachineInstr *LowRegInst) {
    172   unsigned HiOpc = HighRegInst->getOpcode();
    173   unsigned LoOpc = LowRegInst->getOpcode();
    174   (void)HiOpc; // Fix compiler warning
    175   (void)LoOpc; // Fix compiler warning
    176   assert((HiOpc == Hexagon::A2_tfr || HiOpc == Hexagon::A2_tfrsi) &&
    177          (LoOpc == Hexagon::A2_tfr || LoOpc == Hexagon::A2_tfrsi) &&
    178          "Assume individual instructions are of a combinable type");
    179 
    180   // There is no combine of two constant extended values.
    181   if (isGreaterThanNBitTFRI<8>(HighRegInst) &&
    182       isGreaterThanNBitTFRI<6>(LowRegInst))
    183     return false;
    184 
    185   return true;
    186 }
    187 
    188 static bool isEvenReg(unsigned Reg) {
    189   assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
    190          Hexagon::IntRegsRegClass.contains(Reg));
    191   return (Reg - Hexagon::R0) % 2 == 0;
    192 }
    193 
    194 static void removeKillInfo(MachineInstr *MI, unsigned RegNotKilled) {
    195   for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
    196     MachineOperand &Op = MI->getOperand(I);
    197     if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
    198       continue;
    199     Op.setIsKill(false);
    200   }
    201 }
    202 
    203 /// isUnsafeToMoveAcross - Returns true if it is unsafe to move a copy
    204 /// instruction from \p UseReg to \p DestReg over the instruction \p I.
    205 static bool isUnsafeToMoveAcross(MachineInstr *I, unsigned UseReg,
    206                                   unsigned DestReg,
    207                                   const TargetRegisterInfo *TRI) {
    208   return (UseReg && (I->modifiesRegister(UseReg, TRI))) ||
    209          I->modifiesRegister(DestReg, TRI) ||
    210          I->readsRegister(DestReg, TRI) ||
    211          I->hasUnmodeledSideEffects() ||
    212          I->isInlineAsm() || I->isDebugValue();
    213 }
    214 
    215 static unsigned UseReg(const MachineOperand& MO) {
    216   return MO.isReg() ? MO.getReg() : 0;
    217 }
    218 
    219 /// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such
    220 /// that the two instructions can be paired in a combine.
    221 bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
    222                                                 MachineInstr *I2,
    223                                                 unsigned I1DestReg,
    224                                                 unsigned I2DestReg,
    225                                                 bool &DoInsertAtI1) {
    226   unsigned I2UseReg = UseReg(I2->getOperand(1));
    227 
    228   // It is not safe to move I1 and I2 into one combine if I2 has a true
    229   // dependence on I1.
    230   if (I2UseReg && I1->modifiesRegister(I2UseReg, TRI))
    231     return false;
    232 
    233   bool isSafe = true;
    234 
    235   // First try to move I2 towards I1.
    236   {
    237     // A reverse_iterator instantiated like below starts before I2, and I1
    238     // respectively.
    239     // Look at instructions I in between I2 and (excluding) I1.
    240     MachineBasicBlock::reverse_iterator I(I2),
    241       End = --(MachineBasicBlock::reverse_iterator(I1));
    242     // At 03 we got better results (dhrystone!) by being more conservative.
    243     if (!ShouldCombineAggressively)
    244       End = MachineBasicBlock::reverse_iterator(I1);
    245     // If I2 kills its operand and we move I2 over an instruction that also
    246     // uses I2's use reg we need to modify that (first) instruction to now kill
    247     // this reg.
    248     unsigned KilledOperand = 0;
    249     if (I2->killsRegister(I2UseReg))
    250       KilledOperand = I2UseReg;
    251     MachineInstr *KillingInstr = nullptr;
    252 
    253     for (; I != End; ++I) {
    254       // If the intervening instruction I:
    255       //   * modifies I2's use reg
    256       //   * modifies I2's def reg
    257       //   * reads I2's def reg
    258       //   * or has unmodelled side effects
    259       // we can't move I2 across it.
    260       if (isUnsafeToMoveAcross(&*I, I2UseReg, I2DestReg, TRI)) {
    261         isSafe = false;
    262         break;
    263       }
    264 
    265       // Update first use of the killed operand.
    266       if (!KillingInstr && KilledOperand &&
    267           I->readsRegister(KilledOperand, TRI))
    268         KillingInstr = &*I;
    269     }
    270     if (isSafe) {
    271       // Update the intermediate instruction to with the kill flag.
    272       if (KillingInstr) {
    273         bool Added = KillingInstr->addRegisterKilled(KilledOperand, TRI, true);
    274         (void)Added; // suppress compiler warning
    275         assert(Added && "Must successfully update kill flag");
    276         removeKillInfo(I2, KilledOperand);
    277       }
    278       DoInsertAtI1 = true;
    279       return true;
    280     }
    281   }
    282 
    283   // Try to move I1 towards I2.
    284   {
    285     // Look at instructions I in between I1 and (excluding) I2.
    286     MachineBasicBlock::iterator I(I1), End(I2);
    287     // At O3 we got better results (dhrystone) by being more conservative here.
    288     if (!ShouldCombineAggressively)
    289       End = std::next(MachineBasicBlock::iterator(I2));
    290     unsigned I1UseReg = UseReg(I1->getOperand(1));
    291     // Track killed operands. If we move across an instruction that kills our
    292     // operand, we need to update the kill information on the moved I1. It kills
    293     // the operand now.
    294     MachineInstr *KillingInstr = nullptr;
    295     unsigned KilledOperand = 0;
    296 
    297     while(++I != End) {
    298       // If the intervening instruction I:
    299       //   * modifies I1's use reg
    300       //   * modifies I1's def reg
    301       //   * reads I1's def reg
    302       //   * or has unmodelled side effects
    303       //   We introduce this special case because llvm has no api to remove a
    304       //   kill flag for a register (a removeRegisterKilled() analogous to
    305       //   addRegisterKilled) that handles aliased register correctly.
    306       //   * or has a killed aliased register use of I1's use reg
    307       //           %D4<def> = TFRI64 16
    308       //           %R6<def> = TFR %R9
    309       //           %R8<def> = KILL %R8, %D4<imp-use,kill>
    310       //      If we want to move R6 = across the KILL instruction we would have
    311       //      to remove the %D4<imp-use,kill> operand. For now, we are
    312       //      conservative and disallow the move.
    313       // we can't move I1 across it.
    314       if (isUnsafeToMoveAcross(I, I1UseReg, I1DestReg, TRI) ||
    315           // Check for an aliased register kill. Bail out if we see one.
    316           (!I->killsRegister(I1UseReg) && I->killsRegister(I1UseReg, TRI)))
    317         return false;
    318 
    319       // Check for an exact kill (registers match).
    320       if (I1UseReg && I->killsRegister(I1UseReg)) {
    321         assert(!KillingInstr && "Should only see one killing instruction");
    322         KilledOperand = I1UseReg;
    323         KillingInstr = &*I;
    324       }
    325     }
    326     if (KillingInstr) {
    327       removeKillInfo(KillingInstr, KilledOperand);
    328       // Update I1 to set the kill flag. This flag will later be picked up by
    329       // the new COMBINE instruction.
    330       bool Added = I1->addRegisterKilled(KilledOperand, TRI);
    331       (void)Added; // suppress compiler warning
    332       assert(Added && "Must successfully update kill flag");
    333     }
    334     DoInsertAtI1 = false;
    335   }
    336 
    337   return true;
    338 }
    339 
    340 /// findPotentialNewifiableTFRs - Finds tranfers that feed stores that could be
    341 /// newified. (A use of a 64 bit register define can not be newified)
    342 void
    343 HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
    344   DenseMap<unsigned, MachineInstr *> LastDef;
    345   for (MachineBasicBlock::iterator I = BB.begin(), E = BB.end(); I != E; ++I) {
    346     MachineInstr *MI = I;
    347     // Mark TFRs that feed a potential new value store as such.
    348     if(TII->mayBeNewStore(MI)) {
    349       // Look for uses of TFR instructions.
    350       for (unsigned OpdIdx = 0, OpdE = MI->getNumOperands(); OpdIdx != OpdE;
    351            ++OpdIdx) {
    352         MachineOperand &Op = MI->getOperand(OpdIdx);
    353 
    354         // Skip over anything except register uses.
    355         if (!Op.isReg() || !Op.isUse() || !Op.getReg())
    356           continue;
    357 
    358         // Look for the defining instruction.
    359         unsigned Reg = Op.getReg();
    360         MachineInstr *DefInst = LastDef[Reg];
    361         if (!DefInst)
    362           continue;
    363         if (!isCombinableInstType(DefInst, TII, ShouldCombineAggressively))
    364           continue;
    365 
    366         // Only close newifiable stores should influence the decision.
    367         MachineBasicBlock::iterator It(DefInst);
    368         unsigned NumInstsToDef = 0;
    369         while (&*It++ != MI)
    370           ++NumInstsToDef;
    371 
    372         if (NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR)
    373           continue;
    374 
    375         PotentiallyNewifiableTFR.insert(DefInst);
    376       }
    377       // Skip to next instruction.
    378       continue;
    379     }
    380 
    381     // Put instructions that last defined integer or double registers into the
    382     // map.
    383     for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
    384       MachineOperand &Op = MI->getOperand(I);
    385       if (!Op.isReg() || !Op.isDef() || !Op.getReg())
    386         continue;
    387       unsigned Reg = Op.getReg();
    388       if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
    389         for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
    390           LastDef[*SubRegs] = MI;
    391         }
    392       } else if (Hexagon::IntRegsRegClass.contains(Reg))
    393         LastDef[Reg] = MI;
    394     }
    395   }
    396 }
    397 
    398 bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
    399 
    400   if (IsCombinesDisabled) return false;
    401 
    402   bool HasChanged = false;
    403 
    404   // Get target info.
    405   TRI = MF.getSubtarget().getRegisterInfo();
    406   TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
    407 
    408   // Combine aggressively (for code size)
    409   ShouldCombineAggressively =
    410     MF.getTarget().getOptLevel() <= CodeGenOpt::Default;
    411 
    412   // Traverse basic blocks.
    413   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
    414        ++BI) {
    415     PotentiallyNewifiableTFR.clear();
    416     findPotentialNewifiableTFRs(*BI);
    417 
    418     // Traverse instructions in basic block.
    419     for(MachineBasicBlock::iterator MI = BI->begin(), End = BI->end();
    420         MI != End;) {
    421       MachineInstr *I1 = MI++;
    422       // Don't combine a TFR whose user could be newified (instructions that
    423       // define double registers can not be newified - Programmer's Ref Manual
    424       // 5.4.2 New-value stores).
    425       if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I1))
    426         continue;
    427 
    428       // Ignore instructions that are not combinable.
    429       if (!isCombinableInstType(I1, TII, ShouldCombineAggressively))
    430         continue;
    431 
    432       // Find a second instruction that can be merged into a combine
    433       // instruction.
    434       bool DoInsertAtI1 = false;
    435       MachineInstr *I2 = findPairable(I1, DoInsertAtI1);
    436       if (I2) {
    437         HasChanged = true;
    438         combine(I1, I2, MI, DoInsertAtI1);
    439       }
    440     }
    441   }
    442 
    443   return HasChanged;
    444 }
    445 
    446 /// findPairable - Returns an instruction that can be merged with \p I1 into a
    447 /// COMBINE instruction or 0 if no such instruction can be found. Returns true
    448 /// in \p DoInsertAtI1 if the combine must be inserted at instruction \p I1
    449 /// false if the combine must be inserted at the returned instruction.
    450 MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr *I1,
    451                                                  bool &DoInsertAtI1) {
    452   MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1));
    453   unsigned I1DestReg = I1->getOperand(0).getReg();
    454 
    455   for (MachineBasicBlock::iterator End = I1->getParent()->end(); I2 != End;
    456        ++I2) {
    457     // Bail out early if we see a second definition of I1DestReg.
    458     if (I2->modifiesRegister(I1DestReg, TRI))
    459       break;
    460 
    461     // Ignore non-combinable instructions.
    462     if (!isCombinableInstType(I2, TII, ShouldCombineAggressively))
    463       continue;
    464 
    465     // Don't combine a TFR whose user could be newified.
    466     if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I2))
    467       continue;
    468 
    469     unsigned I2DestReg = I2->getOperand(0).getReg();
    470 
    471     // Check that registers are adjacent and that the first destination register
    472     // is even.
    473     bool IsI1LowReg = (I2DestReg - I1DestReg) == 1;
    474     bool IsI2LowReg = (I1DestReg - I2DestReg) == 1;
    475     unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg;
    476     if ((!IsI1LowReg && !IsI2LowReg) || !isEvenReg(FirstRegIndex))
    477       continue;
    478 
    479     // Check that the two instructions are combinable. V4 allows more
    480     // instructions to be merged into a combine.
    481     // The order matters because in a TFRI we might can encode a int8 as the
    482     // hi reg operand but only a uint6 as the low reg operand.
    483     if ((IsI2LowReg && !areCombinableOperations(TRI, I1, I2)) ||
    484         (IsI1LowReg && !areCombinableOperations(TRI, I2, I1)))
    485       break;
    486 
    487     if (isSafeToMoveTogether(I1, I2, I1DestReg, I2DestReg,
    488                              DoInsertAtI1))
    489       return I2;
    490 
    491     // Not safe. Stop searching.
    492     break;
    493   }
    494   return nullptr;
    495 }
    496 
    497 void HexagonCopyToCombine::combine(MachineInstr *I1, MachineInstr *I2,
    498                                    MachineBasicBlock::iterator &MI,
    499                                    bool DoInsertAtI1) {
    500   // We are going to delete I2. If MI points to I2 advance it to the next
    501   // instruction.
    502   if ((MachineInstr *)MI == I2) ++MI;
    503 
    504   // Figure out whether I1 or I2 goes into the lowreg part.
    505   unsigned I1DestReg = I1->getOperand(0).getReg();
    506   unsigned I2DestReg = I2->getOperand(0).getReg();
    507   bool IsI1Loreg = (I2DestReg - I1DestReg) == 1;
    508   unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg;
    509 
    510   // Get the double word register.
    511   unsigned DoubleRegDest =
    512     TRI->getMatchingSuperReg(LoRegDef, Hexagon::subreg_loreg,
    513                              &Hexagon::DoubleRegsRegClass);
    514   assert(DoubleRegDest != 0 && "Expect a valid register");
    515 
    516 
    517   // Setup source operands.
    518   MachineOperand &LoOperand = IsI1Loreg ? I1->getOperand(1) :
    519     I2->getOperand(1);
    520   MachineOperand &HiOperand = IsI1Loreg ? I2->getOperand(1) :
    521     I1->getOperand(1);
    522 
    523   // Figure out which source is a register and which a constant.
    524   bool IsHiReg = HiOperand.isReg();
    525   bool IsLoReg = LoOperand.isReg();
    526 
    527   MachineBasicBlock::iterator InsertPt(DoInsertAtI1 ? I1 : I2);
    528   // Emit combine.
    529   if (IsHiReg && IsLoReg)
    530     emitCombineRR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
    531   else if (IsHiReg)
    532     emitCombineRI(InsertPt, DoubleRegDest, HiOperand, LoOperand);
    533   else if (IsLoReg)
    534     emitCombineIR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
    535   else
    536     emitCombineII(InsertPt, DoubleRegDest, HiOperand, LoOperand);
    537 
    538   I1->eraseFromParent();
    539   I2->eraseFromParent();
    540 }
    541 
    542 void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt,
    543                                          unsigned DoubleDestReg,
    544                                          MachineOperand &HiOperand,
    545                                          MachineOperand &LoOperand) {
    546   DebugLoc DL = InsertPt->getDebugLoc();
    547   MachineBasicBlock *BB = InsertPt->getParent();
    548 
    549   // Handle globals.
    550   if (HiOperand.isGlobal()) {
    551     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
    552       .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
    553                         HiOperand.getTargetFlags())
    554       .addImm(LoOperand.getImm());
    555     return;
    556   }
    557   if (LoOperand.isGlobal()) {
    558     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
    559       .addImm(HiOperand.getImm())
    560       .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
    561                         LoOperand.getTargetFlags());
    562     return;
    563   }
    564 
    565   // Handle block addresses.
    566   if (HiOperand.isBlockAddress()) {
    567     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
    568       .addBlockAddress(HiOperand.getBlockAddress(), HiOperand.getOffset(),
    569                        HiOperand.getTargetFlags())
    570       .addImm(LoOperand.getImm());
    571     return;
    572   }
    573   if (LoOperand.isBlockAddress()) {
    574     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
    575       .addImm(HiOperand.getImm())
    576       .addBlockAddress(LoOperand.getBlockAddress(), LoOperand.getOffset(),
    577                        LoOperand.getTargetFlags());
    578     return;
    579   }
    580 
    581   // Handle jump tables.
    582   if (HiOperand.isJTI()) {
    583     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
    584       .addJumpTableIndex(HiOperand.getIndex(), HiOperand.getTargetFlags())
    585       .addImm(LoOperand.getImm());
    586     return;
    587   }
    588   if (LoOperand.isJTI()) {
    589     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
    590       .addImm(HiOperand.getImm())
    591       .addJumpTableIndex(LoOperand.getIndex(), LoOperand.getTargetFlags());
    592     return;
    593   }
    594 
    595   // Handle constant pools.
    596   if (HiOperand.isCPI()) {
    597     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
    598       .addConstantPoolIndex(HiOperand.getIndex(), HiOperand.getOffset(),
    599                             HiOperand.getTargetFlags())
    600       .addImm(LoOperand.getImm());
    601     return;
    602   }
    603   if (LoOperand.isCPI()) {
    604     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
    605       .addImm(HiOperand.getImm())
    606       .addConstantPoolIndex(LoOperand.getIndex(), LoOperand.getOffset(),
    607                             LoOperand.getTargetFlags());
    608     return;
    609   }
    610 
    611   // First preference should be given to Hexagon::A2_combineii instruction
    612   // as it can include U6 (in Hexagon::A4_combineii) as well.
    613   // In this instruction, HiOperand is const extended, if required.
    614   if (isInt<8>(LoOperand.getImm())) {
    615     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
    616       .addImm(HiOperand.getImm())
    617       .addImm(LoOperand.getImm());
    618       return;
    619   }
    620 
    621   // In this instruction, LoOperand is const extended, if required.
    622   if (isInt<8>(HiOperand.getImm())) {
    623     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
    624       .addImm(HiOperand.getImm())
    625       .addImm(LoOperand.getImm());
    626     return;
    627   }
    628 
    629   // Insert new combine instruction.
    630   //  DoubleRegDest = combine #HiImm, #LoImm
    631   BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
    632     .addImm(HiOperand.getImm())
    633     .addImm(LoOperand.getImm());
    634 }
    635 
    636 void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
    637                                          unsigned DoubleDestReg,
    638                                          MachineOperand &HiOperand,
    639                                          MachineOperand &LoOperand) {
    640   unsigned LoReg = LoOperand.getReg();
    641   unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
    642 
    643   DebugLoc DL = InsertPt->getDebugLoc();
    644   MachineBasicBlock *BB = InsertPt->getParent();
    645 
    646   // Handle globals.
    647   if (HiOperand.isGlobal()) {
    648     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
    649       .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
    650                         HiOperand.getTargetFlags())
    651       .addReg(LoReg, LoRegKillFlag);
    652     return;
    653   }
    654   // Handle block addresses.
    655   if (HiOperand.isBlockAddress()) {
    656     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
    657       .addBlockAddress(HiOperand.getBlockAddress(), HiOperand.getOffset(),
    658                        HiOperand.getTargetFlags())
    659       .addReg(LoReg, LoRegKillFlag);
    660     return;
    661   }
    662   // Handle jump tables.
    663   if (HiOperand.isJTI()) {
    664     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
    665       .addJumpTableIndex(HiOperand.getIndex(), HiOperand.getTargetFlags())
    666       .addReg(LoReg, LoRegKillFlag);
    667     return;
    668   }
    669   // Handle constant pools.
    670   if (HiOperand.isCPI()) {
    671     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
    672       .addConstantPoolIndex(HiOperand.getIndex(), HiOperand.getOffset(),
    673                             HiOperand.getTargetFlags())
    674       .addReg(LoReg, LoRegKillFlag);
    675     return;
    676   }
    677   // Insert new combine instruction.
    678   //  DoubleRegDest = combine #HiImm, LoReg
    679   BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
    680     .addImm(HiOperand.getImm())
    681     .addReg(LoReg, LoRegKillFlag);
    682 }
    683 
    684 void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt,
    685                                          unsigned DoubleDestReg,
    686                                          MachineOperand &HiOperand,
    687                                          MachineOperand &LoOperand) {
    688   unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
    689   unsigned HiReg = HiOperand.getReg();
    690 
    691   DebugLoc DL = InsertPt->getDebugLoc();
    692   MachineBasicBlock *BB = InsertPt->getParent();
    693 
    694   // Handle global.
    695   if (LoOperand.isGlobal()) {
    696     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
    697       .addReg(HiReg, HiRegKillFlag)
    698       .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
    699                         LoOperand.getTargetFlags());
    700     return;
    701   }
    702   // Handle block addresses.
    703   if (LoOperand.isBlockAddress()) {
    704     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
    705       .addReg(HiReg, HiRegKillFlag)
    706       .addBlockAddress(LoOperand.getBlockAddress(), LoOperand.getOffset(),
    707                        LoOperand.getTargetFlags());
    708     return;
    709   }
    710   // Handle jump tables.
    711   if (LoOperand.isJTI()) {
    712     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
    713       .addReg(HiOperand.getReg(), HiRegKillFlag)
    714       .addJumpTableIndex(LoOperand.getIndex(), LoOperand.getTargetFlags());
    715     return;
    716   }
    717   // Handle constant pools.
    718   if (LoOperand.isCPI()) {
    719     BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
    720       .addReg(HiOperand.getReg(), HiRegKillFlag)
    721       .addConstantPoolIndex(LoOperand.getIndex(), LoOperand.getOffset(),
    722                             LoOperand.getTargetFlags());
    723     return;
    724   }
    725 
    726   // Insert new combine instruction.
    727   //  DoubleRegDest = combine HiReg, #LoImm
    728   BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
    729     .addReg(HiReg, HiRegKillFlag)
    730     .addImm(LoOperand.getImm());
    731 }
    732 
    733 void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt,
    734                                          unsigned DoubleDestReg,
    735                                          MachineOperand &HiOperand,
    736                                          MachineOperand &LoOperand) {
    737   unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
    738   unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
    739   unsigned LoReg = LoOperand.getReg();
    740   unsigned HiReg = HiOperand.getReg();
    741 
    742   DebugLoc DL = InsertPt->getDebugLoc();
    743   MachineBasicBlock *BB = InsertPt->getParent();
    744 
    745   // Insert new combine instruction.
    746   //  DoubleRegDest = combine HiReg, LoReg
    747   BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combinew), DoubleDestReg)
    748     .addReg(HiReg, HiRegKillFlag)
    749     .addReg(LoReg, LoRegKillFlag);
    750 }
    751 
    752 FunctionPass *llvm::createHexagonCopyToCombine() {
    753   return new HexagonCopyToCombine();
    754 }
    755