/external/llvm/lib/Analysis/ |
InstructionSimplify.cpp | 148 if (BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS)) 149 if (Op0->getOpcode() == OpcodeToExpand) { 151 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1), *C = RHS; 207 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS); 211 if (Op0 && Op0->getOpcode() == Opcode) { 212 Value *A = Op0->getOperand(0); 213 Value *B = Op0->getOperand(1); 253 if (Op0 && Op0->getOpcode() == Opcode) [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
InstCombineMulDivRem.cpp | 177 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); 182 if (Value *V = SimplifyMulInst(Op0, Op1, DL, TLI, DT, AC)) 190 BinaryOperator *BO = BinaryOperator::CreateNeg(Op0, I.getName()); 252 if (Op0->hasOneUse()) { 255 if (match(Op0, m_Sub(m_Value(Y), m_Value(X)))) 257 else if (match(Op0, m_Add(m_Value(Y), m_ConstantInt(C1)))) 271 if (SelectInst *SI = dyn_cast<SelectInst>(Op0)) 275 if (isa<PHINode>(Op0)) 283 if (match(Op0, m_OneUse(m_Add(m_Value(X), m_Constant(C1))))) { 293 if (Value *Op0v = dyn_castNegVal(Op0)) { // -X * -Y = X* [all...] |
InstCombineAndOrXor.cpp | [all...] |
InstCombineShifts.cpp | 26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); 33 if (isa<Constant>(Op0)) 39 if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I)) 321 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, 339 CanEvaluateShifted(Op0, COp1->getZExtValue(), isLeftShift, *this, &I)) { 341 " to eliminate shift:\n IN: " << *Op0 << "\n SH: " << I <<"\n"); 344 I, GetShiftedValue(Op0, COp1->getZExtValue(), isLeftShift, *this, DL)); 349 uint32_t TypeBits = Op0->getType()->getScalarSizeInBits(); 355 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Op0)) 362 if (SelectInst *SI = dyn_cast<SelectInst>(Op0)) [all...] |
InstCombineCompares.cpp | [all...] |
InstCombineAddSub.cpp | [all...] |
InstCombineCalls.cpp | 386 static Value *SimplifyX86extrq(IntrinsicInst &II, Value *Op0, 397 Constant *C0 = dyn_cast<Constant>(Op0); 448 Builder.CreateBitCast(Op0, ShufTy), 463 Value *Args[] = {Op0, CILength, CIIndex}; 479 static Value *SimplifyX86insertq(IntrinsicInst &II, Value *Op0, Value *Op1, 528 Value *SV = Builder.CreateShuffleVector(Builder.CreateBitCast(Op0, ShufTy), 535 Constant *C0 = dyn_cast<Constant>(Op0); 565 Value *Args[] = {Op0, Op1, CILength, CIIndex}; [all...] |
InstructionCombining.cpp | 201 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(I.getOperand(0)); 206 if (Op0 && Op0->getOpcode() == Opcode) { 207 Value *A = Op0->getOperand(0); 208 Value *B = Op0->getOperand(1); 219 (!Op0 || (isa<BinaryOperator>(Op0) && Op0->hasNoSignedWrap()))) { 221 // the operands to Op0. 257 if (Op0 && Op0->getOpcode() == Opcode) [all...] |
/external/llvm/include/llvm/CodeGen/ |
FastISel.h | 341 virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 346 virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 352 virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 358 virtual unsigned fastEmit_rf(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 365 unsigned Op0, bool Op0IsKill, unsigned Op1, 373 unsigned fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, 394 const TargetRegisterClass *RC, unsigned Op0, 400 const TargetRegisterClass *RC, unsigned Op0, 406 const TargetRegisterClass *RC, unsigned Op0, 413 const TargetRegisterClass *RC, unsigned Op0, [all...] |
/external/llvm/lib/Transforms/Scalar/ |
Scalarizer.cpp | 74 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, 76 return Builder.CreateFCmp(FCI.getPredicate(), Op0, Op1, Name); 85 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, 87 return Builder.CreateICmp(ICI.getPredicate(), Op0, Op1, Name); 96 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, 98 return Builder.CreateBinOp(BO.getOpcode(), Op0, Op1, Name); 381 Scatterer Op0 = scatter(&I, I.getOperand(0)); 383 assert(Op0.size() == NumElems && "Mismatched binary operation"); 388 Res[Elem] = Split(Builder, Op0[Elem], Op1[Elem], 409 Scatterer Op0 = scatter(&SI, SI.getOperand(0)) [all...] |
CorrelatedValuePropagation.cpp | 194 Value *Op0 = C->getOperand(0); 203 auto *I = dyn_cast<Instruction>(Op0); 208 LVI->getPredicateAt(C->getPredicate(), Op0, Op1, C); 346 Value *Op0 = C->getOperand(0); 351 LVI->getPredicateAt(C->getPredicate(), Op0, Op1, At);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
FastISel.cpp | 422 unsigned Op0 = getRegForValue(I->getOperand(0)); 423 if (!Op0) // Unhandled operand. Halt "fast" selection and bail. 445 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, 458 ISDOpcode, Op0, Op0IsKill, CF); 473 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill); [all...] |
/external/llvm/include/llvm/IR/ |
GetElementPtrTypeIterator.h | 128 gep_type_begin(Type *Op0, ArrayRef<T> A) { 129 return generic_gep_type_iterator<const T *>::begin(Op0, A.begin()); 134 gep_type_end(Type * /*Op0*/, ArrayRef<T> A) {
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/external/llvm/lib/Target/Hexagon/ |
HexagonExpandPredSpillCode.cpp | 101 MachineOperand &Op0 = MI->getOperand(0); 112 NewMI->addOperand(Op0); 144 MachineOperand &Op0 = MI->getOperand(0); 156 NewMI->addOperand(Op0); 186 MachineOperand &Op0 = MI->getOperand(0); 197 NewMI->addOperand(Op0); 223 MachineOperand &Op0 = MI->getOperand(0); 233 NewMI->addOperand(Op0);
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HexagonSplitDouble.cpp | 671 MachineOperand &Op0 = MI->getOperand(0); 673 assert(Op0.isReg() && Op1.isImm()); 678 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); 699 MachineOperand &Op0 = MI->getOperand(0); 702 assert(Op0.isReg()); 706 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); 732 MachineOperand &Op0 = MI->getOperand(0); 734 assert(Op0.isReg() && Op1.isReg()); 738 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); 753 MachineOperand &Op0 = MI->getOperand(0) [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZISelDAGToDAG.cpp | 295 // If Op0 is null, then Node is a constant that can be loaded using: 299 // If Op0 is nonnull, then Node can be implemented using: 301 // (Opcode (Opcode Op0 UpperVal) LowerVal) 302 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0, 414 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects 417 SDValue Op0, uint64_t Op1) { 421 changeComponent(AM, IsBase, Op0); 440 SDValue Op0 = N.getOperand(0); 443 unsigned Op0Code = Op0->getOpcode(); 449 return expandAdjDynAlloc(AM, IsBase, Op0); [all...] |
SystemZISelLowering.cpp | 45 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {} 48 SDValue Op0, Op1; 50 // The opcode that should be used to compare Op0 and Op1. [all...] |
/external/llvm/lib/Target/X86/ |
X86FloatingPoint.cpp | [all...] |
/external/opencv3/modules/cudev/include/opencv2/cudev/warp/detail/ |
reduce.hpp | 157 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9> 162 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) 178 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9> 182 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
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/external/llvm/lib/ExecutionEngine/ |
ExecutionEngine.cpp | 647 Constant *Op0 = CE->getOperand(0); 651 GenericValue Result = getConstantValue(Op0); 660 GenericValue GV = getConstantValue(Op0); 666 GenericValue GV = getConstantValue(Op0); 672 GenericValue GV = getConstantValue(Op0); 679 GenericValue GV = getConstantValue(Op0); 685 GenericValue GV = getConstantValue(Op0); 690 GenericValue GV = getConstantValue(Op0); 705 GenericValue GV = getConstantValue(Op0); 721 GenericValue GV = getConstantValue(Op0); [all...] |
/external/llvm/lib/IR/ |
AutoUpgrade.cpp | 568 Value *Op0 = CI->getArgOperand(0); 580 Rep = Builder.CreateShuffleVector(Op0, Op1, ConstantVector::get(Idxs)); 585 Value *Op0 = CI->getArgOperand(0); 626 Rep = Builder.CreateShuffleVector(Op0, Rep, ConstantVector::get(Idxs2)); 631 Value *Op0 = CI->getArgOperand(0); 646 Value *UndefV = UndefValue::get(Op0->getType()); 647 Rep = Builder.CreateShuffleVector(Op0, UndefV, ConstantVector::get(Idxs)); 660 Value *Op0 = CI->getArgOperand(0); 681 Rep = Builder.CreateShuffleVector(Op0, Op0, ConstantVector::get(Idxs)) [all...] |
/external/opencv3/modules/cudev/include/opencv2/cudev/block/ |
reduce.hpp | 71 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9> 75 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) 80 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op);
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/external/llvm/lib/Target/Sparc/ |
SparcISelDAGToDAG.cpp | 390 SDValue Op0, Op1; 395 if (!SelectADDRrr(Op, Op0, Op1)) 396 SelectADDRri(Op, Op0, Op1); 400 OutOps.push_back(Op0);
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/external/llvm/lib/Target/AArch64/ |
AArch64FastISel.cpp | 194 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm); 212 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, 214 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, 216 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, [all...] |
/external/llvm/lib/Target/ARM/ |
ARMLoadStoreOptimizer.cpp | [all...] |