| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 360 .addReg(PPC::R31)
365 .addReg(PPC::X1);
369 .addReg(PPC::R1);
390 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
391 .addReg(NegSizeReg1, RegState::Kill);
396 .addReg(Reg, RegState::Kill)
397 .addReg(PPC::X1)
398 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
400 .addReg(PPC::X1)
415 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)
[all...] |
| PPCFastISel.cpp | 546 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
570 .addReg(Addr.Base.Reg).addReg(IndexReg);
671 .addReg(SrcReg)
682 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
703 .addReg(SrcReg);
710 MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
712 MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg)
[all...] |
| PPCTLSDynamicCall.cpp | 104 .addReg(InReg);
113 .addReg(GPR3));
117 .addReg(GPR3);
|
| /external/llvm/include/llvm/MC/ |
| MCInstBuilder.h | 32 MCInstBuilder &addReg(unsigned Reg) {
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 54 .addReg(SrcReg, getKillRegState(KillSrc)));
64 .addReg(SrcReg, getKillRegState(KillSrc));
66 .addReg(DestReg, getDefRegState(true));
91 .addReg(SrcReg, getKillRegState(isKill))
|
| ThumbRegisterInfo.cpp | 77 .addReg(DestReg, getDefRegState(true), SubIdx)
78 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
96 .addReg(DestReg, getDefRegState(true), SubIdx)
97 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
157 .addReg(LdReg, RegState::Kill).setMIFlags(MIFlags);
170 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
172 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
309 MIB.addReg(BaseReg, RegState::Kill)
[all...] |
| ARMExpandPseudoInsts.cpp | 394 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
396 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
398 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
400 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
431 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
469 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
471 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
473 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
475 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
484 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg
[all...] |
| ARMFastISel.cpp | 295 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
298 .addReg(Op0, Op0IsKill * RegState::Kill));
301 .addReg(II.ImplicitDefs[0]));
321 .addReg(Op0, Op0IsKill * RegState::Kill)
322 .addReg(Op1, Op1IsKill * RegState::Kill));
325 .addReg(Op0, Op0IsKill * RegState::Kill)
326 .addReg(Op1, Op1IsKill * RegState::Kill));
329 .addReg(II.ImplicitDefs[0]));
351 .addReg(Op0, Op0IsKill * RegState::Kill)
352 .addReg(Op1, Op1IsKill * RegState::Kill
[all...] |
| MLxExpansionPass.cpp | 294 .addReg(Src1Reg, getKillRegState(Src1Kill))
295 .addReg(Src2Reg, getKillRegState(Src2Kill));
298 MIB.addImm(Pred).addReg(PredReg);
301 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
305 MIB.addReg(TmpReg, getKillRegState(true))
306 .addReg(AccReg, getKillRegState(AccKill));
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
310 MIB.addImm(Pred).addReg(PredReg);
|
| Thumb2InstrInfo.cpp | 121 .addReg(SrcReg, getKillRegState(KillSrc)));
142 .addReg(SrcReg, getKillRegState(isKill))
200 MIB.addReg(DestReg, RegState::ImplicitDefine);
223 .addReg(BaseReg, RegState::Kill)
224 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
241 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
246 .addReg(DestReg)
248 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
255 .addReg(BaseReg)
256 .addReg(DestReg, RegState::Kill
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 297 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
298 .addReg(SrcReg, getKillRegState(KillSrc));
306 .addReg(SrcReg, getKillRegState(KillSrc));
310 .addReg(SrcReg, getKillRegState(KillSrc));
321 .addReg(SrcReg, getKillRegState(KillSrc));
337 .addReg(SP::G0)
338 .addReg(SrcReg, getKillRegState(KillSrc));
342 .addReg(SrcReg, getKillRegState(KillSrc));
359 MIB.addReg(SP::G0);
360 MIB.addReg(Src)
[all...] |
| SparcFrameLowering.cpp | 53 .addReg(SP::O6).addImm(NumBytes);
67 .addReg(SP::G1).addImm(LO10(NumBytes));
69 .addReg(SP::O6).addReg(SP::G1);
80 .addReg(SP::G1).addImm(LOX10(NumBytes));
82 .addReg(SP::O6).addReg(SP::G1);
182 BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), SP::O6).addReg(SP::O6).addImm(MaxAlign - 1);
212 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
213 .addReg(SP::G0)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 41 return MIB.addFrameIndex(FI).addImm(Offset).addReg(0).addMemOperand(MMO);
|
| SystemZRegisterInfo.cpp | 118 .addReg(BasePtr).addImm(HighOffset).addReg(0);
124 .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
|
| SystemZLDCleanup.cpp | 119 .addReg(TLSBaseAddrReg);
139 .addReg(SystemZ::R2D);
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 162 .addReg(VR, RegState::Kill);
176 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
199 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
201 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
221 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
223 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
254 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
256 .addReg(VR0, RegState::Kill);
257 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
259 .addReg(VR1, RegState::Kill)
[all...] |
| Mips16InstrInfo.cpp | 87 MIB.addReg(DestReg, RegState::Define);
90 MIB.addReg(SrcReg, getKillRegState(KillSrc));
106 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
185 MIB.addReg(Reg, Flags);
210 MIB.addReg(Mips::S2);
253 MIB.addReg(Mips::S2, RegState::Define);
277 MIB2.addReg(Mips::SP, RegState::Kill);
279 MIB3.addReg(Reg1);
280 MIB3.addReg(Reg2, RegState::Kill);
283 MIB4.addReg(Reg1, RegState::Kill)
[all...] |
| MipsISelLowering.cpp | [all...] |
| MipsSERegisterInfo.cpp | 190 .addReg(FrameReg)
207 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg)
208 .addReg(Reg, RegState::Kill);
|
| Mips16ISelLowering.cpp | 557 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
575 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
576 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
618 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
619 .addReg(MI->getOperand(4).getReg());
637 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
638 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
682 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
701 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
702 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | 369 .addReg(SrcReg, getKillRegState(KillSrc));
376 .addReg(SrcReg, getKillRegState(KillSrc));
382 .addReg(SrcReg, getKillRegState(KillSrc));
390 .addReg(SrcReg, getKillRegState(KillSrc));
412 .addReg(SrcReg, getKillRegState(KillSrc));
463 Builder.addReg(RI.getSubReg(SrcReg, SubIdx));
466 Builder.addReg(SrcReg, RegState::Kill | RegState::Implicit);
469 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
566 .addReg(SrcReg) // src
578 .addReg(SrcReg)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 112 .addReg(AArch64::XZR)
121 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
122 .addReg(DstReg)
179 .addReg(AArch64::XZR)
198 .addReg(DstReg,
200 .addReg(DstReg)
223 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
224 .addReg(DstReg)
362 .addReg(AArch64::XZR)
372 .addReg(DstReg
[all...] |
| AArch64CleanupLocalDynamicTLSPass.cpp | 101 AArch64::X0).addReg(TLSBaseAddrReg);
123 .addReg(AArch64::X0);
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyLowerBrUnless.cpp | 116 .addReg(Cond)
117 .addReg(ZeroReg);
126 .addReg(Cond)
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 168 .addReg(M0);
172 .addReg(tmp)
176 .addReg(M0);
198 .addReg(M0);
209 .addReg(AMDGPU::SREG_LIT_0)
215 .addReg(AMDGPU::EXEC);
224 .addReg(AMDGPU::SREG_LIT_0)
225 .addReg(AMDGPU::SREG_LIT_0)
226 .addReg(AMDGPU::SREG_LIT_0)
227 .addReg(AMDGPU::SREG_LIT_0)
[all...] |
