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  /external/dexmaker/src/dx/java/com/android/dx/io/instructions/
ZeroRegisterDecodedInstruction.java 41 getFormat(), getOpcode(), newIndex, getIndexType(),
  /dalvik/dexgen/src/com/android/dexgen/rop/code/
ThrowingCstInsn.java 79 return new ThrowingCstInsn(getOpcode(), getPosition(),
87 return new ThrowingCstInsn(getOpcode(), getPosition(),
98 return new ThrowingCstInsn(getOpcode(), getPosition(),
ThrowingInsn.java 99 return new ThrowingInsn(getOpcode(), getPosition(),
106 return new ThrowingInsn(getOpcode(), getPosition(),
116 return new ThrowingInsn(getOpcode(), getPosition(),
  /dalvik/dx/src/com/android/dx/rop/code/
ThrowingCstInsn.java 84 return new ThrowingCstInsn(getOpcode(), getPosition(),
92 return new ThrowingCstInsn(getOpcode(), getPosition(),
103 return new ThrowingCstInsn(getOpcode(), getPosition(),
ThrowingInsn.java 99 return new ThrowingInsn(getOpcode(), getPosition(),
106 return new ThrowingInsn(getOpcode(), getPosition(),
116 return new ThrowingInsn(getOpcode(), getPosition(),
  /external/dexmaker/src/dx/java/com/android/dx/rop/code/
ThrowingCstInsn.java 84 return new ThrowingCstInsn(getOpcode(), getPosition(),
92 return new ThrowingCstInsn(getOpcode(), getPosition(),
103 return new ThrowingCstInsn(getOpcode(), getPosition(),
ThrowingInsn.java 99 return new ThrowingInsn(getOpcode(), getPosition(),
106 return new ThrowingInsn(getOpcode(), getPosition(),
116 return new ThrowingInsn(getOpcode(), getPosition(),
  /external/llvm/lib/MC/
MCInst.cpp 45 OS << "<MCInst " << getOpcode();
55 OS << "<MCInst #" << getOpcode();
59 OS << ' ' << Printer->getOpcodeName(getOpcode());
  /external/llvm/lib/Target/NVPTX/
NVPTXPeephole.cpp 78 if (Root.getOpcode() != NVPTX::cvta_to_local_yes_64 &&
79 Root.getOpcode() != NVPTX::cvta_to_local_yes)
91 (GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi64 &&
92 GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi)) {
113 BuildMI(MF, Root.getDebugLoc(), TII->get(Prev.getOpcode()),
NVPTXInstrInfo.cpp 114 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS)
161 if (LastInst->getOpcode() == NVPTX::GOTO) {
164 } else if (LastInst->getOpcode() == NVPTX::CBranch) {
182 if (SecondLastInst->getOpcode() == NVPTX::CBranch &&
183 LastInst->getOpcode() == NVPTX::GOTO) {
192 if (SecondLastInst->getOpcode() == NVPTX::GOTO &&
193 LastInst->getOpcode() == NVPTX::GOTO) {
210 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
221 if (I->getOpcode() != NVPTX::CBranch
    [all...]
  /external/llvm/lib/Target/Sparc/
DelaySlotFiller.cpp 119 (MI->getOpcode() == SP::RESTORErr
120 || MI->getOpcode() == SP::RESTOREri)) {
128 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD
129 || MI->getOpcode() == SP::FCMPQ)) {
180 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL)
183 if (slot->getOpcode() == SP::RETL) {
187 if (J->getOpcode() == SP::RESTORErr
188 || J->getOpcode() == SP::RESTOREri)
    [all...]
SparcISelDAGToDAG.cpp 85 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
86 Addr.getOpcode() == ISD::TargetGlobalAddress ||
87 Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
90 if (Addr.getOpcode() == ISD::ADD) {
106 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
111 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
123 if (Addr.getOpcode() == ISD::FrameIndex) return false;
124 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
125 Addr.getOpcode() == ISD::TargetGlobalAddress ||
126 Addr.getOpcode() == ISD::TargetGlobalTLSAddress
    [all...]
  /external/llvm/lib/Target/AMDGPU/MCTargetDesc/
R600MCCodeEmitter.cpp 91 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
92 if (MI.getOpcode() == AMDGPU::RETURN ||
93 MI.getOpcode() == AMDGPU::FETCH_CLAUSE ||
94 MI.getOpcode() == AMDGPU::ALU_CLAUSE ||
95 MI.getOpcode() == AMDGPU::BUNDLE ||
96 MI.getOpcode() == AMDGPU::KILL) {
170 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
  /external/llvm/lib/Target/AArch64/
AArch64BranchRelaxation.cpp 302 switch (MI->getOpcode()) {
355 assert(MI->getOpcode() == AArch64::Bcc && "Unexpected opcode!");
385 BMI->getOpcode() == AArch64::B) {
395 getBranchDisplacementBits(MI->getOpcode()))) {
399 unsigned OpNum = (MI->getOpcode() == AArch64::TBZW ||
400 MI->getOpcode() == AArch64::TBNZW ||
401 MI->getOpcode() == AArch64::TBZX ||
402 MI->getOpcode() == AArch64::TBNZX)
406 MI->setDesc(TII->get(getOppositeConditionOpcode(MI->getOpcode())));
407 if (MI->getOpcode() == AArch64::Bcc
    [all...]
  /external/llvm/lib/Target/AArch64/Disassembler/
AArch64ExternalSymbolizer.cpp 91 } else if (MI.getOpcode() == AArch64::ADRP) {
104 } else if (MI.getOpcode() == AArch64::ADDXri ||
105 MI.getOpcode() == AArch64::LDRXui ||
106 MI.getOpcode() == AArch64::LDRXl ||
107 MI.getOpcode() == AArch64::ADR) {
108 if (MI.getOpcode() == AArch64::ADDXri)
110 else if (MI.getOpcode() == AArch64::LDRXui)
112 if (MI.getOpcode() == AArch64::LDRXl) {
116 } else if (MI.getOpcode() == AArch64::ADR) {
125 MI.getOpcode() == AArch64::ADDXri ? 0x91000000: 0xF9400000
    [all...]
  /external/llvm/lib/Transforms/InstCombine/
InstCombineShifts.cpp 108 switch (I->getOpcode()) {
206 switch (I->getOpcode()) {
323 bool isLeftShift = I.getOpcode() == Instruction::Shl;
338 if (I.getOpcode() != Instruction::AShr &&
356 if (BO->getOpcode() == Instruction::Mul && isLeftShift)
382 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName());
396 if (I.getOpcode() == Instruction::Shl)
399 assert(I.getOpcode() == Instruction::LShr && "Unknown logical shift");
418 switch (Op0BO->getOpcode()) {
432 Value *X = Builder->CreateBinOp(Op0BO->getOpcode(), YS, V1
    [all...]
  /external/smali/dexlib2/src/main/java/org/jf/dexlib2/builder/
MutableMethodImplementation.java 86 final Opcode opcode = instruction.getOpcode();
350 if (instruction.getOpcode() != Opcode.NOP) {
363 switch (instruction.getOpcode()) {
374 if (targetInstruction.getOpcode() == Opcode.NOP) {
383 targetInstruction.getOpcode() != Opcode.PACKED_SWITCH_PAYLOAD) ||
385 targetInstruction.getOpcode() != Opcode.SPARSE_SWITCH_PAYLOAD)) {
411 switch (instruction.getOpcode()) {
454 if (previousInstruction.getOpcode() == Opcode.NOP) {
555 switch (instruction.getOpcode().format) {
660 throw new ExceptionWithContext("Instruction format %s not supported", instruction.getOpcode().format)
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonCFGOptimizer.cpp 75 switch(MI->getOpcode()) {
111 int Opc = MI->getOpcode();
163 if ((MI->getOpcode() == Hexagon::J2_jumpt) ||
164 (MI->getOpcode() == Hexagon::J2_jumpf)) {
176 IsUnconditionalJump(LayoutSucc->front().getOpcode())) {
183 IsUnconditionalJump(JumpAroundTarget->back().getOpcode()) &&
  /external/smali/smalidea/src/test/java/org/jf/smalidea/dexlib/
SmalideaMethodTest.java 119 Assert.assertEquals(Opcode.GOTO, instruction.getOpcode());
125 Assert.assertEquals(Opcode.RETURN_VOID, instruction.getOpcode());
130 Assert.assertEquals(Opcode.CONST_4, instruction.getOpcode());
137 Assert.assertEquals(Opcode.MONITOR_ENTER, instruction.getOpcode());
143 Assert.assertEquals(Opcode.MOVE, instruction.getOpcode());
150 Assert.assertEquals(Opcode.GOTO_16, instruction.getOpcode());
156 Assert.assertEquals(Opcode.SGET, instruction.getOpcode());
164 Assert.assertEquals(Opcode.CONST_HIGH16, instruction.getOpcode());
173 Assert.assertEquals(Opcode.CONST_WIDE_HIGH16, instruction.getOpcode());
181 Assert.assertEquals(Opcode.CONST_WIDE_16, instruction.getOpcode());
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 136 if (N->getOpcode() == ISD::HANDLENODE)
573 if (Op.getOpcode() == ISD::FNEG) return 2;
581 switch (Op.getOpcode()) {
635 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
644 switch (Op.getOpcode()) {
687 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
693 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
700 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
718 if (N.getOpcode() == ISD::SETCC) {
725 if (N.getOpcode() != ISD::SELECT_CC |
    [all...]
  /external/llvm/lib/Target/ARM/
ARMHazardRecognizer.cpp 26 unsigned Opcode = MCID.getOpcode();
63 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
64 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
  /dalvik/dexgen/src/com/android/dexgen/dex/code/
SimpleInsn.java 51 return new SimpleInsn(getOpcode(), getPosition(), registers);
  /dalvik/dx/src/com/android/dx/dex/code/
SimpleInsn.java 51 return new SimpleInsn(getOpcode(), getPosition(), registers);
  /dalvik/dx/src/com/android/dx/io/instructions/
OneRegisterDecodedInstruction.java 52 getFormat(), getOpcode(), newIndex, getIndexType(),
RegisterRangeDecodedInstruction.java 57 getFormat(), getOpcode(), newIndex, getIndexType(),

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