| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | [all...] |
| LegalizeVectorOps.cpp | 201 if (Op.getOpcode() == ISD::LOAD) {
229 } else if (Op.getOpcode() == ISD::STORE) {
247 } else if (Op.getOpcode() == ISD::MSCATTER || Op.getOpcode() == ISD::MSTORE)
258 switch (Op.getOpcode()) {
351 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
386 switch (Op.getOpcode()) {
394 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
405 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
423 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags())
[all...] |
| SelectionDAG.cpp | 101 while (N->getOpcode() == ISD::BITCAST)
104 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
109 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
139 N->getOperand(i).getOpcode() != ISD::UNDEF)
149 while (N->getOpcode() == ISD::BITCAST)
152 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
156 if (Op.getOpcode() == ISD::UNDEF)
187 if (N->getOpcode() != ISD::BUILD_VECTOR)
191 if (Op.getOpcode() == ISD::UNDEF)
202 if (N->getOpcode() != ISD::BUILD_VECTOR
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 629 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
636 } else if (MulOp0.getOpcode() == ISD::LOAD) {
655 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
662 } else if (MulOp1.getOpcode() == ISD::LOAD) {
696 if (Shl_1.getOpcode() == ISD::Constant) {
697 if (Shl_0.getOpcode() == ISD::MUL) {
701 if (Mul_1.getOpcode() == ISD::Constant) {
719 } else if (Shl_0.getOpcode() == ISD::SUB) {
722 if (Sub_0.getOpcode() == ISD::Constant) {
726 if (Sub_1.getOpcode() == ISD::SHL)
[all...] |
| HexagonHardwareLoops.cpp | 418 unsigned UpdOpc = DI->getOpcode();
617 unsigned CondOpc = CondI->getOpcode();
698 if (StartValInstr && (StartValInstr->getOpcode() == Hexagon::A2_tfrsi ||
699 StartValInstr->getOpcode() == Hexagon::A2_tfrpi))
704 if (EndValInstr && (EndValInstr->getOpcode() == Hexagon::A2_tfrsi ||
705 EndValInstr->getOpcode() == Hexagon::A2_tfrpi))
889 if (EndValInstr->getOpcode() == Hexagon::A2_addi &&
[all...] |
| HexagonAsmPrinter.cpp | 264 switch (Inst.getOpcode()) {
409 if (Inst.getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax)
502 MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
515 MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
578 if (MII->getOpcode() == TargetOpcode::DBG_VALUE ||
579 MII->getOpcode() == TargetOpcode::IMPLICIT_DEF)
|
| HexagonGenPredicate.cpp | 166 unsigned Opc = MI->getOpcode();
190 unsigned Opc = MI->getOpcode();
238 unsigned Opc = DefI->getOpcode();
314 unsigned DefOpc = DefI->getOpcode();
353 unsigned Opc = MI->getOpcode();
455 if (I->getOpcode() != TargetOpcode::COPY)
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/analysis/ |
| MethodAnalyzer.java | 199 if (instructionToAnalyze.originalInstruction.getOpcode().odexOnly()) {
217 ex.addContext(String.format("opcode: %s", instructionToAnalyze.instruction.getOpcode().name));
254 if (instruction.getOpcode().odexOnly()) {
256 switch (instruction.getOpcode().format) {
443 Opcode instructionOpcode = instruction.instruction.getOpcode();
486 Opcode instructionOpcode = instruction.instruction.getOpcode();
489 if (instruction.instruction.getOpcode().canContinue()) {
541 if (!allowMoveException && successor.instruction.getOpcode() == Opcode.MOVE_EXCEPTION) {
542 throw new AnalysisException("Execution can pass from the " + predecessor.instruction.getOpcode().name +
565 assert successor.instruction.getOpcode().canThrow()
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombinePHI.cpp | 28 unsigned Opc = FirstInst->getOpcode();
47 if (!I || I->getOpcode() != Opc || !I->hasOneUse() ||
115 CmpInst *NewCI = CmpInst::Create(CIOp->getOpcode(), CIOp->getPredicate(),
123 BinaryOperator::Create(BinOp->getOpcode(), LHSVal, RHSVal);
576 CastInst *NewCI = CastInst::Create(FirstCI->getOpcode(), PhiVal,
583 BinOp = BinaryOperator::Create(BinOp->getOpcode(), PhiVal, ConstantOp);
592 CmpInst *NewCI = CmpInst::Create(CIOp->getOpcode(), CIOp->getPredicate(),
759 if (UserI->getOpcode() != Instruction::LShr ||
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| EarlyCSE.cpp | 106 return hash_combine(BinOp->getOpcode(), Overflow, LHS, RHS);
109 return hash_combine(BinOp->getOpcode(), LHS, RHS);
120 return hash_combine(Inst->getOpcode(), Pred, LHS, RHS);
124 return hash_combine(CI->getOpcode(), CI->getType(), CI->getOperand(0));
127 return hash_combine(EVI->getOpcode(), EVI->getOperand(0),
131 return hash_combine(IVI->getOpcode(), IVI->getOperand(0),
143 Inst->getOpcode(),
153 if (LHSI->getOpcode() != RHSI->getOpcode())
242 Inst->getOpcode(),
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 149 if (N.getOpcode() == ISD::TargetConstant ||
150 N.getOpcode() == ISD::TargetGlobalAddress) {
362 if (N->getOpcode() != ISD::Constant)
380 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
390 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
459 return N->getOpcode() == Opc
485 unsigned Opcode = N->getOpcode();
532 unsigned Op0Opc = Op0.getOpcode();
533 unsigned Op1Opc = Op1.getOpcode();
541 if (Op0.getOperand(0).getOpcode() == ISD::SHL |
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| AArch64ConditionalCompares.cpp | 304 switch (I->getOpcode()) {
321 switch (I->getOpcode()) {
615 switch (CmpMI->getOpcode()) {
668 bool isNZ = CmpMI->getOpcode() == AArch64::CBNZW ||
669 CmpMI->getOpcode() == AArch64::CBNZX;
705 switch (CmpMI->getOpcode()) {
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 194 return std::next(I)->getOpcode() == AMDGPU::RETURN;
205 switch (MI->getOpcode()) {
209 if (TII->isLDSRetInstr(MI->getOpcode())) {
210 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
216 MI->getOpcode() == AMDGPU::LDS_CMPST_RET)
220 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode())));
283 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
290 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
542 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
543 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz)
[all...] |
| /external/llvm/lib/IR/ |
| Instructions.cpp | [all...] |
| /dalvik/dx/src/com/android/dx/dex/code/ |
| OutputFinisher.java | 395 result[i] = insns.get(i).getOpcode();
534 guess.getOpcode() != Opcodes.CONST_STRING) {
553 Dop result = findOpcodeForInsn(insn.getLowRegVersion(), insn.getOpcode());
595 Dop originalOpcode = insn.getOpcode();
630 Dop originalOpcode = insn.getOpcode();
738 Dop opcode = insn.getOpcode();
|
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 175 unsigned Opcode = MI->getOpcode();
395 switch (MI->getOpcode()) {
450 unsigned Opc = MBBI->getOpcode();
798 unsigned Opcode = First->getOpcode();
922 unsigned Opcode = FirstMI->getOpcode();
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| SimplifyIndVar.cpp | 97 switch (UseInst->getOpcode()) {
119 if (UseInst->getOpcode() == Instruction::LShr) {
293 bool IsSigned = Rem->getOpcode() == Instruction::SRem;
294 if (IsSigned || Rem->getOpcode() == Instruction::URem) {
360 switch (BO->getOpcode()) {
465 assert((AddInst->getOpcode() == Instruction::Add &&
|
| /external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/Format/ |
| InstructionMethodItem.java | 84 Opcode opcode = instruction.getOpcode();
134 switch (instruction.getOpcode()) {
158 throw new ExceptionWithContext("Invalid 31t opcode: %s", instruction.getOpcode());
178 switch (instruction.getOpcode().format) {
242 if (instruction.getOpcode().setsWideRegister()) {
371 writer.write(instruction.getOpcode().name);
|
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| InsnFormat.java | 46 String op = insn.getOpcode().getName();
409 int opcode = insn.getOpcode().getOpcode();
|
| /dalvik/dx/src/com/android/dx/ssa/ |
| ConstCollector.java | 174 if (insn == null || insn.getOpcode() == null) continue;
184 if (insn.getOpcode().getOpcode() == RegOps.MOVE_RESULT_PSEUDO) {
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| TestAfterDivZeroChecker.cpp | 108 BinaryOperator::Opcode Op = BO->getOpcode();
205 BinaryOperator::Opcode Op = B->getOpcode();
234 if (U->getOpcode() == UO_LNot) {
|
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| ConstCollector.java | 174 if (insn == null || insn.getOpcode() == null) continue;
184 if (insn.getOpcode().getOpcode() == RegOps.MOVE_RESULT_PSEUDO) {
|
