1 //===- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG -*- C++ -*--==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This declares the Emit routines for the SelectionDAG class, which creates 11 // MachineInstrs based on the decisions of the SelectionDAG instruction 12 // selection. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H 17 #define LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H 18 19 #include "llvm/ADT/DenseMap.h" 20 #include "llvm/CodeGen/MachineBasicBlock.h" 21 #include "llvm/CodeGen/SelectionDAG.h" 22 23 namespace llvm { 24 25 class MachineInstrBuilder; 26 class MCInstrDesc; 27 class SDDbgValue; 28 29 class LLVM_LIBRARY_VISIBILITY InstrEmitter { 30 MachineFunction *MF; 31 MachineRegisterInfo *MRI; 32 const TargetInstrInfo *TII; 33 const TargetRegisterInfo *TRI; 34 const TargetLowering *TLI; 35 36 MachineBasicBlock *MBB; 37 MachineBasicBlock::iterator InsertPos; 38 39 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 40 /// implicit physical register output. 41 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, 42 bool IsClone, bool IsCloned, 43 unsigned SrcReg, 44 DenseMap<SDValue, unsigned> &VRBaseMap); 45 46 /// getDstOfCopyToRegUse - If the only use of the specified result number of 47 /// node is a CopyToReg, return its destination register. Return 0 otherwise. 48 unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, 49 unsigned ResNo) const; 50 51 void CreateVirtualRegisters(SDNode *Node, 52 MachineInstrBuilder &MIB, 53 const MCInstrDesc &II, 54 bool IsClone, bool IsCloned, 55 DenseMap<SDValue, unsigned> &VRBaseMap); 56 57 /// getVR - Return the virtual register corresponding to the specified result 58 /// of the specified node. 59 unsigned getVR(SDValue Op, 60 DenseMap<SDValue, unsigned> &VRBaseMap); 61 62 /// AddRegisterOperand - Add the specified register as an operand to the 63 /// specified machine instr. Insert register copies if the register is 64 /// not in the required register class. 65 void AddRegisterOperand(MachineInstrBuilder &MIB, 66 SDValue Op, 67 unsigned IIOpNum, 68 const MCInstrDesc *II, 69 DenseMap<SDValue, unsigned> &VRBaseMap, 70 bool IsDebug, bool IsClone, bool IsCloned); 71 72 /// AddOperand - Add the specified operand to the specified machine instr. II 73 /// specifies the instruction information for the node, and IIOpNum is the 74 /// operand number (in the II) that we are adding. IIOpNum and II are used for 75 /// assertions only. 76 void AddOperand(MachineInstrBuilder &MIB, 77 SDValue Op, 78 unsigned IIOpNum, 79 const MCInstrDesc *II, 80 DenseMap<SDValue, unsigned> &VRBaseMap, 81 bool IsDebug, bool IsClone, bool IsCloned); 82 83 /// ConstrainForSubReg - Try to constrain VReg to a register class that 84 /// supports SubIdx sub-registers. Emit a copy if that isn't possible. 85 /// Return the virtual register to use. 86 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx, 87 MVT VT, DebugLoc DL); 88 89 /// EmitSubregNode - Generate machine code for subreg nodes. 90 /// 91 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap, 92 bool IsClone, bool IsCloned); 93 94 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 95 /// COPY_TO_REGCLASS is just a normal copy, except that the destination 96 /// register is constrained to be in a particular register class. 97 /// 98 void EmitCopyToRegClassNode(SDNode *Node, 99 DenseMap<SDValue, unsigned> &VRBaseMap); 100 101 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 102 /// 103 void EmitRegSequence(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap, 104 bool IsClone, bool IsCloned); 105 public: 106 /// CountResults - The results of target nodes have register or immediate 107 /// operands first, then an optional chain, and optional flag operands 108 /// (which do not go into the machine instrs.) 109 static unsigned CountResults(SDNode *Node); 110 111 /// EmitDbgValue - Generate machine instruction for a dbg_value node. 112 /// 113 MachineInstr *EmitDbgValue(SDDbgValue *SD, 114 DenseMap<SDValue, unsigned> &VRBaseMap); 115 116 /// EmitNode - Generate machine code for a node and needed dependencies. 117 /// 118 void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, 119 DenseMap<SDValue, unsigned> &VRBaseMap) { 120 if (Node->isMachineOpcode()) 121 EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap); 122 else 123 EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap); 124 } 125 126 /// getBlock - Return the current basic block. 127 MachineBasicBlock *getBlock() { return MBB; } 128 129 /// getInsertPos - Return the current insertion position. 130 MachineBasicBlock::iterator getInsertPos() { return InsertPos; } 131 132 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting 133 /// at the given position in the given block. 134 InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos); 135 136 private: 137 void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 138 DenseMap<SDValue, unsigned> &VRBaseMap); 139 void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 140 DenseMap<SDValue, unsigned> &VRBaseMap); 141 }; 142 143 } 144 145 #endif 146
