1 //===-- XCoreISelDAGToDAG.cpp - A dag to dag inst selector for XCore ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines an instruction selector for the XCore target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "XCore.h" 15 #include "XCoreTargetMachine.h" 16 #include "llvm/CodeGen/MachineFrameInfo.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/CodeGen/SelectionDAGISel.h" 22 #include "llvm/IR/CallingConv.h" 23 #include "llvm/IR/Constants.h" 24 #include "llvm/IR/DerivedTypes.h" 25 #include "llvm/IR/Function.h" 26 #include "llvm/IR/Intrinsics.h" 27 #include "llvm/IR/LLVMContext.h" 28 #include "llvm/Support/Compiler.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/raw_ostream.h" 32 #include "llvm/Target/TargetLowering.h" 33 using namespace llvm; 34 35 /// XCoreDAGToDAGISel - XCore specific code to select XCore machine 36 /// instructions for SelectionDAG operations. 37 /// 38 namespace { 39 class XCoreDAGToDAGISel : public SelectionDAGISel { 40 41 public: 42 XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel) 43 : SelectionDAGISel(TM, OptLevel) {} 44 45 SDNode *Select(SDNode *N) override; 46 SDNode *SelectBRIND(SDNode *N); 47 48 /// getI32Imm - Return a target constant with the specified value, of type 49 /// i32. 50 inline SDValue getI32Imm(unsigned Imm, SDLoc dl) { 51 return CurDAG->getTargetConstant(Imm, dl, MVT::i32); 52 } 53 54 inline bool immMskBitp(SDNode *inN) const { 55 ConstantSDNode *N = cast<ConstantSDNode>(inN); 56 uint32_t value = (uint32_t)N->getZExtValue(); 57 if (!isMask_32(value)) { 58 return false; 59 } 60 int msksize = 32 - countLeadingZeros(value); 61 return (msksize >= 1 && msksize <= 8) || 62 msksize == 16 || msksize == 24 || msksize == 32; 63 } 64 65 // Complex Pattern Selectors. 66 bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset); 67 68 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, 69 std::vector<SDValue> &OutOps) override; 70 71 const char *getPassName() const override { 72 return "XCore DAG->DAG Pattern Instruction Selection"; 73 } 74 75 // Include the pieces autogenerated from the target description. 76 #include "XCoreGenDAGISel.inc" 77 }; 78 } // end anonymous namespace 79 80 /// createXCoreISelDag - This pass converts a legalized DAG into a 81 /// XCore-specific DAG, ready for instruction scheduling. 82 /// 83 FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM, 84 CodeGenOpt::Level OptLevel) { 85 return new XCoreDAGToDAGISel(TM, OptLevel); 86 } 87 88 bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base, 89 SDValue &Offset) { 90 FrameIndexSDNode *FIN = nullptr; 91 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) { 92 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 93 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); 94 return true; 95 } 96 if (Addr.getOpcode() == ISD::ADD) { 97 ConstantSDNode *CN = nullptr; 98 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) 99 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) 100 && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { 101 // Constant positive word offset from frame index 102 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 103 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr), 104 MVT::i32); 105 return true; 106 } 107 } 108 return false; 109 } 110 111 bool XCoreDAGToDAGISel:: 112 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, 113 std::vector<SDValue> &OutOps) { 114 SDValue Reg; 115 switch (ConstraintID) { 116 default: return true; 117 case InlineAsm::Constraint_m: // Memory. 118 switch (Op.getOpcode()) { 119 default: return true; 120 case XCoreISD::CPRelativeWrapper: 121 Reg = CurDAG->getRegister(XCore::CP, MVT::i32); 122 break; 123 case XCoreISD::DPRelativeWrapper: 124 Reg = CurDAG->getRegister(XCore::DP, MVT::i32); 125 break; 126 } 127 } 128 OutOps.push_back(Reg); 129 OutOps.push_back(Op.getOperand(0)); 130 return false; 131 } 132 133 SDNode *XCoreDAGToDAGISel::Select(SDNode *N) { 134 SDLoc dl(N); 135 switch (N->getOpcode()) { 136 default: break; 137 case ISD::Constant: { 138 uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue(); 139 if (immMskBitp(N)) { 140 // Transformation function: get the size of a mask 141 // Look for the first non-zero bit 142 SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val), dl); 143 return CurDAG->getMachineNode(XCore::MKMSK_rus, dl, 144 MVT::i32, MskSize); 145 } 146 else if (!isUInt<16>(Val)) { 147 SDValue CPIdx = CurDAG->getTargetConstantPool( 148 ConstantInt::get(Type::getInt32Ty(*CurDAG->getContext()), Val), 149 getTargetLowering()->getPointerTy(CurDAG->getDataLayout())); 150 SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, 151 MVT::Other, CPIdx, 152 CurDAG->getEntryNode()); 153 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 154 MemOp[0] = 155 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF), 156 MachineMemOperand::MOLoad, 4, 4); 157 cast<MachineSDNode>(node)->setMemRefs(MemOp, MemOp + 1); 158 return node; 159 } 160 break; 161 } 162 case XCoreISD::LADD: { 163 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 164 N->getOperand(2) }; 165 return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32, 166 Ops); 167 } 168 case XCoreISD::LSUB: { 169 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 170 N->getOperand(2) }; 171 return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32, 172 Ops); 173 } 174 case XCoreISD::MACCU: { 175 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 176 N->getOperand(2), N->getOperand(3) }; 177 return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32, 178 Ops); 179 } 180 case XCoreISD::MACCS: { 181 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 182 N->getOperand(2), N->getOperand(3) }; 183 return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32, 184 Ops); 185 } 186 case XCoreISD::LMUL: { 187 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 188 N->getOperand(2), N->getOperand(3) }; 189 return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32, 190 Ops); 191 } 192 case XCoreISD::CRC8: { 193 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; 194 return CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32, MVT::i32, 195 Ops); 196 } 197 case ISD::BRIND: 198 if (SDNode *ResNode = SelectBRIND(N)) 199 return ResNode; 200 break; 201 // Other cases are autogenerated. 202 } 203 return SelectCode(N); 204 } 205 206 /// Given a chain return a new chain where any appearance of Old is replaced 207 /// by New. There must be at most one instruction between Old and Chain and 208 /// this instruction must be a TokenFactor. Returns an empty SDValue if 209 /// these conditions don't hold. 210 static SDValue 211 replaceInChain(SelectionDAG *CurDAG, SDValue Chain, SDValue Old, SDValue New) 212 { 213 if (Chain == Old) 214 return New; 215 if (Chain->getOpcode() != ISD::TokenFactor) 216 return SDValue(); 217 SmallVector<SDValue, 8> Ops; 218 bool found = false; 219 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) { 220 if (Chain->getOperand(i) == Old) { 221 Ops.push_back(New); 222 found = true; 223 } else { 224 Ops.push_back(Chain->getOperand(i)); 225 } 226 } 227 if (!found) 228 return SDValue(); 229 return CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, Ops); 230 } 231 232 SDNode *XCoreDAGToDAGISel::SelectBRIND(SDNode *N) { 233 SDLoc dl(N); 234 // (brind (int_xcore_checkevent (addr))) 235 SDValue Chain = N->getOperand(0); 236 SDValue Addr = N->getOperand(1); 237 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN) 238 return nullptr; 239 unsigned IntNo = cast<ConstantSDNode>(Addr->getOperand(1))->getZExtValue(); 240 if (IntNo != Intrinsic::xcore_checkevent) 241 return nullptr; 242 SDValue nextAddr = Addr->getOperand(2); 243 SDValue CheckEventChainOut(Addr.getNode(), 1); 244 if (!CheckEventChainOut.use_empty()) { 245 // If the chain out of the checkevent intrinsic is an operand of the 246 // indirect branch or used in a TokenFactor which is the operand of the 247 // indirect branch then build a new chain which uses the chain coming into 248 // the checkevent intrinsic instead. 249 SDValue CheckEventChainIn = Addr->getOperand(0); 250 SDValue NewChain = replaceInChain(CurDAG, Chain, CheckEventChainOut, 251 CheckEventChainIn); 252 if (!NewChain.getNode()) 253 return nullptr; 254 Chain = NewChain; 255 } 256 // Enable events on the thread using setsr 1 and then disable them immediately 257 // after with clrsr 1. If any resources owned by the thread are ready an event 258 // will be taken. If no resource is ready we branch to the address which was 259 // the operand to the checkevent intrinsic. 260 SDValue constOne = getI32Imm(1, dl); 261 SDValue Glue = 262 SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue, 263 constOne, Chain), 0); 264 Glue = 265 SDValue(CurDAG->getMachineNode(XCore::CLRSR_branch_u6, dl, MVT::Glue, 266 constOne, Glue), 0); 267 if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper && 268 nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) { 269 return CurDAG->SelectNodeTo(N, XCore::BRFU_lu6, MVT::Other, 270 nextAddr->getOperand(0), Glue); 271 } 272 return CurDAG->SelectNodeTo(N, XCore::BAU_1r, MVT::Other, nextAddr, Glue); 273 } 274
