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      1 /* alias.s Test file for AArch64 instructions aliases or disassembly
      2    preference.  It is also used to test the -Mno-aliases option in
      3    the disassemler.
      4 
      5    Copyright (C) 2012-2014 Free Software Foundation, Inc.
      6    Contributed by ARM Ltd.
      7 
      8    This file is part of GAS.
      9 
     10    GAS is free software; you can redistribute it and/or modify
     11    it under the terms of the GNU General Public License as published by
     12    the Free Software Foundation; either version 3 of the license, or
     13    (at your option) any later version.
     14 
     15    GAS is distributed in the hope that it will be useful,
     16    but WITHOUT ANY WARRANTY; without even the implied warranty of
     17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     18    GNU General Public License for more details.
     19 
     20    You should have received a copy of the GNU General Public License
     21    along with this program; see the file COPYING3. If not,
     22    see <http://www.gnu.org/licenses/>.  */
     23 
     24 .text
     25 	extr	w0, w1, w2, #15
     26 	extr	x0, x1, x2, #15
     27 	extr	w0, w3, w3, #7
     28 	extr	x0, x5, x5, #7
     29 	ror	w6, w7, #18
     30 	ror	x6, x7, #40
     31 
     32 	madd	w0, w1, w2, w3
     33 	madd	w0, w1, w2, wzr
     34 	mul	w0, w1, w2
     35 	msub	x0, x1, x2, x3
     36 	msub	x0, x1, x2, xzr
     37 	mneg	x0, x1, x2
     38 	smaddl	x0, w1, w2, x3
     39 	smaddl	x0, w1, w2, xzr
     40 	smull	x0, w1, w2
     41 	smsubl	x0, w1, w2, x3
     42 	smsubl	x0, w1, w2, xzr
     43 	smnegl	x0, w1, w2
     44 	umaddl	x0, w1, w2, x3
     45 	umaddl	x0, w1, w2, xzr
     46 	umull	x0, w1, w2
     47 	umsubl	x0, w1, w2, x3
     48 	umsubl	x0, w1, w2, xzr
     49 	umnegl	x0, w1, w2
     50 
     51 	csinc	w0, w1, wzr, eq
     52 	csinc	w0, w1, w1, eq
     53 	cinc	w0, w1, ne
     54 	csinc	w0, wzr, wzr, lo
     55 	cset	w0, cs
     56 	csinv	x0, x1, xzr, hs
     57 	csinv	x0, x1, x1, hs
     58 	cinv	x0, x1, cc
     59 	csinv	x0, xzr, xzr, mi
     60 	csetm	x0, pl
     61 	csneg	x0, xzr, x30, lt
     62 	csneg	x0, x30, x30, lt
     63 	cneg	x0, x30, ge
     64 
     65 	ands	x0, x1, x2
     66 	ands	xzr, x1, x2
     67 	tst	x1, x2
     68 	ands	wzr, w1, w2, ror #31
     69 	tst	w1, w2, ror #31
     70 
     71 	orn	x0, x1, x2
     72 	orn	xzr, x1, x2
     73 	orn	x0, xzr, x2
     74 	mvn	x0, x2
     75 	orn	wzr, w1, w2, asr #15
     76 	orn	w0, wzr, w2, asr #15
     77 	mvn	w0, w2, asr #15
     78 
     79 	mov	v0.8b, v1.8b
     80 	orr	v0.8b, v1.8b, v2.8b
     81 	orr	v0.8b, v1.8b, v1.8b
     82 
     83 	mov	x3, x17
     84 	orr	x3, x0, x17
     85 	orr	x3, xzr, x17
     86 
     87 	bic	x1, x1, #(1<<30)-1
     88 	bic	x0, x0, #2
     89 	bic	w0, w0, #2
     90 
     91 	ands	wzr, w24, #0x7f8
     92 	ands	w0, w24, #0x7f8
     93 	tst	w24, #0x7f8
     94 
     95 	subs	wzr, w3, #0x20
     96 	subs	w3, wsp, #0x20
     97 	cmp	w3, #0x20
     98 
     99 	adds	xzr, x15, #0xfff
    100 	subs	x15, sp, #0xfff
    101 	cmn	x15, #0xfff
    102 
    103 	.macro asimdshll	s
    104 	 \s\()xtl v8.8h, v2.8b
    105 	 \s\()shll v8.8h, v2.8b, #0
    106 	 \s\()xtl2 v8.8h, v2.16b
    107 	 \s\()shll2 v8.8h, v2.16b, #0
    108 	 \s\()xtl v8.4s, v2.4h
    109 	 \s\()shll v8.4s, v2.4h, #0
    110 	 \s\()xtl2 v8.4s, v2.8h
    111 	 \s\()shll2 v8.4s, v2.8h, #0
    112 	 \s\()xtl v8.2d, v2.2s
    113 	 \s\()shll v8.2d, v2.2s, #0
    114 	 \s\()xtl2 v8.2d, v2.4s
    115 	 \s\()shll2 v8.2d, v2.4s, #0
    116 	.endm
    117 
    118 	asimdshll	s
    119 	asimdshll	u
    120 
    121 	csinc	w0, w1, w1, nv
    122 	csinc	w0, w1, w1, al
    123 	csinc	w0, wzr, wzr, nv
    124 	csinc	w0, wzr, wzr, al
    125 	csinv	w0, w1, w1, nv
    126 	csinv	w0, w1, w1, al
    127 	csinv	w0, wzr, wzr, nv
    128 	csinv	w0, wzr, wzr, al
    129 	csneg	w0, w1, w1, nv
    130 	csneg	w0, w1, w1, al
    131