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  /external/v8/src/mips64/
disasm-mips64.cc     [all...]
constants-mips64.h 661 ADDIUPC = ((0U << 2) + 0),
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assembler-mips64.cc 2151 void Assembler::addiupc(Register rs, int32_t imm19) { function in class:v8::internal::Assembler
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assembler-mips64.h 829 void addiupc(Register rs, int32_t imm19);
    [all...]
macro-assembler-mips64.h     [all...]
code-stubs-mips64.cc     [all...]
simulator-mips64.cc     [all...]
  /art/compiler/utils/mips64/
assembler_mips64_test.cc     [all...]
assembler_mips64.cc 697 void Mips64Assembler::Addiupc(GpuRegister rs, uint32_t imm19) {
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  /external/llvm/test/MC/Disassembler/Mips/micromips32r6/
valid.txt 35 0x78 0x80 0x00 0x19 # CHECK: addiupc $4, 100
  /toolchain/binutils/binutils-2.25/opcodes/
ChangeLog-2011 229 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
micromips-opc.c 329 {"addiu", "mb,mr,mQ", 0x78000000, 0xfc000000, WR_1, RD_pc, I1, 0, 0 }, /* addiupc */
331 {"addiupc", "mb,mQ", 0x78000000, 0xfc000000, WR_1, RD_pc, I1, 0, 0 },
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  /toolchain/binutils/binutils-2.25/include/opcode/
mips.h 606 but the rules for MIPS16 instructions like ADDIUPC are more complicated. */
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  /toolchain/binutils/binutils-2.25/bfd/
elfxx-mips.c     [all...]
  /toolchain/binutils/binutils-2.25/gold/
mips.cc     [all...]
  /external/llvm/lib/Target/Mips/
MicroMipsInstrInfo.td 725 def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
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MicroMips32r6InstrInfo.td 558 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
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  /external/v8/src/mips/
constants-mips.h 631 ADDIUPC = ((0U << 2) + 0),
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assembler-mips.cc 1947 void Assembler::addiupc(Register rs, int32_t imm19) { function in class:v8::Assembler
    [all...]
assembler-mips.h 781 void addiupc(Register rs, int32_t imm19);
    [all...]
macro-assembler-mips.h     [all...]
simulator-mips.cc     [all...]
code-stubs-mips.cc     [all...]
  /art/compiler/utils/mips/
assembler_mips.cc 898 void MipsAssembler::Addiupc(Register rs, uint32_t imm19) {
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  /toolchain/binutils/binutils-2.25/bfd/po/
fi.po     [all...]

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12 3