1 //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file includes code for rendering MCInst instances as Intel-style 11 // assembly. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "X86IntelInstPrinter.h" 16 #include "MCTargetDesc/X86BaseInfo.h" 17 #include "MCTargetDesc/X86MCTargetDesc.h" 18 #include "X86InstComments.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include "llvm/Support/ErrorHandling.h" 23 #include "llvm/Support/FormattedStream.h" 24 #include <cctype> 25 using namespace llvm; 26 27 #define DEBUG_TYPE "asm-printer" 28 29 #include "X86GenAsmWriter1.inc" 30 31 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 32 OS << getRegisterName(RegNo); 33 } 34 35 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, 36 StringRef Annot, 37 const MCSubtargetInfo &STI) { 38 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 39 uint64_t TSFlags = Desc.TSFlags; 40 41 if (TSFlags & X86II::LOCK) 42 OS << "\tlock\n"; 43 44 printInstruction(MI, OS); 45 46 // Next always print the annotation. 47 printAnnotation(OS, Annot); 48 49 // If verbose assembly is enabled, we can print some informative comments. 50 if (CommentStream) 51 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName); 52 } 53 54 void X86IntelInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op, 55 raw_ostream &O) { 56 int64_t Imm = MI->getOperand(Op).getImm(); 57 switch (Imm) { 58 default: llvm_unreachable("Invalid avxcc argument!"); 59 case 0: O << "eq"; break; 60 case 1: O << "lt"; break; 61 case 2: O << "le"; break; 62 case 3: O << "unord"; break; 63 case 4: O << "neq"; break; 64 case 5: O << "nlt"; break; 65 case 6: O << "nle"; break; 66 case 7: O << "ord"; break; 67 case 8: O << "eq_uq"; break; 68 case 9: O << "nge"; break; 69 case 0xa: O << "ngt"; break; 70 case 0xb: O << "false"; break; 71 case 0xc: O << "neq_oq"; break; 72 case 0xd: O << "ge"; break; 73 case 0xe: O << "gt"; break; 74 case 0xf: O << "true"; break; 75 case 0x10: O << "eq_os"; break; 76 case 0x11: O << "lt_oq"; break; 77 case 0x12: O << "le_oq"; break; 78 case 0x13: O << "unord_s"; break; 79 case 0x14: O << "neq_us"; break; 80 case 0x15: O << "nlt_uq"; break; 81 case 0x16: O << "nle_uq"; break; 82 case 0x17: O << "ord_s"; break; 83 case 0x18: O << "eq_us"; break; 84 case 0x19: O << "nge_uq"; break; 85 case 0x1a: O << "ngt_uq"; break; 86 case 0x1b: O << "false_os"; break; 87 case 0x1c: O << "neq_os"; break; 88 case 0x1d: O << "ge_oq"; break; 89 case 0x1e: O << "gt_oq"; break; 90 case 0x1f: O << "true_us"; break; 91 } 92 } 93 94 void X86IntelInstPrinter::printXOPCC(const MCInst *MI, unsigned Op, 95 raw_ostream &O) { 96 int64_t Imm = MI->getOperand(Op).getImm(); 97 switch (Imm) { 98 default: llvm_unreachable("Invalid xopcc argument!"); 99 case 0: O << "lt"; break; 100 case 1: O << "le"; break; 101 case 2: O << "gt"; break; 102 case 3: O << "ge"; break; 103 case 4: O << "eq"; break; 104 case 5: O << "neq"; break; 105 case 6: O << "false"; break; 106 case 7: O << "true"; break; 107 } 108 } 109 110 void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op, 111 raw_ostream &O) { 112 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; 113 switch (Imm) { 114 case 0: O << "{rn-sae}"; break; 115 case 1: O << "{rd-sae}"; break; 116 case 2: O << "{ru-sae}"; break; 117 case 3: O << "{rz-sae}"; break; 118 } 119 } 120 121 /// printPCRelImm - This is used to print an immediate value that ends up 122 /// being encoded as a pc-relative value. 123 void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo, 124 raw_ostream &O) { 125 const MCOperand &Op = MI->getOperand(OpNo); 126 if (Op.isImm()) 127 O << formatImm(Op.getImm()); 128 else { 129 assert(Op.isExpr() && "unknown pcrel immediate operand"); 130 // If a symbolic branch target was added as a constant expression then print 131 // that address in hex. 132 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); 133 int64_t Address; 134 if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) { 135 O << formatHex((uint64_t)Address); 136 } 137 else { 138 // Otherwise, just print the expression. 139 Op.getExpr()->print(O, &MAI); 140 } 141 } 142 } 143 144 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 145 raw_ostream &O) { 146 const MCOperand &Op = MI->getOperand(OpNo); 147 if (Op.isReg()) { 148 printRegName(O, Op.getReg()); 149 } else if (Op.isImm()) { 150 O << formatImm((int64_t)Op.getImm()); 151 } else { 152 assert(Op.isExpr() && "unknown operand kind in printOperand"); 153 Op.getExpr()->print(O, &MAI); 154 } 155 } 156 157 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op, 158 raw_ostream &O) { 159 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); 160 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); 161 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); 162 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); 163 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg); 164 165 // If this has a segment register, print it. 166 if (SegReg.getReg()) { 167 printOperand(MI, Op+X86::AddrSegmentReg, O); 168 O << ':'; 169 } 170 171 O << '['; 172 173 bool NeedPlus = false; 174 if (BaseReg.getReg()) { 175 printOperand(MI, Op+X86::AddrBaseReg, O); 176 NeedPlus = true; 177 } 178 179 if (IndexReg.getReg()) { 180 if (NeedPlus) O << " + "; 181 if (ScaleVal != 1) 182 O << ScaleVal << '*'; 183 printOperand(MI, Op+X86::AddrIndexReg, O); 184 NeedPlus = true; 185 } 186 187 if (!DispSpec.isImm()) { 188 if (NeedPlus) O << " + "; 189 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?"); 190 DispSpec.getExpr()->print(O, &MAI); 191 } else { 192 int64_t DispVal = DispSpec.getImm(); 193 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { 194 if (NeedPlus) { 195 if (DispVal > 0) 196 O << " + "; 197 else { 198 O << " - "; 199 DispVal = -DispVal; 200 } 201 } 202 O << formatImm(DispVal); 203 } 204 } 205 206 O << ']'; 207 } 208 209 void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op, 210 raw_ostream &O) { 211 const MCOperand &SegReg = MI->getOperand(Op+1); 212 213 // If this has a segment register, print it. 214 if (SegReg.getReg()) { 215 printOperand(MI, Op+1, O); 216 O << ':'; 217 } 218 O << '['; 219 printOperand(MI, Op, O); 220 O << ']'; 221 } 222 223 void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op, 224 raw_ostream &O) { 225 // DI accesses are always ES-based. 226 O << "es:["; 227 printOperand(MI, Op, O); 228 O << ']'; 229 } 230 231 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op, 232 raw_ostream &O) { 233 const MCOperand &DispSpec = MI->getOperand(Op); 234 const MCOperand &SegReg = MI->getOperand(Op+1); 235 236 // If this has a segment register, print it. 237 if (SegReg.getReg()) { 238 printOperand(MI, Op+1, O); 239 O << ':'; 240 } 241 242 O << '['; 243 244 if (DispSpec.isImm()) { 245 O << formatImm(DispSpec.getImm()); 246 } else { 247 assert(DispSpec.isExpr() && "non-immediate displacement?"); 248 DispSpec.getExpr()->print(O, &MAI); 249 } 250 251 O << ']'; 252 } 253 254 void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op, 255 raw_ostream &O) { 256 O << formatImm(MI->getOperand(Op).getImm() & 0xff); 257 } 258
