1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the X86-specific support for the FastISel class. Much 11 // of the target-specific code is generated by tablegen in the file 12 // X86GenFastISel.inc, which is #included here. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86.h" 17 #include "X86InstrBuilder.h" 18 #include "X86ISelLowering.h" 19 #include "X86RegisterInfo.h" 20 #include "X86Subtarget.h" 21 #include "X86TargetMachine.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/DerivedTypes.h" 24 #include "llvm/GlobalVariable.h" 25 #include "llvm/GlobalAlias.h" 26 #include "llvm/Instructions.h" 27 #include "llvm/IntrinsicInst.h" 28 #include "llvm/Operator.h" 29 #include "llvm/CodeGen/Analysis.h" 30 #include "llvm/CodeGen/FastISel.h" 31 #include "llvm/CodeGen/FunctionLoweringInfo.h" 32 #include "llvm/CodeGen/MachineConstantPool.h" 33 #include "llvm/CodeGen/MachineFrameInfo.h" 34 #include "llvm/CodeGen/MachineRegisterInfo.h" 35 #include "llvm/Support/CallSite.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/GetElementPtrTypeIterator.h" 38 #include "llvm/Target/TargetOptions.h" 39 using namespace llvm; 40 41 namespace { 42 43 class X86FastISel : public FastISel { 44 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 45 /// make the right decision when generating code for different targets. 46 const X86Subtarget *Subtarget; 47 48 /// StackPtr - Register used as the stack pointer. 49 /// 50 unsigned StackPtr; 51 52 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 53 /// floating point ops. 54 /// When SSE is available, use it for f32 operations. 55 /// When SSE2 is available, use it for f64 operations. 56 bool X86ScalarSSEf64; 57 bool X86ScalarSSEf32; 58 59 public: 60 explicit X86FastISel(FunctionLoweringInfo &funcInfo) : FastISel(funcInfo) { 61 Subtarget = &TM.getSubtarget<X86Subtarget>(); 62 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 63 X86ScalarSSEf64 = Subtarget->hasSSE2() || Subtarget->hasAVX(); 64 X86ScalarSSEf32 = Subtarget->hasSSE1() || Subtarget->hasAVX(); 65 } 66 67 virtual bool TargetSelectInstruction(const Instruction *I); 68 69 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that 70 /// vreg is being provided by the specified load instruction. If possible, 71 /// try to fold the load as an operand to the instruction, returning true if 72 /// possible. 73 virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo, 74 const LoadInst *LI); 75 76 #include "X86GenFastISel.inc" 77 78 private: 79 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT); 80 81 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR); 82 83 bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM); 84 bool X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM); 85 86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 87 unsigned &ResultReg); 88 89 bool X86SelectAddress(const Value *V, X86AddressMode &AM); 90 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM); 91 92 bool X86SelectLoad(const Instruction *I); 93 94 bool X86SelectStore(const Instruction *I); 95 96 bool X86SelectRet(const Instruction *I); 97 98 bool X86SelectCmp(const Instruction *I); 99 100 bool X86SelectZExt(const Instruction *I); 101 102 bool X86SelectBranch(const Instruction *I); 103 104 bool X86SelectShift(const Instruction *I); 105 106 bool X86SelectSelect(const Instruction *I); 107 108 bool X86SelectTrunc(const Instruction *I); 109 110 bool X86SelectFPExt(const Instruction *I); 111 bool X86SelectFPTrunc(const Instruction *I); 112 113 bool X86VisitIntrinsicCall(const IntrinsicInst &I); 114 bool X86SelectCall(const Instruction *I); 115 116 bool DoSelectCall(const Instruction *I, const char *MemIntName); 117 118 const X86InstrInfo *getInstrInfo() const { 119 return getTargetMachine()->getInstrInfo(); 120 } 121 const X86TargetMachine *getTargetMachine() const { 122 return static_cast<const X86TargetMachine *>(&TM); 123 } 124 125 unsigned TargetMaterializeConstant(const Constant *C); 126 127 unsigned TargetMaterializeAlloca(const AllocaInst *C); 128 129 unsigned TargetMaterializeFloatZero(const ConstantFP *CF); 130 131 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 132 /// computed in an SSE register, not on the X87 floating point stack. 133 bool isScalarFPTypeInSSEReg(EVT VT) const { 134 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 135 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 136 } 137 138 bool isTypeLegal(Type *Ty, MVT &VT, bool AllowI1 = false); 139 140 bool IsMemcpySmall(uint64_t Len); 141 142 bool TryEmitSmallMemcpy(X86AddressMode DestAM, 143 X86AddressMode SrcAM, uint64_t Len); 144 }; 145 146 } // end anonymous namespace. 147 148 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) { 149 EVT evt = TLI.getValueType(Ty, /*HandleUnknown=*/true); 150 if (evt == MVT::Other || !evt.isSimple()) 151 // Unhandled type. Halt "fast" selection and bail. 152 return false; 153 154 VT = evt.getSimpleVT(); 155 // For now, require SSE/SSE2 for performing floating-point operations, 156 // since x87 requires additional work. 157 if (VT == MVT::f64 && !X86ScalarSSEf64) 158 return false; 159 if (VT == MVT::f32 && !X86ScalarSSEf32) 160 return false; 161 // Similarly, no f80 support yet. 162 if (VT == MVT::f80) 163 return false; 164 // We only handle legal types. For example, on x86-32 the instruction 165 // selector contains all of the 64-bit instructions from x86-64, 166 // under the assumption that i64 won't be used if the target doesn't 167 // support it. 168 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT); 169 } 170 171 #include "X86GenCallingConv.inc" 172 173 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT. 174 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV. 175 /// Return true and the result register by reference if it is possible. 176 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, 177 unsigned &ResultReg) { 178 // Get opcode and regclass of the output for the given load instruction. 179 unsigned Opc = 0; 180 const TargetRegisterClass *RC = NULL; 181 switch (VT.getSimpleVT().SimpleTy) { 182 default: return false; 183 case MVT::i1: 184 case MVT::i8: 185 Opc = X86::MOV8rm; 186 RC = X86::GR8RegisterClass; 187 break; 188 case MVT::i16: 189 Opc = X86::MOV16rm; 190 RC = X86::GR16RegisterClass; 191 break; 192 case MVT::i32: 193 Opc = X86::MOV32rm; 194 RC = X86::GR32RegisterClass; 195 break; 196 case MVT::i64: 197 // Must be in x86-64 mode. 198 Opc = X86::MOV64rm; 199 RC = X86::GR64RegisterClass; 200 break; 201 case MVT::f32: 202 if (X86ScalarSSEf32) { 203 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm; 204 RC = X86::FR32RegisterClass; 205 } else { 206 Opc = X86::LD_Fp32m; 207 RC = X86::RFP32RegisterClass; 208 } 209 break; 210 case MVT::f64: 211 if (X86ScalarSSEf64) { 212 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm; 213 RC = X86::FR64RegisterClass; 214 } else { 215 Opc = X86::LD_Fp64m; 216 RC = X86::RFP64RegisterClass; 217 } 218 break; 219 case MVT::f80: 220 // No f80 support yet. 221 return false; 222 } 223 224 ResultReg = createResultReg(RC); 225 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 226 DL, TII.get(Opc), ResultReg), AM); 227 return true; 228 } 229 230 /// X86FastEmitStore - Emit a machine instruction to store a value Val of 231 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr 232 /// and a displacement offset, or a GlobalAddress, 233 /// i.e. V. Return true if it is possible. 234 bool 235 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM) { 236 // Get opcode and regclass of the output for the given store instruction. 237 unsigned Opc = 0; 238 switch (VT.getSimpleVT().SimpleTy) { 239 case MVT::f80: // No f80 support yet. 240 default: return false; 241 case MVT::i1: { 242 // Mask out all but lowest bit. 243 unsigned AndResult = createResultReg(X86::GR8RegisterClass); 244 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 245 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1); 246 Val = AndResult; 247 } 248 // FALLTHROUGH, handling i1 as i8. 249 case MVT::i8: Opc = X86::MOV8mr; break; 250 case MVT::i16: Opc = X86::MOV16mr; break; 251 case MVT::i32: Opc = X86::MOV32mr; break; 252 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode. 253 case MVT::f32: 254 Opc = X86ScalarSSEf32 ? 255 (Subtarget->hasAVX() ? X86::VMOVSSmr : X86::MOVSSmr) : X86::ST_Fp32m; 256 break; 257 case MVT::f64: 258 Opc = X86ScalarSSEf64 ? 259 (Subtarget->hasAVX() ? X86::VMOVSDmr : X86::MOVSDmr) : X86::ST_Fp64m; 260 break; 261 } 262 263 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 264 DL, TII.get(Opc)), AM).addReg(Val); 265 return true; 266 } 267 268 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val, 269 const X86AddressMode &AM) { 270 // Handle 'null' like i32/i64 0. 271 if (isa<ConstantPointerNull>(Val)) 272 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext())); 273 274 // If this is a store of a simple constant, fold the constant into the store. 275 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) { 276 unsigned Opc = 0; 277 bool Signed = true; 278 switch (VT.getSimpleVT().SimpleTy) { 279 default: break; 280 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8. 281 case MVT::i8: Opc = X86::MOV8mi; break; 282 case MVT::i16: Opc = X86::MOV16mi; break; 283 case MVT::i32: Opc = X86::MOV32mi; break; 284 case MVT::i64: 285 // Must be a 32-bit sign extended value. 286 if ((int)CI->getSExtValue() == CI->getSExtValue()) 287 Opc = X86::MOV64mi32; 288 break; 289 } 290 291 if (Opc) { 292 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 293 DL, TII.get(Opc)), AM) 294 .addImm(Signed ? (uint64_t) CI->getSExtValue() : 295 CI->getZExtValue()); 296 return true; 297 } 298 } 299 300 unsigned ValReg = getRegForValue(Val); 301 if (ValReg == 0) 302 return false; 303 304 return X86FastEmitStore(VT, ValReg, AM); 305 } 306 307 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of 308 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 309 /// ISD::SIGN_EXTEND). 310 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, 311 unsigned Src, EVT SrcVT, 312 unsigned &ResultReg) { 313 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, 314 Src, /*TODO: Kill=*/false); 315 316 if (RR != 0) { 317 ResultReg = RR; 318 return true; 319 } else 320 return false; 321 } 322 323 /// X86SelectAddress - Attempt to fill in an address from the given value. 324 /// 325 bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) { 326 const User *U = NULL; 327 unsigned Opcode = Instruction::UserOp1; 328 if (const Instruction *I = dyn_cast<Instruction>(V)) { 329 // Don't walk into other basic blocks; it's possible we haven't 330 // visited them yet, so the instructions may not yet be assigned 331 // virtual registers. 332 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(V)) || 333 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) { 334 Opcode = I->getOpcode(); 335 U = I; 336 } 337 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 338 Opcode = C->getOpcode(); 339 U = C; 340 } 341 342 if (PointerType *Ty = dyn_cast<PointerType>(V->getType())) 343 if (Ty->getAddressSpace() > 255) 344 // Fast instruction selection doesn't support the special 345 // address spaces. 346 return false; 347 348 switch (Opcode) { 349 default: break; 350 case Instruction::BitCast: 351 // Look past bitcasts. 352 return X86SelectAddress(U->getOperand(0), AM); 353 354 case Instruction::IntToPtr: 355 // Look past no-op inttoptrs. 356 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 357 return X86SelectAddress(U->getOperand(0), AM); 358 break; 359 360 case Instruction::PtrToInt: 361 // Look past no-op ptrtoints. 362 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 363 return X86SelectAddress(U->getOperand(0), AM); 364 break; 365 366 case Instruction::Alloca: { 367 // Do static allocas. 368 const AllocaInst *A = cast<AllocaInst>(V); 369 DenseMap<const AllocaInst*, int>::iterator SI = 370 FuncInfo.StaticAllocaMap.find(A); 371 if (SI != FuncInfo.StaticAllocaMap.end()) { 372 AM.BaseType = X86AddressMode::FrameIndexBase; 373 AM.Base.FrameIndex = SI->second; 374 return true; 375 } 376 break; 377 } 378 379 case Instruction::Add: { 380 // Adds of constants are common and easy enough. 381 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) { 382 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue(); 383 // They have to fit in the 32-bit signed displacement field though. 384 if (isInt<32>(Disp)) { 385 AM.Disp = (uint32_t)Disp; 386 return X86SelectAddress(U->getOperand(0), AM); 387 } 388 } 389 break; 390 } 391 392 case Instruction::GetElementPtr: { 393 X86AddressMode SavedAM = AM; 394 395 // Pattern-match simple GEPs. 396 uint64_t Disp = (int32_t)AM.Disp; 397 unsigned IndexReg = AM.IndexReg; 398 unsigned Scale = AM.Scale; 399 gep_type_iterator GTI = gep_type_begin(U); 400 // Iterate through the indices, folding what we can. Constants can be 401 // folded, and one dynamic index can be handled, if the scale is supported. 402 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); 403 i != e; ++i, ++GTI) { 404 const Value *Op = *i; 405 if (StructType *STy = dyn_cast<StructType>(*GTI)) { 406 const StructLayout *SL = TD.getStructLayout(STy); 407 Disp += SL->getElementOffset(cast<ConstantInt>(Op)->getZExtValue()); 408 continue; 409 } 410 411 // A array/variable index is always of the form i*S where S is the 412 // constant scale size. See if we can push the scale into immediates. 413 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType()); 414 for (;;) { 415 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 416 // Constant-offset addressing. 417 Disp += CI->getSExtValue() * S; 418 break; 419 } 420 if (isa<AddOperator>(Op) && 421 (!isa<Instruction>(Op) || 422 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()] 423 == FuncInfo.MBB) && 424 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) { 425 // An add (in the same block) with a constant operand. Fold the 426 // constant. 427 ConstantInt *CI = 428 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1)); 429 Disp += CI->getSExtValue() * S; 430 // Iterate on the other operand. 431 Op = cast<AddOperator>(Op)->getOperand(0); 432 continue; 433 } 434 if (IndexReg == 0 && 435 (!AM.GV || !Subtarget->isPICStyleRIPRel()) && 436 (S == 1 || S == 2 || S == 4 || S == 8)) { 437 // Scaled-index addressing. 438 Scale = S; 439 IndexReg = getRegForGEPIndex(Op).first; 440 if (IndexReg == 0) 441 return false; 442 break; 443 } 444 // Unsupported. 445 goto unsupported_gep; 446 } 447 } 448 // Check for displacement overflow. 449 if (!isInt<32>(Disp)) 450 break; 451 // Ok, the GEP indices were covered by constant-offset and scaled-index 452 // addressing. Update the address state and move on to examining the base. 453 AM.IndexReg = IndexReg; 454 AM.Scale = Scale; 455 AM.Disp = (uint32_t)Disp; 456 if (X86SelectAddress(U->getOperand(0), AM)) 457 return true; 458 459 // If we couldn't merge the gep value into this addr mode, revert back to 460 // our address and just match the value instead of completely failing. 461 AM = SavedAM; 462 break; 463 unsupported_gep: 464 // Ok, the GEP indices weren't all covered. 465 break; 466 } 467 } 468 469 // Handle constant address. 470 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 471 // Can't handle alternate code models yet. 472 if (TM.getCodeModel() != CodeModel::Small) 473 return false; 474 475 // Can't handle TLS yet. 476 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 477 if (GVar->isThreadLocal()) 478 return false; 479 480 // Can't handle TLS yet, part 2 (this is slightly crazy, but this is how 481 // it works...). 482 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 483 if (const GlobalVariable *GVar = 484 dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false))) 485 if (GVar->isThreadLocal()) 486 return false; 487 488 // RIP-relative addresses can't have additional register operands, so if 489 // we've already folded stuff into the addressing mode, just force the 490 // global value into its own register, which we can use as the basereg. 491 if (!Subtarget->isPICStyleRIPRel() || 492 (AM.Base.Reg == 0 && AM.IndexReg == 0)) { 493 // Okay, we've committed to selecting this global. Set up the address. 494 AM.GV = GV; 495 496 // Allow the subtarget to classify the global. 497 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM); 498 499 // If this reference is relative to the pic base, set it now. 500 if (isGlobalRelativeToPICBase(GVFlags)) { 501 // FIXME: How do we know Base.Reg is free?? 502 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF); 503 } 504 505 // Unless the ABI requires an extra load, return a direct reference to 506 // the global. 507 if (!isGlobalStubReference(GVFlags)) { 508 if (Subtarget->isPICStyleRIPRel()) { 509 // Use rip-relative addressing if we can. Above we verified that the 510 // base and index registers are unused. 511 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 512 AM.Base.Reg = X86::RIP; 513 } 514 AM.GVOpFlags = GVFlags; 515 return true; 516 } 517 518 // Ok, we need to do a load from a stub. If we've already loaded from 519 // this stub, reuse the loaded pointer, otherwise emit the load now. 520 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V); 521 unsigned LoadReg; 522 if (I != LocalValueMap.end() && I->second != 0) { 523 LoadReg = I->second; 524 } else { 525 // Issue load from stub. 526 unsigned Opc = 0; 527 const TargetRegisterClass *RC = NULL; 528 X86AddressMode StubAM; 529 StubAM.Base.Reg = AM.Base.Reg; 530 StubAM.GV = GV; 531 StubAM.GVOpFlags = GVFlags; 532 533 // Prepare for inserting code in the local-value area. 534 SavePoint SaveInsertPt = enterLocalValueArea(); 535 536 if (TLI.getPointerTy() == MVT::i64) { 537 Opc = X86::MOV64rm; 538 RC = X86::GR64RegisterClass; 539 540 if (Subtarget->isPICStyleRIPRel()) 541 StubAM.Base.Reg = X86::RIP; 542 } else { 543 Opc = X86::MOV32rm; 544 RC = X86::GR32RegisterClass; 545 } 546 547 LoadReg = createResultReg(RC); 548 MachineInstrBuilder LoadMI = 549 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), LoadReg); 550 addFullAddress(LoadMI, StubAM); 551 552 // Ok, back to normal mode. 553 leaveLocalValueArea(SaveInsertPt); 554 555 // Prevent loading GV stub multiple times in same MBB. 556 LocalValueMap[V] = LoadReg; 557 } 558 559 // Now construct the final address. Note that the Disp, Scale, 560 // and Index values may already be set here. 561 AM.Base.Reg = LoadReg; 562 AM.GV = 0; 563 return true; 564 } 565 } 566 567 // If all else fails, try to materialize the value in a register. 568 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 569 if (AM.Base.Reg == 0) { 570 AM.Base.Reg = getRegForValue(V); 571 return AM.Base.Reg != 0; 572 } 573 if (AM.IndexReg == 0) { 574 assert(AM.Scale == 1 && "Scale with no index!"); 575 AM.IndexReg = getRegForValue(V); 576 return AM.IndexReg != 0; 577 } 578 } 579 580 return false; 581 } 582 583 /// X86SelectCallAddress - Attempt to fill in an address from the given value. 584 /// 585 bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) { 586 const User *U = NULL; 587 unsigned Opcode = Instruction::UserOp1; 588 if (const Instruction *I = dyn_cast<Instruction>(V)) { 589 Opcode = I->getOpcode(); 590 U = I; 591 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 592 Opcode = C->getOpcode(); 593 U = C; 594 } 595 596 switch (Opcode) { 597 default: break; 598 case Instruction::BitCast: 599 // Look past bitcasts. 600 return X86SelectCallAddress(U->getOperand(0), AM); 601 602 case Instruction::IntToPtr: 603 // Look past no-op inttoptrs. 604 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 605 return X86SelectCallAddress(U->getOperand(0), AM); 606 break; 607 608 case Instruction::PtrToInt: 609 // Look past no-op ptrtoints. 610 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 611 return X86SelectCallAddress(U->getOperand(0), AM); 612 break; 613 } 614 615 // Handle constant address. 616 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 617 // Can't handle alternate code models yet. 618 if (TM.getCodeModel() != CodeModel::Small) 619 return false; 620 621 // RIP-relative addresses can't have additional register operands. 622 if (Subtarget->isPICStyleRIPRel() && 623 (AM.Base.Reg != 0 || AM.IndexReg != 0)) 624 return false; 625 626 // Can't handle DLLImport. 627 if (GV->hasDLLImportLinkage()) 628 return false; 629 630 // Can't handle TLS. 631 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 632 if (GVar->isThreadLocal()) 633 return false; 634 635 // Okay, we've committed to selecting this global. Set up the basic address. 636 AM.GV = GV; 637 638 // No ABI requires an extra load for anything other than DLLImport, which 639 // we rejected above. Return a direct reference to the global. 640 if (Subtarget->isPICStyleRIPRel()) { 641 // Use rip-relative addressing if we can. Above we verified that the 642 // base and index registers are unused. 643 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 644 AM.Base.Reg = X86::RIP; 645 } else if (Subtarget->isPICStyleStubPIC()) { 646 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET; 647 } else if (Subtarget->isPICStyleGOT()) { 648 AM.GVOpFlags = X86II::MO_GOTOFF; 649 } 650 651 return true; 652 } 653 654 // If all else fails, try to materialize the value in a register. 655 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 656 if (AM.Base.Reg == 0) { 657 AM.Base.Reg = getRegForValue(V); 658 return AM.Base.Reg != 0; 659 } 660 if (AM.IndexReg == 0) { 661 assert(AM.Scale == 1 && "Scale with no index!"); 662 AM.IndexReg = getRegForValue(V); 663 return AM.IndexReg != 0; 664 } 665 } 666 667 return false; 668 } 669 670 671 /// X86SelectStore - Select and emit code to implement store instructions. 672 bool X86FastISel::X86SelectStore(const Instruction *I) { 673 // Atomic stores need special handling. 674 if (cast<StoreInst>(I)->isAtomic()) 675 return false; 676 677 MVT VT; 678 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true)) 679 return false; 680 681 X86AddressMode AM; 682 if (!X86SelectAddress(I->getOperand(1), AM)) 683 return false; 684 685 return X86FastEmitStore(VT, I->getOperand(0), AM); 686 } 687 688 /// X86SelectRet - Select and emit code to implement ret instructions. 689 bool X86FastISel::X86SelectRet(const Instruction *I) { 690 const ReturnInst *Ret = cast<ReturnInst>(I); 691 const Function &F = *I->getParent()->getParent(); 692 693 if (!FuncInfo.CanLowerReturn) 694 return false; 695 696 CallingConv::ID CC = F.getCallingConv(); 697 if (CC != CallingConv::C && 698 CC != CallingConv::Fast && 699 CC != CallingConv::X86_FastCall) 700 return false; 701 702 if (Subtarget->isTargetWin64()) 703 return false; 704 705 // Don't handle popping bytes on return for now. 706 if (FuncInfo.MF->getInfo<X86MachineFunctionInfo>() 707 ->getBytesToPopOnReturn() != 0) 708 return 0; 709 710 // fastcc with -tailcallopt is intended to provide a guaranteed 711 // tail call optimization. Fastisel doesn't know how to do that. 712 if (CC == CallingConv::Fast && GuaranteedTailCallOpt) 713 return false; 714 715 // Let SDISel handle vararg functions. 716 if (F.isVarArg()) 717 return false; 718 719 if (Ret->getNumOperands() > 0) { 720 SmallVector<ISD::OutputArg, 4> Outs; 721 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 722 Outs, TLI); 723 724 // Analyze operands of the call, assigning locations to each operand. 725 SmallVector<CCValAssign, 16> ValLocs; 726 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, 727 I->getContext()); 728 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 729 730 const Value *RV = Ret->getOperand(0); 731 unsigned Reg = getRegForValue(RV); 732 if (Reg == 0) 733 return false; 734 735 // Only handle a single return value for now. 736 if (ValLocs.size() != 1) 737 return false; 738 739 CCValAssign &VA = ValLocs[0]; 740 741 // Don't bother handling odd stuff for now. 742 if (VA.getLocInfo() != CCValAssign::Full) 743 return false; 744 // Only handle register returns for now. 745 if (!VA.isRegLoc()) 746 return false; 747 748 // The calling-convention tables for x87 returns don't tell 749 // the whole story. 750 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 751 return false; 752 753 unsigned SrcReg = Reg + VA.getValNo(); 754 EVT SrcVT = TLI.getValueType(RV->getType()); 755 EVT DstVT = VA.getValVT(); 756 // Special handling for extended integers. 757 if (SrcVT != DstVT) { 758 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) 759 return false; 760 761 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) 762 return false; 763 764 assert(DstVT == MVT::i32 && "X86 should always ext to i32"); 765 766 if (SrcVT == MVT::i1) { 767 if (Outs[0].Flags.isSExt()) 768 return false; 769 SrcReg = FastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false); 770 SrcVT = MVT::i8; 771 } 772 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : 773 ISD::SIGN_EXTEND; 774 SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, 775 SrcReg, /*TODO: Kill=*/false); 776 } 777 778 // Make the copy. 779 unsigned DstReg = VA.getLocReg(); 780 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); 781 // Avoid a cross-class copy. This is very unlikely. 782 if (!SrcRC->contains(DstReg)) 783 return false; 784 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 785 DstReg).addReg(SrcReg); 786 787 // Mark the register as live out of the function. 788 MRI.addLiveOut(VA.getLocReg()); 789 } 790 791 // Now emit the RET. 792 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET)); 793 return true; 794 } 795 796 /// X86SelectLoad - Select and emit code to implement load instructions. 797 /// 798 bool X86FastISel::X86SelectLoad(const Instruction *I) { 799 // Atomic loads need special handling. 800 if (cast<LoadInst>(I)->isAtomic()) 801 return false; 802 803 MVT VT; 804 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true)) 805 return false; 806 807 X86AddressMode AM; 808 if (!X86SelectAddress(I->getOperand(0), AM)) 809 return false; 810 811 unsigned ResultReg = 0; 812 if (X86FastEmitLoad(VT, AM, ResultReg)) { 813 UpdateValueMap(I, ResultReg); 814 return true; 815 } 816 return false; 817 } 818 819 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) { 820 bool HasAVX = Subtarget->hasAVX(); 821 bool X86ScalarSSEf32 = HasAVX || Subtarget->hasSSE1(); 822 bool X86ScalarSSEf64 = HasAVX || Subtarget->hasSSE2(); 823 824 switch (VT.getSimpleVT().SimpleTy) { 825 default: return 0; 826 case MVT::i8: return X86::CMP8rr; 827 case MVT::i16: return X86::CMP16rr; 828 case MVT::i32: return X86::CMP32rr; 829 case MVT::i64: return X86::CMP64rr; 830 case MVT::f32: 831 return X86ScalarSSEf32 ? (HasAVX ? X86::VUCOMISSrr : X86::UCOMISSrr) : 0; 832 case MVT::f64: 833 return X86ScalarSSEf64 ? (HasAVX ? X86::VUCOMISDrr : X86::UCOMISDrr) : 0; 834 } 835 } 836 837 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS 838 /// of the comparison, return an opcode that works for the compare (e.g. 839 /// CMP32ri) otherwise return 0. 840 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) { 841 switch (VT.getSimpleVT().SimpleTy) { 842 // Otherwise, we can't fold the immediate into this comparison. 843 default: return 0; 844 case MVT::i8: return X86::CMP8ri; 845 case MVT::i16: return X86::CMP16ri; 846 case MVT::i32: return X86::CMP32ri; 847 case MVT::i64: 848 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext 849 // field. 850 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue()) 851 return X86::CMP64ri32; 852 return 0; 853 } 854 } 855 856 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1, 857 EVT VT) { 858 unsigned Op0Reg = getRegForValue(Op0); 859 if (Op0Reg == 0) return false; 860 861 // Handle 'null' like i32/i64 0. 862 if (isa<ConstantPointerNull>(Op1)) 863 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext())); 864 865 // We have two options: compare with register or immediate. If the RHS of 866 // the compare is an immediate that we can fold into this compare, use 867 // CMPri, otherwise use CMPrr. 868 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) { 869 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) { 870 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareImmOpc)) 871 .addReg(Op0Reg) 872 .addImm(Op1C->getSExtValue()); 873 return true; 874 } 875 } 876 877 unsigned CompareOpc = X86ChooseCmpOpcode(VT, Subtarget); 878 if (CompareOpc == 0) return false; 879 880 unsigned Op1Reg = getRegForValue(Op1); 881 if (Op1Reg == 0) return false; 882 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareOpc)) 883 .addReg(Op0Reg) 884 .addReg(Op1Reg); 885 886 return true; 887 } 888 889 bool X86FastISel::X86SelectCmp(const Instruction *I) { 890 const CmpInst *CI = cast<CmpInst>(I); 891 892 MVT VT; 893 if (!isTypeLegal(I->getOperand(0)->getType(), VT)) 894 return false; 895 896 unsigned ResultReg = createResultReg(&X86::GR8RegClass); 897 unsigned SetCCOpc; 898 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 899 switch (CI->getPredicate()) { 900 case CmpInst::FCMP_OEQ: { 901 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 902 return false; 903 904 unsigned EReg = createResultReg(&X86::GR8RegClass); 905 unsigned NPReg = createResultReg(&X86::GR8RegClass); 906 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg); 907 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 908 TII.get(X86::SETNPr), NPReg); 909 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 910 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg); 911 UpdateValueMap(I, ResultReg); 912 return true; 913 } 914 case CmpInst::FCMP_UNE: { 915 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 916 return false; 917 918 unsigned NEReg = createResultReg(&X86::GR8RegClass); 919 unsigned PReg = createResultReg(&X86::GR8RegClass); 920 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETNEr), NEReg); 921 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETPr), PReg); 922 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::OR8rr),ResultReg) 923 .addReg(PReg).addReg(NEReg); 924 UpdateValueMap(I, ResultReg); 925 return true; 926 } 927 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 928 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 929 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break; 930 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break; 931 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 932 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break; 933 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break; 934 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 935 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break; 936 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break; 937 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 938 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 939 940 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 941 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 942 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 943 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 944 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 945 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 946 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break; 947 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break; 948 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break; 949 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break; 950 default: 951 return false; 952 } 953 954 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 955 if (SwapArgs) 956 std::swap(Op0, Op1); 957 958 // Emit a compare of Op0/Op1. 959 if (!X86FastEmitCompare(Op0, Op1, VT)) 960 return false; 961 962 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(SetCCOpc), ResultReg); 963 UpdateValueMap(I, ResultReg); 964 return true; 965 } 966 967 bool X86FastISel::X86SelectZExt(const Instruction *I) { 968 // Handle zero-extension from i1 to i8, which is common. 969 if (!I->getOperand(0)->getType()->isIntegerTy(1)) 970 return false; 971 972 EVT DstVT = TLI.getValueType(I->getType()); 973 if (!TLI.isTypeLegal(DstVT)) 974 return false; 975 976 unsigned ResultReg = getRegForValue(I->getOperand(0)); 977 if (ResultReg == 0) 978 return false; 979 980 // Set the high bits to zero. 981 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false); 982 if (ResultReg == 0) 983 return false; 984 985 if (DstVT != MVT::i8) { 986 ResultReg = FastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, 987 ResultReg, /*Kill=*/true); 988 if (ResultReg == 0) 989 return false; 990 } 991 992 UpdateValueMap(I, ResultReg); 993 return true; 994 } 995 996 997 bool X86FastISel::X86SelectBranch(const Instruction *I) { 998 // Unconditional branches are selected by tablegen-generated code. 999 // Handle a conditional branch. 1000 const BranchInst *BI = cast<BranchInst>(I); 1001 MachineBasicBlock *TrueMBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; 1002 MachineBasicBlock *FalseMBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; 1003 1004 // Fold the common case of a conditional branch with a comparison 1005 // in the same block (values defined on other blocks may not have 1006 // initialized registers). 1007 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 1008 if (CI->hasOneUse() && CI->getParent() == I->getParent()) { 1009 EVT VT = TLI.getValueType(CI->getOperand(0)->getType()); 1010 1011 // Try to take advantage of fallthrough opportunities. 1012 CmpInst::Predicate Predicate = CI->getPredicate(); 1013 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) { 1014 std::swap(TrueMBB, FalseMBB); 1015 Predicate = CmpInst::getInversePredicate(Predicate); 1016 } 1017 1018 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 1019 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA" 1020 1021 switch (Predicate) { 1022 case CmpInst::FCMP_OEQ: 1023 std::swap(TrueMBB, FalseMBB); 1024 Predicate = CmpInst::FCMP_UNE; 1025 // FALL THROUGH 1026 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 1027 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break; 1028 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break; 1029 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break; 1030 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break; 1031 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 1032 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break; 1033 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break; 1034 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break; 1035 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break; 1036 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break; 1037 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break; 1038 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break; 1039 1040 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break; 1041 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 1042 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break; 1043 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break; 1044 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break; 1045 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break; 1046 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break; 1047 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break; 1048 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break; 1049 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break; 1050 default: 1051 return false; 1052 } 1053 1054 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 1055 if (SwapArgs) 1056 std::swap(Op0, Op1); 1057 1058 // Emit a compare of the LHS and RHS, setting the flags. 1059 if (!X86FastEmitCompare(Op0, Op1, VT)) 1060 return false; 1061 1062 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BranchOpc)) 1063 .addMBB(TrueMBB); 1064 1065 if (Predicate == CmpInst::FCMP_UNE) { 1066 // X86 requires a second branch to handle UNE (and OEQ, 1067 // which is mapped to UNE above). 1068 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4)) 1069 .addMBB(TrueMBB); 1070 } 1071 1072 FastEmitBranch(FalseMBB, DL); 1073 FuncInfo.MBB->addSuccessor(TrueMBB); 1074 return true; 1075 } 1076 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) { 1077 // Handle things like "%cond = trunc i32 %X to i1 / br i1 %cond", which 1078 // typically happen for _Bool and C++ bools. 1079 MVT SourceVT; 1080 if (TI->hasOneUse() && TI->getParent() == I->getParent() && 1081 isTypeLegal(TI->getOperand(0)->getType(), SourceVT)) { 1082 unsigned TestOpc = 0; 1083 switch (SourceVT.SimpleTy) { 1084 default: break; 1085 case MVT::i8: TestOpc = X86::TEST8ri; break; 1086 case MVT::i16: TestOpc = X86::TEST16ri; break; 1087 case MVT::i32: TestOpc = X86::TEST32ri; break; 1088 case MVT::i64: TestOpc = X86::TEST64ri32; break; 1089 } 1090 if (TestOpc) { 1091 unsigned OpReg = getRegForValue(TI->getOperand(0)); 1092 if (OpReg == 0) return false; 1093 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TestOpc)) 1094 .addReg(OpReg).addImm(1); 1095 1096 unsigned JmpOpc = X86::JNE_4; 1097 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) { 1098 std::swap(TrueMBB, FalseMBB); 1099 JmpOpc = X86::JE_4; 1100 } 1101 1102 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(JmpOpc)) 1103 .addMBB(TrueMBB); 1104 FastEmitBranch(FalseMBB, DL); 1105 FuncInfo.MBB->addSuccessor(TrueMBB); 1106 return true; 1107 } 1108 } 1109 } 1110 1111 // Otherwise do a clumsy setcc and re-test it. 1112 // Note that i1 essentially gets ANY_EXTEND'ed to i8 where it isn't used 1113 // in an explicit cast, so make sure to handle that correctly. 1114 unsigned OpReg = getRegForValue(BI->getCondition()); 1115 if (OpReg == 0) return false; 1116 1117 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri)) 1118 .addReg(OpReg).addImm(1); 1119 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4)) 1120 .addMBB(TrueMBB); 1121 FastEmitBranch(FalseMBB, DL); 1122 FuncInfo.MBB->addSuccessor(TrueMBB); 1123 return true; 1124 } 1125 1126 bool X86FastISel::X86SelectShift(const Instruction *I) { 1127 unsigned CReg = 0, OpReg = 0; 1128 const TargetRegisterClass *RC = NULL; 1129 if (I->getType()->isIntegerTy(8)) { 1130 CReg = X86::CL; 1131 RC = &X86::GR8RegClass; 1132 switch (I->getOpcode()) { 1133 case Instruction::LShr: OpReg = X86::SHR8rCL; break; 1134 case Instruction::AShr: OpReg = X86::SAR8rCL; break; 1135 case Instruction::Shl: OpReg = X86::SHL8rCL; break; 1136 default: return false; 1137 } 1138 } else if (I->getType()->isIntegerTy(16)) { 1139 CReg = X86::CX; 1140 RC = &X86::GR16RegClass; 1141 switch (I->getOpcode()) { 1142 case Instruction::LShr: OpReg = X86::SHR16rCL; break; 1143 case Instruction::AShr: OpReg = X86::SAR16rCL; break; 1144 case Instruction::Shl: OpReg = X86::SHL16rCL; break; 1145 default: return false; 1146 } 1147 } else if (I->getType()->isIntegerTy(32)) { 1148 CReg = X86::ECX; 1149 RC = &X86::GR32RegClass; 1150 switch (I->getOpcode()) { 1151 case Instruction::LShr: OpReg = X86::SHR32rCL; break; 1152 case Instruction::AShr: OpReg = X86::SAR32rCL; break; 1153 case Instruction::Shl: OpReg = X86::SHL32rCL; break; 1154 default: return false; 1155 } 1156 } else if (I->getType()->isIntegerTy(64)) { 1157 CReg = X86::RCX; 1158 RC = &X86::GR64RegClass; 1159 switch (I->getOpcode()) { 1160 case Instruction::LShr: OpReg = X86::SHR64rCL; break; 1161 case Instruction::AShr: OpReg = X86::SAR64rCL; break; 1162 case Instruction::Shl: OpReg = X86::SHL64rCL; break; 1163 default: return false; 1164 } 1165 } else { 1166 return false; 1167 } 1168 1169 MVT VT; 1170 if (!isTypeLegal(I->getType(), VT)) 1171 return false; 1172 1173 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 1174 if (Op0Reg == 0) return false; 1175 1176 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1177 if (Op1Reg == 0) return false; 1178 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1179 CReg).addReg(Op1Reg); 1180 1181 // The shift instruction uses X86::CL. If we defined a super-register 1182 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here. 1183 if (CReg != X86::CL) 1184 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1185 TII.get(TargetOpcode::KILL), X86::CL) 1186 .addReg(CReg, RegState::Kill); 1187 1188 unsigned ResultReg = createResultReg(RC); 1189 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpReg), ResultReg) 1190 .addReg(Op0Reg); 1191 UpdateValueMap(I, ResultReg); 1192 return true; 1193 } 1194 1195 bool X86FastISel::X86SelectSelect(const Instruction *I) { 1196 MVT VT; 1197 if (!isTypeLegal(I->getType(), VT)) 1198 return false; 1199 1200 // We only use cmov here, if we don't have a cmov instruction bail. 1201 if (!Subtarget->hasCMov()) return false; 1202 1203 unsigned Opc = 0; 1204 const TargetRegisterClass *RC = NULL; 1205 if (VT == MVT::i16) { 1206 Opc = X86::CMOVE16rr; 1207 RC = &X86::GR16RegClass; 1208 } else if (VT == MVT::i32) { 1209 Opc = X86::CMOVE32rr; 1210 RC = &X86::GR32RegClass; 1211 } else if (VT == MVT::i64) { 1212 Opc = X86::CMOVE64rr; 1213 RC = &X86::GR64RegClass; 1214 } else { 1215 return false; 1216 } 1217 1218 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 1219 if (Op0Reg == 0) return false; 1220 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1221 if (Op1Reg == 0) return false; 1222 unsigned Op2Reg = getRegForValue(I->getOperand(2)); 1223 if (Op2Reg == 0) return false; 1224 1225 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr)) 1226 .addReg(Op0Reg).addReg(Op0Reg); 1227 unsigned ResultReg = createResultReg(RC); 1228 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) 1229 .addReg(Op1Reg).addReg(Op2Reg); 1230 UpdateValueMap(I, ResultReg); 1231 return true; 1232 } 1233 1234 bool X86FastISel::X86SelectFPExt(const Instruction *I) { 1235 // fpext from float to double. 1236 if (X86ScalarSSEf64 && 1237 I->getType()->isDoubleTy()) { 1238 const Value *V = I->getOperand(0); 1239 if (V->getType()->isFloatTy()) { 1240 unsigned OpReg = getRegForValue(V); 1241 if (OpReg == 0) return false; 1242 unsigned ResultReg = createResultReg(X86::FR64RegisterClass); 1243 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1244 TII.get(X86::CVTSS2SDrr), ResultReg) 1245 .addReg(OpReg); 1246 UpdateValueMap(I, ResultReg); 1247 return true; 1248 } 1249 } 1250 1251 return false; 1252 } 1253 1254 bool X86FastISel::X86SelectFPTrunc(const Instruction *I) { 1255 if (X86ScalarSSEf64) { 1256 if (I->getType()->isFloatTy()) { 1257 const Value *V = I->getOperand(0); 1258 if (V->getType()->isDoubleTy()) { 1259 unsigned OpReg = getRegForValue(V); 1260 if (OpReg == 0) return false; 1261 unsigned ResultReg = createResultReg(X86::FR32RegisterClass); 1262 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1263 TII.get(X86::CVTSD2SSrr), ResultReg) 1264 .addReg(OpReg); 1265 UpdateValueMap(I, ResultReg); 1266 return true; 1267 } 1268 } 1269 } 1270 1271 return false; 1272 } 1273 1274 bool X86FastISel::X86SelectTrunc(const Instruction *I) { 1275 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1276 EVT DstVT = TLI.getValueType(I->getType()); 1277 1278 // This code only handles truncation to byte. 1279 if (DstVT != MVT::i8 && DstVT != MVT::i1) 1280 return false; 1281 if (!TLI.isTypeLegal(SrcVT)) 1282 return false; 1283 1284 unsigned InputReg = getRegForValue(I->getOperand(0)); 1285 if (!InputReg) 1286 // Unhandled operand. Halt "fast" selection and bail. 1287 return false; 1288 1289 if (SrcVT == MVT::i8) { 1290 // Truncate from i8 to i1; no code needed. 1291 UpdateValueMap(I, InputReg); 1292 return true; 1293 } 1294 1295 if (!Subtarget->is64Bit()) { 1296 // If we're on x86-32; we can't extract an i8 from a general register. 1297 // First issue a copy to GR16_ABCD or GR32_ABCD. 1298 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) 1299 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass; 1300 unsigned CopyReg = createResultReg(CopyRC); 1301 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1302 CopyReg).addReg(InputReg); 1303 InputReg = CopyReg; 1304 } 1305 1306 // Issue an extract_subreg. 1307 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8, 1308 InputReg, /*Kill=*/true, 1309 X86::sub_8bit); 1310 if (!ResultReg) 1311 return false; 1312 1313 UpdateValueMap(I, ResultReg); 1314 return true; 1315 } 1316 1317 bool X86FastISel::IsMemcpySmall(uint64_t Len) { 1318 return Len <= (Subtarget->is64Bit() ? 32 : 16); 1319 } 1320 1321 bool X86FastISel::TryEmitSmallMemcpy(X86AddressMode DestAM, 1322 X86AddressMode SrcAM, uint64_t Len) { 1323 1324 // Make sure we don't bloat code by inlining very large memcpy's. 1325 if (!IsMemcpySmall(Len)) 1326 return false; 1327 1328 bool i64Legal = Subtarget->is64Bit(); 1329 1330 // We don't care about alignment here since we just emit integer accesses. 1331 while (Len) { 1332 MVT VT; 1333 if (Len >= 8 && i64Legal) 1334 VT = MVT::i64; 1335 else if (Len >= 4) 1336 VT = MVT::i32; 1337 else if (Len >= 2) 1338 VT = MVT::i16; 1339 else { 1340 assert(Len == 1); 1341 VT = MVT::i8; 1342 } 1343 1344 unsigned Reg; 1345 bool RV = X86FastEmitLoad(VT, SrcAM, Reg); 1346 RV &= X86FastEmitStore(VT, Reg, DestAM); 1347 assert(RV && "Failed to emit load or store??"); 1348 1349 unsigned Size = VT.getSizeInBits()/8; 1350 Len -= Size; 1351 DestAM.Disp += Size; 1352 SrcAM.Disp += Size; 1353 } 1354 1355 return true; 1356 } 1357 1358 bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) { 1359 // FIXME: Handle more intrinsics. 1360 switch (I.getIntrinsicID()) { 1361 default: return false; 1362 case Intrinsic::memcpy: { 1363 const MemCpyInst &MCI = cast<MemCpyInst>(I); 1364 // Don't handle volatile or variable length memcpys. 1365 if (MCI.isVolatile()) 1366 return false; 1367 1368 if (isa<ConstantInt>(MCI.getLength())) { 1369 // Small memcpy's are common enough that we want to do them 1370 // without a call if possible. 1371 uint64_t Len = cast<ConstantInt>(MCI.getLength())->getZExtValue(); 1372 if (IsMemcpySmall(Len)) { 1373 X86AddressMode DestAM, SrcAM; 1374 if (!X86SelectAddress(MCI.getRawDest(), DestAM) || 1375 !X86SelectAddress(MCI.getRawSource(), SrcAM)) 1376 return false; 1377 TryEmitSmallMemcpy(DestAM, SrcAM, Len); 1378 return true; 1379 } 1380 } 1381 1382 unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32; 1383 if (!MCI.getLength()->getType()->isIntegerTy(SizeWidth)) 1384 return false; 1385 1386 if (MCI.getSourceAddressSpace() > 255 || MCI.getDestAddressSpace() > 255) 1387 return false; 1388 1389 return DoSelectCall(&I, "memcpy"); 1390 } 1391 case Intrinsic::memset: { 1392 const MemSetInst &MSI = cast<MemSetInst>(I); 1393 1394 if (MSI.isVolatile()) 1395 return false; 1396 1397 unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32; 1398 if (!MSI.getLength()->getType()->isIntegerTy(SizeWidth)) 1399 return false; 1400 1401 if (MSI.getDestAddressSpace() > 255) 1402 return false; 1403 1404 return DoSelectCall(&I, "memset"); 1405 } 1406 case Intrinsic::stackprotector: { 1407 // Emit code inline code to store the stack guard onto the stack. 1408 EVT PtrTy = TLI.getPointerTy(); 1409 1410 const Value *Op1 = I.getArgOperand(0); // The guard's value. 1411 const AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 1412 1413 // Grab the frame index. 1414 X86AddressMode AM; 1415 if (!X86SelectAddress(Slot, AM)) return false; 1416 if (!X86FastEmitStore(PtrTy, Op1, AM)) return false; 1417 return true; 1418 } 1419 case Intrinsic::dbg_declare: { 1420 const DbgDeclareInst *DI = cast<DbgDeclareInst>(&I); 1421 X86AddressMode AM; 1422 assert(DI->getAddress() && "Null address should be checked earlier!"); 1423 if (!X86SelectAddress(DI->getAddress(), AM)) 1424 return false; 1425 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 1426 // FIXME may need to add RegState::Debug to any registers produced, 1427 // although ESP/EBP should be the only ones at the moment. 1428 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II), AM). 1429 addImm(0).addMetadata(DI->getVariable()); 1430 return true; 1431 } 1432 case Intrinsic::trap: { 1433 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP)); 1434 return true; 1435 } 1436 case Intrinsic::sadd_with_overflow: 1437 case Intrinsic::uadd_with_overflow: { 1438 // FIXME: Should fold immediates. 1439 1440 // Replace "add with overflow" intrinsics with an "add" instruction followed 1441 // by a seto/setc instruction. 1442 const Function *Callee = I.getCalledFunction(); 1443 Type *RetTy = 1444 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0)); 1445 1446 MVT VT; 1447 if (!isTypeLegal(RetTy, VT)) 1448 return false; 1449 1450 const Value *Op1 = I.getArgOperand(0); 1451 const Value *Op2 = I.getArgOperand(1); 1452 unsigned Reg1 = getRegForValue(Op1); 1453 unsigned Reg2 = getRegForValue(Op2); 1454 1455 if (Reg1 == 0 || Reg2 == 0) 1456 // FIXME: Handle values *not* in registers. 1457 return false; 1458 1459 unsigned OpC = 0; 1460 if (VT == MVT::i32) 1461 OpC = X86::ADD32rr; 1462 else if (VT == MVT::i64) 1463 OpC = X86::ADD64rr; 1464 else 1465 return false; 1466 1467 // The call to CreateRegs builds two sequential registers, to store the 1468 // both the the returned values. 1469 unsigned ResultReg = FuncInfo.CreateRegs(I.getType()); 1470 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg) 1471 .addReg(Reg1).addReg(Reg2); 1472 1473 unsigned Opc = X86::SETBr; 1474 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow) 1475 Opc = X86::SETOr; 1476 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg+1); 1477 1478 UpdateValueMap(&I, ResultReg, 2); 1479 return true; 1480 } 1481 } 1482 } 1483 1484 bool X86FastISel::X86SelectCall(const Instruction *I) { 1485 const CallInst *CI = cast<CallInst>(I); 1486 const Value *Callee = CI->getCalledValue(); 1487 1488 // Can't handle inline asm yet. 1489 if (isa<InlineAsm>(Callee)) 1490 return false; 1491 1492 // Handle intrinsic calls. 1493 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI)) 1494 return X86VisitIntrinsicCall(*II); 1495 1496 return DoSelectCall(I, 0); 1497 } 1498 1499 // Select either a call, or an llvm.memcpy/memmove/memset intrinsic 1500 bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) { 1501 const CallInst *CI = cast<CallInst>(I); 1502 const Value *Callee = CI->getCalledValue(); 1503 1504 // Handle only C and fastcc calling conventions for now. 1505 ImmutableCallSite CS(CI); 1506 CallingConv::ID CC = CS.getCallingConv(); 1507 if (CC != CallingConv::C && CC != CallingConv::Fast && 1508 CC != CallingConv::X86_FastCall) 1509 return false; 1510 1511 // fastcc with -tailcallopt is intended to provide a guaranteed 1512 // tail call optimization. Fastisel doesn't know how to do that. 1513 if (CC == CallingConv::Fast && GuaranteedTailCallOpt) 1514 return false; 1515 1516 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 1517 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1518 bool isVarArg = FTy->isVarArg(); 1519 1520 // Don't know how to handle Win64 varargs yet. Nothing special needed for 1521 // x86-32. Special handling for x86-64 is implemented. 1522 if (isVarArg && Subtarget->isTargetWin64()) 1523 return false; 1524 1525 // Fast-isel doesn't know about callee-pop yet. 1526 if (X86::isCalleePop(CC, Subtarget->is64Bit(), isVarArg, 1527 GuaranteedTailCallOpt)) 1528 return false; 1529 1530 // Check whether the function can return without sret-demotion. 1531 SmallVector<ISD::OutputArg, 4> Outs; 1532 SmallVector<uint64_t, 4> Offsets; 1533 GetReturnInfo(I->getType(), CS.getAttributes().getRetAttributes(), 1534 Outs, TLI, &Offsets); 1535 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 1536 *FuncInfo.MF, FTy->isVarArg(), 1537 Outs, FTy->getContext()); 1538 if (!CanLowerReturn) 1539 return false; 1540 1541 // Materialize callee address in a register. FIXME: GV address can be 1542 // handled with a CALLpcrel32 instead. 1543 X86AddressMode CalleeAM; 1544 if (!X86SelectCallAddress(Callee, CalleeAM)) 1545 return false; 1546 unsigned CalleeOp = 0; 1547 const GlobalValue *GV = 0; 1548 if (CalleeAM.GV != 0) { 1549 GV = CalleeAM.GV; 1550 } else if (CalleeAM.Base.Reg != 0) { 1551 CalleeOp = CalleeAM.Base.Reg; 1552 } else 1553 return false; 1554 1555 // Deal with call operands first. 1556 SmallVector<const Value *, 8> ArgVals; 1557 SmallVector<unsigned, 8> Args; 1558 SmallVector<MVT, 8> ArgVTs; 1559 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1560 Args.reserve(CS.arg_size()); 1561 ArgVals.reserve(CS.arg_size()); 1562 ArgVTs.reserve(CS.arg_size()); 1563 ArgFlags.reserve(CS.arg_size()); 1564 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 1565 i != e; ++i) { 1566 // If we're lowering a mem intrinsic instead of a regular call, skip the 1567 // last two arguments, which should not passed to the underlying functions. 1568 if (MemIntName && e-i <= 2) 1569 break; 1570 Value *ArgVal = *i; 1571 ISD::ArgFlagsTy Flags; 1572 unsigned AttrInd = i - CS.arg_begin() + 1; 1573 if (CS.paramHasAttr(AttrInd, Attribute::SExt)) 1574 Flags.setSExt(); 1575 if (CS.paramHasAttr(AttrInd, Attribute::ZExt)) 1576 Flags.setZExt(); 1577 1578 if (CS.paramHasAttr(AttrInd, Attribute::ByVal)) { 1579 PointerType *Ty = cast<PointerType>(ArgVal->getType()); 1580 Type *ElementTy = Ty->getElementType(); 1581 unsigned FrameSize = TD.getTypeAllocSize(ElementTy); 1582 unsigned FrameAlign = CS.getParamAlignment(AttrInd); 1583 if (!FrameAlign) 1584 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 1585 Flags.setByVal(); 1586 Flags.setByValSize(FrameSize); 1587 Flags.setByValAlign(FrameAlign); 1588 if (!IsMemcpySmall(FrameSize)) 1589 return false; 1590 } 1591 1592 if (CS.paramHasAttr(AttrInd, Attribute::InReg)) 1593 Flags.setInReg(); 1594 if (CS.paramHasAttr(AttrInd, Attribute::Nest)) 1595 Flags.setNest(); 1596 1597 // If this is an i1/i8/i16 argument, promote to i32 to avoid an extra 1598 // instruction. This is safe because it is common to all fastisel supported 1599 // calling conventions on x86. 1600 if (ConstantInt *CI = dyn_cast<ConstantInt>(ArgVal)) { 1601 if (CI->getBitWidth() == 1 || CI->getBitWidth() == 8 || 1602 CI->getBitWidth() == 16) { 1603 if (Flags.isSExt()) 1604 ArgVal = ConstantExpr::getSExt(CI,Type::getInt32Ty(CI->getContext())); 1605 else 1606 ArgVal = ConstantExpr::getZExt(CI,Type::getInt32Ty(CI->getContext())); 1607 } 1608 } 1609 1610 unsigned ArgReg; 1611 1612 // Passing bools around ends up doing a trunc to i1 and passing it. 1613 // Codegen this as an argument + "and 1". 1614 if (ArgVal->getType()->isIntegerTy(1) && isa<TruncInst>(ArgVal) && 1615 cast<TruncInst>(ArgVal)->getParent() == I->getParent() && 1616 ArgVal->hasOneUse()) { 1617 ArgVal = cast<TruncInst>(ArgVal)->getOperand(0); 1618 ArgReg = getRegForValue(ArgVal); 1619 if (ArgReg == 0) return false; 1620 1621 MVT ArgVT; 1622 if (!isTypeLegal(ArgVal->getType(), ArgVT)) return false; 1623 1624 ArgReg = FastEmit_ri(ArgVT, ArgVT, ISD::AND, ArgReg, 1625 ArgVal->hasOneUse(), 1); 1626 } else { 1627 ArgReg = getRegForValue(ArgVal); 1628 } 1629 1630 if (ArgReg == 0) return false; 1631 1632 Type *ArgTy = ArgVal->getType(); 1633 MVT ArgVT; 1634 if (!isTypeLegal(ArgTy, ArgVT)) 1635 return false; 1636 if (ArgVT == MVT::x86mmx) 1637 return false; 1638 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 1639 Flags.setOrigAlign(OriginalAlignment); 1640 1641 Args.push_back(ArgReg); 1642 ArgVals.push_back(ArgVal); 1643 ArgVTs.push_back(ArgVT); 1644 ArgFlags.push_back(Flags); 1645 } 1646 1647 // Analyze operands of the call, assigning locations to each operand. 1648 SmallVector<CCValAssign, 16> ArgLocs; 1649 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, 1650 I->getParent()->getContext()); 1651 1652 // Allocate shadow area for Win64 1653 if (Subtarget->isTargetWin64()) 1654 CCInfo.AllocateStack(32, 8); 1655 1656 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_X86); 1657 1658 // Get a count of how many bytes are to be pushed on the stack. 1659 unsigned NumBytes = CCInfo.getNextStackOffset(); 1660 1661 // Issue CALLSEQ_START 1662 unsigned AdjStackDown = TII.getCallFrameSetupOpcode(); 1663 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown)) 1664 .addImm(NumBytes); 1665 1666 // Process argument: walk the register/memloc assignments, inserting 1667 // copies / loads. 1668 SmallVector<unsigned, 4> RegArgs; 1669 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1670 CCValAssign &VA = ArgLocs[i]; 1671 unsigned Arg = Args[VA.getValNo()]; 1672 EVT ArgVT = ArgVTs[VA.getValNo()]; 1673 1674 // Promote the value if needed. 1675 switch (VA.getLocInfo()) { 1676 default: llvm_unreachable("Unknown loc info!"); 1677 case CCValAssign::Full: break; 1678 case CCValAssign::SExt: { 1679 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && 1680 "Unexpected extend"); 1681 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1682 Arg, ArgVT, Arg); 1683 assert(Emitted && "Failed to emit a sext!"); (void)Emitted; 1684 ArgVT = VA.getLocVT(); 1685 break; 1686 } 1687 case CCValAssign::ZExt: { 1688 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && 1689 "Unexpected extend"); 1690 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1691 Arg, ArgVT, Arg); 1692 assert(Emitted && "Failed to emit a zext!"); (void)Emitted; 1693 ArgVT = VA.getLocVT(); 1694 break; 1695 } 1696 case CCValAssign::AExt: { 1697 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && 1698 "Unexpected extend"); 1699 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), 1700 Arg, ArgVT, Arg); 1701 if (!Emitted) 1702 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1703 Arg, ArgVT, Arg); 1704 if (!Emitted) 1705 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1706 Arg, ArgVT, Arg); 1707 1708 assert(Emitted && "Failed to emit a aext!"); (void)Emitted; 1709 ArgVT = VA.getLocVT(); 1710 break; 1711 } 1712 case CCValAssign::BCvt: { 1713 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT(), 1714 ISD::BITCAST, Arg, /*TODO: Kill=*/false); 1715 assert(BC != 0 && "Failed to emit a bitcast!"); 1716 Arg = BC; 1717 ArgVT = VA.getLocVT(); 1718 break; 1719 } 1720 } 1721 1722 if (VA.isRegLoc()) { 1723 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1724 VA.getLocReg()).addReg(Arg); 1725 RegArgs.push_back(VA.getLocReg()); 1726 } else { 1727 unsigned LocMemOffset = VA.getLocMemOffset(); 1728 X86AddressMode AM; 1729 AM.Base.Reg = StackPtr; 1730 AM.Disp = LocMemOffset; 1731 const Value *ArgVal = ArgVals[VA.getValNo()]; 1732 ISD::ArgFlagsTy Flags = ArgFlags[VA.getValNo()]; 1733 1734 if (Flags.isByVal()) { 1735 X86AddressMode SrcAM; 1736 SrcAM.Base.Reg = Arg; 1737 bool Res = TryEmitSmallMemcpy(AM, SrcAM, Flags.getByValSize()); 1738 assert(Res && "memcpy length already checked!"); (void)Res; 1739 } else if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) { 1740 // If this is a really simple value, emit this with the Value* version 1741 // of X86FastEmitStore. If it isn't simple, we don't want to do this, 1742 // as it can cause us to reevaluate the argument. 1743 X86FastEmitStore(ArgVT, ArgVal, AM); 1744 } else { 1745 X86FastEmitStore(ArgVT, Arg, AM); 1746 } 1747 } 1748 } 1749 1750 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1751 // GOT pointer. 1752 if (Subtarget->isPICStyleGOT()) { 1753 unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF); 1754 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1755 X86::EBX).addReg(Base); 1756 } 1757 1758 if (Subtarget->is64Bit() && isVarArg && !Subtarget->isTargetWin64()) { 1759 // Count the number of XMM registers allocated. 1760 static const unsigned XMMArgRegs[] = { 1761 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1762 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1763 }; 1764 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1765 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::MOV8ri), 1766 X86::AL).addImm(NumXMMRegs); 1767 } 1768 1769 // Issue the call. 1770 MachineInstrBuilder MIB; 1771 if (CalleeOp) { 1772 // Register-indirect call. 1773 unsigned CallOpc; 1774 if (Subtarget->isTargetWin64()) 1775 CallOpc = X86::WINCALL64r; 1776 else if (Subtarget->is64Bit()) 1777 CallOpc = X86::CALL64r; 1778 else 1779 CallOpc = X86::CALL32r; 1780 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc)) 1781 .addReg(CalleeOp); 1782 1783 } else { 1784 // Direct call. 1785 assert(GV && "Not a direct call"); 1786 unsigned CallOpc; 1787 if (Subtarget->isTargetWin64()) 1788 CallOpc = X86::WINCALL64pcrel32; 1789 else if (Subtarget->is64Bit()) 1790 CallOpc = X86::CALL64pcrel32; 1791 else 1792 CallOpc = X86::CALLpcrel32; 1793 1794 // See if we need any target-specific flags on the GV operand. 1795 unsigned char OpFlags = 0; 1796 1797 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 1798 // external symbols most go through the PLT in PIC mode. If the symbol 1799 // has hidden or protected visibility, or if it is static or local, then 1800 // we don't need to use the PLT - we can directly call it. 1801 if (Subtarget->isTargetELF() && 1802 TM.getRelocationModel() == Reloc::PIC_ && 1803 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 1804 OpFlags = X86II::MO_PLT; 1805 } else if (Subtarget->isPICStyleStubAny() && 1806 (GV->isDeclaration() || GV->isWeakForLinker()) && 1807 (!Subtarget->getTargetTriple().isMacOSX() || 1808 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 1809 // PC-relative references to external symbols should go through $stub, 1810 // unless we're building with the leopard linker or later, which 1811 // automatically synthesizes these stubs. 1812 OpFlags = X86II::MO_DARWIN_STUB; 1813 } 1814 1815 1816 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc)); 1817 if (MemIntName) 1818 MIB.addExternalSymbol(MemIntName, OpFlags); 1819 else 1820 MIB.addGlobalAddress(GV, 0, OpFlags); 1821 } 1822 1823 // Add an implicit use GOT pointer in EBX. 1824 if (Subtarget->isPICStyleGOT()) 1825 MIB.addReg(X86::EBX); 1826 1827 if (Subtarget->is64Bit() && isVarArg && !Subtarget->isTargetWin64()) 1828 MIB.addReg(X86::AL); 1829 1830 // Add implicit physical register uses to the call. 1831 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 1832 MIB.addReg(RegArgs[i]); 1833 1834 // Issue CALLSEQ_END 1835 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode(); 1836 unsigned NumBytesCallee = 0; 1837 if (!Subtarget->is64Bit() && CS.paramHasAttr(1, Attribute::StructRet)) 1838 NumBytesCallee = 4; 1839 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp)) 1840 .addImm(NumBytes).addImm(NumBytesCallee); 1841 1842 // Build info for return calling conv lowering code. 1843 // FIXME: This is practically a copy-paste from TargetLowering::LowerCallTo. 1844 SmallVector<ISD::InputArg, 32> Ins; 1845 SmallVector<EVT, 4> RetTys; 1846 ComputeValueVTs(TLI, I->getType(), RetTys); 1847 for (unsigned i = 0, e = RetTys.size(); i != e; ++i) { 1848 EVT VT = RetTys[i]; 1849 EVT RegisterVT = TLI.getRegisterType(I->getParent()->getContext(), VT); 1850 unsigned NumRegs = TLI.getNumRegisters(I->getParent()->getContext(), VT); 1851 for (unsigned j = 0; j != NumRegs; ++j) { 1852 ISD::InputArg MyFlags; 1853 MyFlags.VT = RegisterVT.getSimpleVT(); 1854 MyFlags.Used = !CS.getInstruction()->use_empty(); 1855 if (CS.paramHasAttr(0, Attribute::SExt)) 1856 MyFlags.Flags.setSExt(); 1857 if (CS.paramHasAttr(0, Attribute::ZExt)) 1858 MyFlags.Flags.setZExt(); 1859 if (CS.paramHasAttr(0, Attribute::InReg)) 1860 MyFlags.Flags.setInReg(); 1861 Ins.push_back(MyFlags); 1862 } 1863 } 1864 1865 // Now handle call return values. 1866 SmallVector<unsigned, 4> UsedRegs; 1867 SmallVector<CCValAssign, 16> RVLocs; 1868 CCState CCRetInfo(CC, false, *FuncInfo.MF, TM, RVLocs, 1869 I->getParent()->getContext()); 1870 unsigned ResultReg = FuncInfo.CreateRegs(I->getType()); 1871 CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86); 1872 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1873 EVT CopyVT = RVLocs[i].getValVT(); 1874 unsigned CopyReg = ResultReg + i; 1875 1876 // If this is a call to a function that returns an fp value on the x87 fp 1877 // stack, but where we prefer to use the value in xmm registers, copy it 1878 // out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1879 if ((RVLocs[i].getLocReg() == X86::ST0 || 1880 RVLocs[i].getLocReg() == X86::ST1)) { 1881 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) { 1882 CopyVT = MVT::f80; 1883 CopyReg = createResultReg(X86::RFP80RegisterClass); 1884 } 1885 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::FpPOP_RETVAL), 1886 CopyReg); 1887 } else { 1888 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1889 CopyReg).addReg(RVLocs[i].getLocReg()); 1890 UsedRegs.push_back(RVLocs[i].getLocReg()); 1891 } 1892 1893 if (CopyVT != RVLocs[i].getValVT()) { 1894 // Round the F80 the right size, which also moves to the appropriate xmm 1895 // register. This is accomplished by storing the F80 value in memory and 1896 // then loading it back. Ewww... 1897 EVT ResVT = RVLocs[i].getValVT(); 1898 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; 1899 unsigned MemSize = ResVT.getSizeInBits()/8; 1900 int FI = MFI.CreateStackObject(MemSize, MemSize, false); 1901 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1902 TII.get(Opc)), FI) 1903 .addReg(CopyReg); 1904 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; 1905 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1906 TII.get(Opc), ResultReg + i), FI); 1907 } 1908 } 1909 1910 if (RVLocs.size()) 1911 UpdateValueMap(I, ResultReg, RVLocs.size()); 1912 1913 // Set all unused physreg defs as dead. 1914 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); 1915 1916 return true; 1917 } 1918 1919 1920 bool 1921 X86FastISel::TargetSelectInstruction(const Instruction *I) { 1922 switch (I->getOpcode()) { 1923 default: break; 1924 case Instruction::Load: 1925 return X86SelectLoad(I); 1926 case Instruction::Store: 1927 return X86SelectStore(I); 1928 case Instruction::Ret: 1929 return X86SelectRet(I); 1930 case Instruction::ICmp: 1931 case Instruction::FCmp: 1932 return X86SelectCmp(I); 1933 case Instruction::ZExt: 1934 return X86SelectZExt(I); 1935 case Instruction::Br: 1936 return X86SelectBranch(I); 1937 case Instruction::Call: 1938 return X86SelectCall(I); 1939 case Instruction::LShr: 1940 case Instruction::AShr: 1941 case Instruction::Shl: 1942 return X86SelectShift(I); 1943 case Instruction::Select: 1944 return X86SelectSelect(I); 1945 case Instruction::Trunc: 1946 return X86SelectTrunc(I); 1947 case Instruction::FPExt: 1948 return X86SelectFPExt(I); 1949 case Instruction::FPTrunc: 1950 return X86SelectFPTrunc(I); 1951 case Instruction::IntToPtr: // Deliberate fall-through. 1952 case Instruction::PtrToInt: { 1953 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1954 EVT DstVT = TLI.getValueType(I->getType()); 1955 if (DstVT.bitsGT(SrcVT)) 1956 return X86SelectZExt(I); 1957 if (DstVT.bitsLT(SrcVT)) 1958 return X86SelectTrunc(I); 1959 unsigned Reg = getRegForValue(I->getOperand(0)); 1960 if (Reg == 0) return false; 1961 UpdateValueMap(I, Reg); 1962 return true; 1963 } 1964 } 1965 1966 return false; 1967 } 1968 1969 unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) { 1970 MVT VT; 1971 if (!isTypeLegal(C->getType(), VT)) 1972 return false; 1973 1974 // Get opcode and regclass of the output for the given load instruction. 1975 unsigned Opc = 0; 1976 const TargetRegisterClass *RC = NULL; 1977 switch (VT.SimpleTy) { 1978 default: return false; 1979 case MVT::i8: 1980 Opc = X86::MOV8rm; 1981 RC = X86::GR8RegisterClass; 1982 break; 1983 case MVT::i16: 1984 Opc = X86::MOV16rm; 1985 RC = X86::GR16RegisterClass; 1986 break; 1987 case MVT::i32: 1988 Opc = X86::MOV32rm; 1989 RC = X86::GR32RegisterClass; 1990 break; 1991 case MVT::i64: 1992 // Must be in x86-64 mode. 1993 Opc = X86::MOV64rm; 1994 RC = X86::GR64RegisterClass; 1995 break; 1996 case MVT::f32: 1997 if (X86ScalarSSEf32) { 1998 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm; 1999 RC = X86::FR32RegisterClass; 2000 } else { 2001 Opc = X86::LD_Fp32m; 2002 RC = X86::RFP32RegisterClass; 2003 } 2004 break; 2005 case MVT::f64: 2006 if (X86ScalarSSEf64) { 2007 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm; 2008 RC = X86::FR64RegisterClass; 2009 } else { 2010 Opc = X86::LD_Fp64m; 2011 RC = X86::RFP64RegisterClass; 2012 } 2013 break; 2014 case MVT::f80: 2015 // No f80 support yet. 2016 return false; 2017 } 2018 2019 // Materialize addresses with LEA instructions. 2020 if (isa<GlobalValue>(C)) { 2021 X86AddressMode AM; 2022 if (X86SelectAddress(C, AM)) { 2023 // If the expression is just a basereg, then we're done, otherwise we need 2024 // to emit an LEA. 2025 if (AM.BaseType == X86AddressMode::RegBase && 2026 AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == 0) 2027 return AM.Base.Reg; 2028 2029 Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r; 2030 unsigned ResultReg = createResultReg(RC); 2031 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 2032 TII.get(Opc), ResultReg), AM); 2033 return ResultReg; 2034 } 2035 return 0; 2036 } 2037 2038 // MachineConstantPool wants an explicit alignment. 2039 unsigned Align = TD.getPrefTypeAlignment(C->getType()); 2040 if (Align == 0) { 2041 // Alignment of vector types. FIXME! 2042 Align = TD.getTypeAllocSize(C->getType()); 2043 } 2044 2045 // x86-32 PIC requires a PIC base register for constant pools. 2046 unsigned PICBase = 0; 2047 unsigned char OpFlag = 0; 2048 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic 2049 OpFlag = X86II::MO_PIC_BASE_OFFSET; 2050 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF); 2051 } else if (Subtarget->isPICStyleGOT()) { 2052 OpFlag = X86II::MO_GOTOFF; 2053 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF); 2054 } else if (Subtarget->isPICStyleRIPRel() && 2055 TM.getCodeModel() == CodeModel::Small) { 2056 PICBase = X86::RIP; 2057 } 2058 2059 // Create the load from the constant pool. 2060 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align); 2061 unsigned ResultReg = createResultReg(RC); 2062 addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 2063 TII.get(Opc), ResultReg), 2064 MCPOffset, PICBase, OpFlag); 2065 2066 return ResultReg; 2067 } 2068 2069 unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) { 2070 // Fail on dynamic allocas. At this point, getRegForValue has already 2071 // checked its CSE maps, so if we're here trying to handle a dynamic 2072 // alloca, we're not going to succeed. X86SelectAddress has a 2073 // check for dynamic allocas, because it's called directly from 2074 // various places, but TargetMaterializeAlloca also needs a check 2075 // in order to avoid recursion between getRegForValue, 2076 // X86SelectAddrss, and TargetMaterializeAlloca. 2077 if (!FuncInfo.StaticAllocaMap.count(C)) 2078 return 0; 2079 2080 X86AddressMode AM; 2081 if (!X86SelectAddress(C, AM)) 2082 return 0; 2083 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 2084 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); 2085 unsigned ResultReg = createResultReg(RC); 2086 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 2087 TII.get(Opc), ResultReg), AM); 2088 return ResultReg; 2089 } 2090 2091 unsigned X86FastISel::TargetMaterializeFloatZero(const ConstantFP *CF) { 2092 MVT VT; 2093 if (!isTypeLegal(CF->getType(), VT)) 2094 return false; 2095 2096 // Get opcode and regclass for the given zero. 2097 unsigned Opc = 0; 2098 const TargetRegisterClass *RC = NULL; 2099 switch (VT.SimpleTy) { 2100 default: return false; 2101 case MVT::f32: 2102 if (X86ScalarSSEf32) { 2103 Opc = X86::FsFLD0SS; 2104 RC = X86::FR32RegisterClass; 2105 } else { 2106 Opc = X86::LD_Fp032; 2107 RC = X86::RFP32RegisterClass; 2108 } 2109 break; 2110 case MVT::f64: 2111 if (X86ScalarSSEf64) { 2112 Opc = X86::FsFLD0SD; 2113 RC = X86::FR64RegisterClass; 2114 } else { 2115 Opc = X86::LD_Fp064; 2116 RC = X86::RFP64RegisterClass; 2117 } 2118 break; 2119 case MVT::f80: 2120 // No f80 support yet. 2121 return false; 2122 } 2123 2124 unsigned ResultReg = createResultReg(RC); 2125 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg); 2126 return ResultReg; 2127 } 2128 2129 2130 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that 2131 /// vreg is being provided by the specified load instruction. If possible, 2132 /// try to fold the load as an operand to the instruction, returning true if 2133 /// possible. 2134 bool X86FastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo, 2135 const LoadInst *LI) { 2136 X86AddressMode AM; 2137 if (!X86SelectAddress(LI->getOperand(0), AM)) 2138 return false; 2139 2140 X86InstrInfo &XII = (X86InstrInfo&)TII; 2141 2142 unsigned Size = TD.getTypeAllocSize(LI->getType()); 2143 unsigned Alignment = LI->getAlignment(); 2144 2145 SmallVector<MachineOperand, 8> AddrOps; 2146 AM.getFullAddress(AddrOps); 2147 2148 MachineInstr *Result = 2149 XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps, Size, Alignment); 2150 if (Result == 0) return false; 2151 2152 FuncInfo.MBB->insert(FuncInfo.InsertPt, Result); 2153 MI->eraseFromParent(); 2154 return true; 2155 } 2156 2157 2158 namespace llvm { 2159 llvm::FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo) { 2160 return new X86FastISel(funcInfo); 2161 } 2162 } 2163