| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 45 unsigned IndexReg;
49 SystemZAddressMode() : BaseType(RegBase), IndexReg(0), Disp(0) {
98 return MIB.addImm(AM.Disp).addReg(AM.IndexReg);
|
| SystemZISelDAGToDAG.cpp | 47 SDValue IndexReg;
52 : BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) {
68 errs() << "IndexReg ";
69 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
232 if (AM.IndexReg.getNode() || AM.isRI) {
249 AM.IndexReg = Neg;
281 !AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) {
283 AM.IndexReg = N.getNode()->getOperand(1);
322 if (AM.IndexReg.getNode() == 0 && !AM.isRI)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 111 const MCOperand &IndexReg = MI->getOperand(Op+2);
123 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
130 if (IndexReg.getReg() || BaseReg.getReg()) {
135 if (IndexReg.getReg()) {
|
| X86IntelInstPrinter.cpp | 99 const MCOperand &IndexReg = MI->getOperand(Op+2);
117 if (IndexReg.getReg()) {
132 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86InstrBuilder.h | 50 unsigned IndexReg;
56 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) {
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
|
| X86ISelDAGToDAG.cpp | 64 SDValue IndexReg;
76 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
86 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
113 << "IndexReg ";
114 if (IndexReg.getNode() != 0)
115 IndexReg.getNode()->dump();
237 Index = AM.IndexReg;
708 AM.Base_Reg = AM.IndexReg;
720 AM.IndexReg.getNode() == 0 &&
785 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1
[all...] |
| X86CodeEmitter.cpp | 469 const MachineOperand &IndexReg = MI.getOperand(Op+2);
476 assert(IndexReg.getReg() == 0 && Is64BitMode &&
497 IndexReg.getReg() == 0 &&
535 assert(IndexReg.getReg() != X86::ESP &&
536 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
569 if (IndexReg.getReg())
570 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
577 if (IndexReg.getReg())
578 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
[all...] |
| X86FastISel.cpp | 397 unsigned IndexReg = AM.IndexReg;
434 if (IndexReg == 0 &&
439 IndexReg = getRegForGEPIndex(Op).first;
440 if (IndexReg == 0)
453 AM.IndexReg = IndexReg;
492 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
511 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
573 if (AM.IndexReg == 0)
[all...] |
| X86AsmPrinter.cpp | 283 const MachineOperand &IndexReg = MI->getOperand(Op+2);
293 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
309 assert(IndexReg.getReg() != X86::ESP &&
316 if (IndexReg.getReg()) {
|
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 49 unsigned IndexReg;
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
104 AM.IndexReg = Op.getImm();
162 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
|
| X86AsmPrinter.cpp | 232 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
242 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
262 assert(IndexReg.getReg() != X86::ESP &&
269 if (IndexReg.getReg()) {
298 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
316 if (IndexReg.getReg()) {
329 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| X86ISelDAGToDAG.cpp | 62 SDValue IndexReg;
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
86 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
113 << "IndexReg ";
114 if (IndexReg.getNode())
115 IndexReg.getNode()->dump();
254 Index = AM.IndexReg;
847 AM.Base_Reg = AM.IndexReg;
859 AM.IndexReg.getNode() == nullptr &&
[all...] |
| X86FastISel.cpp | 253 /// IndexReg field of the addressing mode will be updated to match in this case.
258 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg,
722 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
741 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
803 if (AM.IndexReg == 0) {
805 AM.IndexReg = getRegForValue(V);
806 return AM.IndexReg != 0;
890 unsigned IndexReg = AM.IndexReg;
[all...] |
| X86MCInstLower.cpp | 780 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
781 Opc = IndexReg = Displacement = SegmentReg = 0;
791 IndexReg = X86::RAX; break;
793 IndexReg = X86::RAX; break;
796 IndexReg = X86::RAX; break;
798 IndexReg = X86::RAX; break;
800 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 198 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
212 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
219 if (IndexReg.getReg() || BaseReg.getReg()) {
224 if (IndexReg.getReg()) {
|
| X86IntelInstPrinter.cpp | 161 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
179 if (IndexReg.getReg()) {
193 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86Operand.h | 56 unsigned IndexReg;
121 return Mem.IndexReg;
238 return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR;
504 Res->Mem.IndexReg = 0;
517 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
522 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
531 Res->Mem.IndexReg = IndexReg;
|
| X86AsmParser.cpp | 264 unsigned BaseReg, IndexReg, TmpReg, Scale;
274 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
279 unsigned getIndexReg() { return IndexReg; }
382 // If we already have a BaseReg, then assume this is the IndexReg with
387 assert (!IndexReg && "BaseReg/IndexReg already set!");
388 IndexReg = TmpReg;
419 // If we already have a BaseReg, then assume this is the IndexReg with
424 assert (!IndexReg && "BaseReg/IndexReg already set!")
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 136 unsigned IndexReg;
185 return Mem.IndexReg;
345 Res->Mem.IndexReg = 0;
352 unsigned BaseReg, unsigned IndexReg,
356 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
365 Res->Mem.IndexReg = IndexReg;
380 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
389 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
525 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefi
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 163 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
167 (IndexReg.getReg() != 0 &&
168 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
249 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
255 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
286 IndexReg.getReg() == 0 &&
325 assert(IndexReg.getReg() != X86::ESP &&
326 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
362 if (IndexReg.getReg())
363 IndexRegNo = GetX86RegNum(IndexReg);
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
69 (IndexReg.getReg() != 0 &&
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
207 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
211 (IndexReg.getReg() != 0 &&
212 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
215 assert(IndexReg.getReg() == 0 && "Invalid eip-based address.");
226 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
230 (IndexReg.getReg() != 0 &&
231 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 163 unsigned &IndexReg);
433 unsigned &IndexReg) {
454 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
455 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
519 unsigned IndexReg = 0;
520 PPCSimplifyAddress(Addr, UseOffset, IndexReg);
583 .addReg(Addr.Base.Reg).addReg(IndexReg);
655 unsigned IndexReg = 0;
656 PPCSimplifyAddress(Addr, UseOffset, IndexReg);
722 if (IndexReg)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
