1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_S390_CONSTANTS_S390_H_ 6 #define V8_S390_CONSTANTS_S390_H_ 7 8 // Get the standard printf format macros for C99 stdint types. 9 #ifndef __STDC_FORMAT_MACROS 10 #define __STDC_FORMAT_MACROS 11 #endif 12 #include <inttypes.h> 13 14 #include <stdint.h> 15 16 #include "src/base/logging.h" 17 #include "src/base/macros.h" 18 #include "src/globals.h" 19 20 namespace v8 { 21 namespace internal { 22 23 // Number of registers 24 const int kNumRegisters = 16; 25 26 // FP support. 27 const int kNumDoubleRegisters = 16; 28 29 const int kNoRegister = -1; 30 31 // sign-extend the least significant 16-bits of value <imm> 32 #define SIGN_EXT_IMM16(imm) ((static_cast<int>(imm) << 16) >> 16) 33 34 // sign-extend the least significant 26-bits of value <imm> 35 #define SIGN_EXT_IMM26(imm) ((static_cast<int>(imm) << 6) >> 6) 36 37 // ----------------------------------------------------------------------------- 38 // Conditions. 39 40 // Defines constants and accessor classes to assemble, disassemble and 41 // simulate z/Architecture instructions. 42 // 43 // Section references in the code refer to the "z/Architecture Principles 44 // Of Operation" http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr009.pdf 45 // 46 47 // Constants for specific fields are defined in their respective named enums. 48 // General constants are in an anonymous enum in class Instr. 49 enum Condition { 50 kNoCondition = -1, 51 eq = 0x8, // Equal. 52 ne = 0x7, // Not equal. 53 ge = 0xa, // Greater or equal. 54 lt = 0x4, // Less than. 55 gt = 0x2, // Greater than. 56 le = 0xc, // Less then or equal 57 al = 0xf, // Always. 58 59 CC_NOP = 0x0, // S390 NOP 60 CC_EQ = 0x08, // S390 condition code 0b1000 61 CC_LT = 0x04, // S390 condition code 0b0100 62 CC_LE = CC_EQ | CC_LT, // S390 condition code 0b1100 63 CC_GT = 0x02, // S390 condition code 0b0010 64 CC_GE = CC_EQ | CC_GT, // S390 condition code 0b1010 65 CC_OF = 0x01, // S390 condition code 0b0001 66 CC_NOF = 0x0E, // S390 condition code 0b1110 67 CC_ALWAYS = 0x0F, // S390 always taken branch 68 unordered = CC_OF, // Floating-point unordered 69 ordered = CC_NOF, // floating-point ordered 70 overflow = CC_OF, // Summary overflow 71 nooverflow = CC_NOF, 72 73 mask0x0 = 0, // no jumps 74 mask0x1 = 1, 75 mask0x2 = 2, 76 mask0x3 = 3, 77 mask0x4 = 4, 78 mask0x5 = 5, 79 mask0x6 = 6, 80 mask0x7 = 7, 81 mask0x8 = 8, 82 mask0x9 = 9, 83 mask0xA = 10, 84 mask0xB = 11, 85 mask0xC = 12, 86 mask0xD = 13, 87 mask0xE = 14, 88 mask0xF = 15, 89 90 // Rounding modes for floating poing facility 91 CURRENT_ROUNDING_MODE = 0, 92 ROUND_TO_NEAREST_WITH_TIES_AWAY_FROM_0 = 1, 93 ROUND_TO_PREPARE_FOR_SHORTER_PRECISION = 3, 94 ROUND_TO_NEAREST_WITH_TIES_TO_EVEN = 4, 95 ROUND_TOWARD_0 = 5, 96 ROUND_TOWARD_PLUS_INFINITE = 6, 97 ROUND_TOWARD_MINUS_INFINITE = 7 98 }; 99 100 inline Condition NegateCondition(Condition cond) { 101 DCHECK(cond != al); 102 switch (cond) { 103 case eq: 104 return ne; 105 case ne: 106 return eq; 107 case ge: 108 return lt; 109 case gt: 110 return le; 111 case le: 112 return gt; 113 case lt: 114 return ge; 115 case lt | gt: 116 return eq; 117 case le | ge: 118 return CC_OF; 119 case CC_OF: 120 return CC_NOF; 121 default: 122 DCHECK(false); 123 } 124 return al; 125 } 126 127 // Commute a condition such that {a cond b == b cond' a}. 128 inline Condition CommuteCondition(Condition cond) { 129 switch (cond) { 130 case lt: 131 return gt; 132 case gt: 133 return lt; 134 case ge: 135 return le; 136 case le: 137 return ge; 138 case eq: 139 return eq; 140 case ne: 141 return ne; 142 default: 143 DCHECK(false); 144 return cond; 145 } 146 } 147 148 // ----------------------------------------------------------------------------- 149 // Instructions encoding. 150 151 // Instr is merely used by the Assembler to distinguish 32bit integers 152 // representing instructions from usual 32 bit values. 153 // Instruction objects are pointers to 32bit values, and provide methods to 154 // access the various ISA fields. 155 typedef int32_t Instr; 156 typedef uint16_t TwoByteInstr; 157 typedef uint32_t FourByteInstr; 158 typedef uint64_t SixByteInstr; 159 160 #define S390_RSY_A_OPCODE_LIST(V) \ 161 V(lmg, LMG, 0xEB04) /* type = RSY_A LOAD MULTIPLE (64) */ \ 162 V(srag, SRAG, 0xEB0A) /* type = RSY_A SHIFT RIGHT SINGLE (64) */ \ 163 V(slag, SLAG, 0xEB0B) /* type = RSY_A SHIFT LEFT SINGLE (64) */ \ 164 V(srlg, SRLG, 0xEB0C) /* type = RSY_A SHIFT RIGHT SINGLE LOGICAL (64) */ \ 165 V(sllg, SLLG, 0xEB0D) /* type = RSY_A SHIFT LEFT SINGLE LOGICAL (64) */ \ 166 V(tracg, TRACG, 0xEB0F) /* type = RSY_A TRACE (64) */ \ 167 V(csy, CSY, 0xEB14) /* type = RSY_A COMPARE AND SWAP (32) */ \ 168 V(rllg, RLLG, 0xEB1C) /* type = RSY_A ROTATE LEFT SINGLE LOGICAL (64) */ \ 169 V(rll, RLL, 0xEB1D) /* type = RSY_A ROTATE LEFT SINGLE LOGICAL (32) */ \ 170 V(stmg, STMG, 0xEB24) /* type = RSY_A STORE MULTIPLE (64) */ \ 171 V(stctg, STCTG, 0xEB25) /* type = RSY_A STORE CONTROL (64) */ \ 172 V(stmh, STMH, 0xEB26) /* type = RSY_A STORE MULTIPLE HIGH (32) */ \ 173 V(lctlg, LCTLG, 0xEB2F) /* type = RSY_A LOAD CONTROL (64) */ \ 174 V(csg, CSG, 0xEB30) /* type = RSY_A COMPARE AND SWAP (64) */ \ 175 V(cdsy, CDSY, 0xEB31) /* type = RSY_A COMPARE DOUBLE AND SWAP (32) */ \ 176 V(cdsg, CDSG, 0xEB3E) /* type = RSY_A COMPARE DOUBLE AND SWAP (64) */ \ 177 V(bxhg, BXHG, 0xEB44) /* type = RSY_A BRANCH ON INDEX HIGH (64) */ \ 178 V(bxleg, BXLEG, 0xEB45) /* type = RSY_A BRANCH ON INDEX LOW OR EQUAL (64) */ \ 179 V(ecag, ECAG, 0xEB4C) /* type = RSY_A EXTRACT CPU ATTRIBUTE */ \ 180 V(mvclu, MVCLU, 0xEB8E) /* type = RSY_A MOVE LONG UNICODE */ \ 181 V(clclu, CLCLU, 0xEB8F) /* type = RSY_A COMPARE LOGICAL LONG UNICODE */ \ 182 V(stmy, STMY, 0xEB90) /* type = RSY_A STORE MULTIPLE (32) */ \ 183 V(lmh, LMH, 0xEB96) /* type = RSY_A LOAD MULTIPLE HIGH (32) */ \ 184 V(lmy, LMY, 0xEB98) /* type = RSY_A LOAD MULTIPLE (32) */ \ 185 V(lamy, LAMY, 0xEB9A) /* type = RSY_A LOAD ACCESS MULTIPLE */ \ 186 V(stamy, STAMY, 0xEB9B) /* type = RSY_A STORE ACCESS MULTIPLE */ \ 187 V(srak, SRAK, 0xEBDC) /* type = RSY_A SHIFT RIGHT SINGLE (32) */ \ 188 V(slak, SLAK, 0xEBDD) /* type = RSY_A SHIFT LEFT SINGLE (32) */ \ 189 V(srlk, SRLK, 0xEBDE) /* type = RSY_A SHIFT RIGHT SINGLE LOGICAL (32) */ \ 190 V(sllk, SLLK, 0xEBDF) /* type = RSY_A SHIFT LEFT SINGLE LOGICAL (32) */ \ 191 V(lang, LANG, 0xEBE4) /* type = RSY_A LOAD AND AND (64) */ \ 192 V(laog, LAOG, 0xEBE6) /* type = RSY_A LOAD AND OR (64) */ \ 193 V(laxg, LAXG, 0xEBE7) /* type = RSY_A LOAD AND EXCLUSIVE OR (64) */ \ 194 V(laag, LAAG, 0xEBE8) /* type = RSY_A LOAD AND ADD (64) */ \ 195 V(laalg, LAALG, 0xEBEA) /* type = RSY_A LOAD AND ADD LOGICAL (64) */ \ 196 V(lan, LAN, 0xEBF4) /* type = RSY_A LOAD AND AND (32) */ \ 197 V(lao, LAO, 0xEBF6) /* type = RSY_A LOAD AND OR (32) */ \ 198 V(lax, LAX, 0xEBF7) /* type = RSY_A LOAD AND EXCLUSIVE OR (32) */ \ 199 V(laa, LAA, 0xEBF8) /* type = RSY_A LOAD AND ADD (32) */ \ 200 V(laal, LAAL, 0xEBFA) /* type = RSY_A LOAD AND ADD LOGICAL (32) */ 201 202 #define S390_RSY_B_OPCODE_LIST(V) \ 203 V(clmh, CLMH, \ 204 0xEB20) /* type = RSY_B COMPARE LOGICAL CHAR. UNDER MASK (high) */ \ 205 V(clmy, CLMY, \ 206 0xEB21) /* type = RSY_B COMPARE LOGICAL CHAR. UNDER MASK (low) */ \ 207 V(clt, CLT, 0xEB23) /* type = RSY_B COMPARE LOGICAL AND TRAP (32) */ \ 208 V(clgt, CLGT, 0xEB2B) /* type = RSY_B COMPARE LOGICAL AND TRAP (64) */ \ 209 V(stcmh, STCMH, \ 210 0xEB2C) /* type = RSY_B STORE CHARACTERS UNDER MASK (high) */ \ 211 V(stcmy, STCMY, 0xEB2D) /* type = RSY_B STORE CHARACTERS UNDER MASK (low) */ \ 212 V(icmh, ICMH, 0xEB80) /* type = RSY_B INSERT CHARACTERS UNDER MASK (high) */ \ 213 V(icmy, ICMY, 0xEB81) /* type = RSY_B INSERT CHARACTERS UNDER MASK (low) */ \ 214 V(locfh, LOCFH, 0xEBE0) /* type = RSY_B LOAD HIGH ON CONDITION (32) */ \ 215 V(stocfh, STOCFH, 0xEBE1) /* type = RSY_B STORE HIGH ON CONDITION */ \ 216 V(locg, LOCG, 0xEBE2) /* type = RSY_B LOAD ON CONDITION (64) */ \ 217 V(stocg, STOCG, 0xEBE3) /* type = RSY_B STORE ON CONDITION (64) */ \ 218 V(loc, LOC, 0xEBF2) /* type = RSY_B LOAD ON CONDITION (32) */ \ 219 V(stoc, STOC, 0xEBF3) /* type = RSY_B STORE ON CONDITION (32) */ 220 221 #define S390_RXE_OPCODE_LIST(V) \ 222 V(lcbb, LCBB, 0xE727) /* type = RXE LOAD COUNT TO BLOCK BOUNDARY */ \ 223 V(ldeb, LDEB, 0xED04) /* type = RXE LOAD LENGTHENED (short to long BFP) */ \ 224 V(lxdb, LXDB, \ 225 0xED05) /* type = RXE LOAD LENGTHENED (long to extended BFP) */ \ 226 V(lxeb, LXEB, \ 227 0xED06) /* type = RXE LOAD LENGTHENED (short to extended BFP) */ \ 228 V(mxdb, MXDB, 0xED07) /* type = RXE MULTIPLY (long to extended BFP) */ \ 229 V(keb, KEB, 0xED08) /* type = RXE COMPARE AND SIGNAL (short BFP) */ \ 230 V(ceb, CEB, 0xED09) /* type = RXE COMPARE (short BFP) */ \ 231 V(aeb, AEB, 0xED0A) /* type = RXE ADD (short BFP) */ \ 232 V(seb, SEB, 0xED0B) /* type = RXE SUBTRACT (short BFP) */ \ 233 V(mdeb, MDEB, 0xED0C) /* type = RXE MULTIPLY (short to long BFP) */ \ 234 V(deb, DEB, 0xED0D) /* type = RXE DIVIDE (short BFP) */ \ 235 V(tceb, TCEB, 0xED10) /* type = RXE TEST DATA CLASS (short BFP) */ \ 236 V(tcdb, TCDB, 0xED11) /* type = RXE TEST DATA CLASS (long BFP) */ \ 237 V(tcxb, TCXB, 0xED12) /* type = RXE TEST DATA CLASS (extended BFP) */ \ 238 V(sqeb, SQEB, 0xED14) /* type = RXE SQUARE ROOT (short BFP) */ \ 239 V(sqdb, SQDB, 0xED15) /* type = RXE SQUARE ROOT (long BFP) */ \ 240 V(meeb, MEEB, 0xED17) /* type = RXE MULTIPLY (short BFP) */ \ 241 V(kdb, KDB, 0xED18) /* type = RXE COMPARE AND SIGNAL (long BFP) */ \ 242 V(cdb, CDB, 0xED19) /* type = RXE COMPARE (long BFP) */ \ 243 V(adb, ADB, 0xED1A) /* type = RXE ADD (long BFP) */ \ 244 V(sdb, SDB, 0xED1B) /* type = RXE SUBTRACT (long BFP) */ \ 245 V(mdb, MDB, 0xED1C) /* type = RXE MULTIPLY (long BFP) */ \ 246 V(ddb, DDB, 0xED1D) /* type = RXE DIVIDE (long BFP) */ \ 247 V(lde, LDE, 0xED24) /* type = RXE LOAD LENGTHENED (short to long HFP) */ \ 248 V(lxd, LXD, \ 249 0xED25) /* type = RXE LOAD LENGTHENED (long to extended HFP) */ \ 250 V(lxe, LXE, \ 251 0xED26) /* type = RXE LOAD LENGTHENED (short to extended HFP) */ \ 252 V(sqe, SQE, 0xED34) /* type = RXE SQUARE ROOT (short HFP) */ \ 253 V(sqd, SQD, 0xED35) /* type = RXE SQUARE ROOT (long HFP) */ \ 254 V(mee, MEE, 0xED37) /* type = RXE MULTIPLY (short HFP) */ \ 255 V(tdcet, TDCET, 0xED50) /* type = RXE TEST DATA CLASS (short DFP) */ \ 256 V(tdget, TDGET, 0xED51) /* type = RXE TEST DATA GROUP (short DFP) */ \ 257 V(tdcdt, TDCDT, 0xED54) /* type = RXE TEST DATA CLASS (long DFP) */ \ 258 V(tdgdt, TDGDT, 0xED55) /* type = RXE TEST DATA GROUP (long DFP) */ \ 259 V(tdcxt, TDCXT, 0xED58) /* type = RXE TEST DATA CLASS (extended DFP) */ \ 260 V(tdgxt, TDGXT, 0xED59) /* type = RXE TEST DATA GROUP (extended DFP) */ 261 262 #define S390_RRF_A_OPCODE_LIST(V) \ 263 V(ipte, IPTE, 0xB221) /* type = RRF_A INVALIDATE PAGE TABLE ENTRY */ \ 264 V(mdtr, MDTR, 0xB3D0) /* type = RRF_A MULTIPLY (long DFP) */ \ 265 V(mdtra, MDTRA, 0xB3D0) /* type = RRF_A MULTIPLY (long DFP) */ \ 266 V(ddtr, DDTR, 0xB3D1) /* type = RRF_A DIVIDE (long DFP) */ \ 267 V(ddtra, DDTRA, 0xB3D1) /* type = RRF_A DIVIDE (long DFP) */ \ 268 V(adtr, ADTR, 0xB3D2) /* type = RRF_A ADD (long DFP) */ \ 269 V(adtra, ADTRA, 0xB3D2) /* type = RRF_A ADD (long DFP) */ \ 270 V(sdtr, SDTR, 0xB3D3) /* type = RRF_A SUBTRACT (long DFP) */ \ 271 V(sdtra, SDTRA, 0xB3D3) /* type = RRF_A SUBTRACT (long DFP) */ \ 272 V(mxtr, MXTR, 0xB3D8) /* type = RRF_A MULTIPLY (extended DFP) */ \ 273 V(mxtra, MXTRA, 0xB3D8) /* type = RRF_A MULTIPLY (extended DFP) */ \ 274 V(msrkc, MSRKC, 0xB9FD) /* type = RRF_A MULTIPLY (32)*/ \ 275 V(msgrkc, MSGRKC, 0xB9ED) /* type = RRF_A MULTIPLY (64)*/ \ 276 V(dxtr, DXTR, 0xB3D9) /* type = RRF_A DIVIDE (extended DFP) */ \ 277 V(dxtra, DXTRA, 0xB3D9) /* type = RRF_A DIVIDE (extended DFP) */ \ 278 V(axtr, AXTR, 0xB3DA) /* type = RRF_A ADD (extended DFP) */ \ 279 V(axtra, AXTRA, 0xB3DA) /* type = RRF_A ADD (extended DFP) */ \ 280 V(sxtr, SXTR, 0xB3DB) /* type = RRF_A SUBTRACT (extended DFP) */ \ 281 V(sxtra, SXTRA, 0xB3DB) /* type = RRF_A SUBTRACT (extended DFP) */ \ 282 V(ahhhr, AHHHR, 0xB9C8) /* type = RRF_A ADD HIGH (32) */ \ 283 V(shhhr, SHHHR, 0xB9C9) /* type = RRF_A SUBTRACT HIGH (32) */ \ 284 V(alhhhr, ALHHHR, 0xB9CA) /* type = RRF_A ADD LOGICAL HIGH (32) */ \ 285 V(slhhhr, SLHHHR, 0xB9CB) /* type = RRF_A SUBTRACT LOGICAL HIGH (32) */ \ 286 V(ahhlr, AHHLR, 0xB9D8) /* type = RRF_A ADD HIGH (32) */ \ 287 V(shhlr, SHHLR, 0xB9D9) /* type = RRF_A SUBTRACT HIGH (32) */ \ 288 V(alhhlr, ALHHLR, 0xB9DA) /* type = RRF_A ADD LOGICAL HIGH (32) */ \ 289 V(slhhlr, SLHHLR, 0xB9DB) /* type = RRF_A SUBTRACT LOGICAL HIGH (32) */ \ 290 V(ngrk, NGRK, 0xB9E4) /* type = RRF_A AND (64) */ \ 291 V(ogrk, OGRK, 0xB9E6) /* type = RRF_A OR (64) */ \ 292 V(xgrk, XGRK, 0xB9E7) /* type = RRF_A EXCLUSIVE OR (64) */ \ 293 V(agrk, AGRK, 0xB9E8) /* type = RRF_A ADD (64) */ \ 294 V(sgrk, SGRK, 0xB9E9) /* type = RRF_A SUBTRACT (64) */ \ 295 V(algrk, ALGRK, 0xB9EA) /* type = RRF_A ADD LOGICAL (64) */ \ 296 V(slgrk, SLGRK, 0xB9EB) /* type = RRF_A SUBTRACT LOGICAL (64) */ \ 297 V(nrk, NRK, 0xB9F4) /* type = RRF_A AND (32) */ \ 298 V(ork, ORK, 0xB9F6) /* type = RRF_A OR (32) */ \ 299 V(xrk, XRK, 0xB9F7) /* type = RRF_A EXCLUSIVE OR (32) */ \ 300 V(ark, ARK, 0xB9F8) /* type = RRF_A ADD (32) */ \ 301 V(srk, SRK, 0xB9F9) /* type = RRF_A SUBTRACT (32) */ \ 302 V(alrk, ALRK, 0xB9FA) /* type = RRF_A ADD LOGICAL (32) */ \ 303 V(slrk, SLRK, 0xB9FB) /* type = RRF_A SUBTRACT LOGICAL (32) */ 304 305 #define S390_RXF_OPCODE_LIST(V) \ 306 V(maeb, MAEB, 0xED0E) /* type = RXF MULTIPLY AND ADD (short BFP) */ \ 307 V(mseb, MSEB, 0xED0F) /* type = RXF MULTIPLY AND SUBTRACT (short BFP) */ \ 308 V(madb, MADB, 0xED1E) /* type = RXF MULTIPLY AND ADD (long BFP) */ \ 309 V(msdb, MSDB, 0xED1F) /* type = RXF MULTIPLY AND SUBTRACT (long BFP) */ \ 310 V(mae, MAE, 0xED2E) /* type = RXF MULTIPLY AND ADD (short HFP) */ \ 311 V(mse, MSE, 0xED2F) /* type = RXF MULTIPLY AND SUBTRACT (short HFP) */ \ 312 V(mayl, MAYL, \ 313 0xED38) /* type = RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) */ \ 314 V(myl, MYL, \ 315 0xED39) /* type = RXF MULTIPLY UNNORM. (long to ext. low HFP) */ \ 316 V(may, MAY, \ 317 0xED3A) /* type = RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) */ \ 318 V(my, MY, \ 319 0xED3B) /* type = RXF MULTIPLY UNNORMALIZED (long to ext. HFP) */ \ 320 V(mayh, MAYH, \ 321 0xED3C) /* type = RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) */ \ 322 V(myh, MYH, \ 323 0xED3D) /* type = RXF MULTIPLY UNNORM. (long to ext. high HFP) */ \ 324 V(mad, MAD, 0xED3E) /* type = RXF MULTIPLY AND ADD (long HFP) */ \ 325 V(msd, MSD, 0xED3F) /* type = RXF MULTIPLY AND SUBTRACT (long HFP) */ \ 326 V(sldt, SLDT, 0xED40) /* type = RXF SHIFT SIGNIFICAND LEFT (long DFP) */ \ 327 V(srdt, SRDT, 0xED41) /* type = RXF SHIFT SIGNIFICAND RIGHT (long DFP) */ \ 328 V(slxt, SLXT, \ 329 0xED48) /* type = RXF SHIFT SIGNIFICAND LEFT (extended DFP) */ \ 330 V(srxt, SRXT, \ 331 0xED49) /* type = RXF SHIFT SIGNIFICAND RIGHT (extended DFP) */ 332 333 #define S390_IE_OPCODE_LIST(V) \ 334 V(niai, NIAI, 0xB2FA) /* type = IE NEXT INSTRUCTION ACCESS INTENT */ 335 336 #define S390_RRF_B_OPCODE_LIST(V) \ 337 V(diebr, DIEBR, 0xB353) /* type = RRF_B DIVIDE TO INTEGER (short BFP) */ \ 338 V(didbr, DIDBR, 0xB35B) /* type = RRF_B DIVIDE TO INTEGER (long BFP) */ \ 339 V(cpsdr, CPSDR, 0xB372) /* type = RRF_B COPY SIGN (long) */ \ 340 V(qadtr, QADTR, 0xB3F5) /* type = RRF_B QUANTIZE (long DFP) */ \ 341 V(iedtr, IEDTR, \ 342 0xB3F6) /* type = RRF_B INSERT BIASED EXPONENT (64 to long DFP) */ \ 343 V(rrdtr, RRDTR, 0xB3F7) /* type = RRF_B REROUND (long DFP) */ \ 344 V(qaxtr, QAXTR, 0xB3FD) /* type = RRF_B QUANTIZE (extended DFP) */ \ 345 V(iextr, IEXTR, \ 346 0xB3FE) /* type = RRF_B INSERT BIASED EXPONENT (64 to extended DFP) */ \ 347 V(rrxtr, RRXTR, 0xB3FF) /* type = RRF_B REROUND (extended DFP) */ \ 348 V(kmctr, KMCTR, 0xB92D) /* type = RRF_B CIPHER MESSAGE WITH COUNTER */ \ 349 V(idte, IDTE, 0xB98E) /* type = RRF_B INVALIDATE DAT TABLE ENTRY */ \ 350 V(crdte, CRDTE, \ 351 0xB98F) /* type = RRF_B COMPARE AND REPLACE DAT TABLE ENTRY */ \ 352 V(lptea, LPTEA, 0xB9AA) /* type = RRF_B LOAD PAGE TABLE ENTRY ADDRESS */ 353 354 #define S390_RRF_C_OPCODE_LIST(V) \ 355 V(sske, SSKE, 0xB22B) /* type = RRF_C SET STORAGE KEY EXTENDED */ \ 356 V(cuutf, CUUTF, 0xB2A6) /* type = RRF_C CONVERT UNICODE TO UTF-8 */ \ 357 V(cu21, CU21, 0xB2A6) /* type = RRF_C CONVERT UTF-16 TO UTF-8 */ \ 358 V(cutfu, CUTFU, 0xB2A7) /* type = RRF_C CONVERT UTF-8 TO UNICODE */ \ 359 V(cu12, CU12, 0xB2A7) /* type = RRF_C CONVERT UTF-8 TO UTF-16 */ \ 360 V(ppa, PPA, 0xB2E8) /* type = RRF_C PERFORM PROCESSOR ASSIST */ \ 361 V(cgrt, CGRT, 0xB960) /* type = RRF_C COMPARE AND TRAP (64) */ \ 362 V(clgrt, CLGRT, 0xB961) /* type = RRF_C COMPARE LOGICAL AND TRAP (64) */ \ 363 V(crt, CRT, 0xB972) /* type = RRF_C COMPARE AND TRAP (32) */ \ 364 V(clrt, CLRT, 0xB973) /* type = RRF_C COMPARE LOGICAL AND TRAP (32) */ \ 365 V(trtt, TRTT, 0xB990) /* type = RRF_C TRANSLATE TWO TO TWO */ \ 366 V(trto, TRTO, 0xB991) /* type = RRF_C TRANSLATE TWO TO ONE */ \ 367 V(trot, TROT, 0xB992) /* type = RRF_C TRANSLATE ONE TO TWO */ \ 368 V(troo, TROO, 0xB993) /* type = RRF_C TRANSLATE ONE TO ONE */ \ 369 V(cu14, CU14, 0xB9B0) /* type = RRF_C CONVERT UTF-8 TO UTF-32 */ \ 370 V(cu24, CU24, 0xB9B1) /* type = RRF_C CONVERT UTF-16 TO UTF-32 */ \ 371 V(trtre, TRTRE, \ 372 0xB9BD) /* type = RRF_C TRANSLATE AND TEST REVERSE EXTENDED */ \ 373 V(trte, TRTE, 0xB9BF) /* type = RRF_C TRANSLATE AND TEST EXTENDED */ \ 374 V(locfhr, LOCFHR, 0xB9E0) /* type = RRF_C LOAD HIGH ON CONDITION (32) */ \ 375 V(locgr, LOCGR, 0xB9E2) /* type = RRF_C LOAD ON CONDITION (64) */ \ 376 V(locr, LOCR, 0xB9F2) /* type = RRF_C LOAD ON CONDITION (32) */ 377 378 #define S390_MII_OPCODE_LIST(V) \ 379 V(bprp, BPRP, 0xC5) /* type = MII BRANCH PREDICTION RELATIVE PRELOAD */ 380 381 #define S390_RRF_D_OPCODE_LIST(V) \ 382 V(ldetr, LDETR, \ 383 0xB3D4) /* type = RRF_D LOAD LENGTHENED (short to long DFP) */ \ 384 V(lxdtr, LXDTR, \ 385 0xB3DC) /* type = RRF_D LOAD LENGTHENED (long to extended DFP) */ \ 386 V(csdtr, CSDTR, \ 387 0xB3E3) /* type = RRF_D CONVERT TO SIGNED PACKED (long DFP to 64) */ \ 388 V(csxtr, CSXTR, \ 389 0xB3EB) /* type = RRF_D CONVERT TO SIGNED PACKED (extended DFP to 128) */ 390 391 #define S390_RRF_E_OPCODE_LIST(V) \ 392 V(ledbra, LEDBRA, \ 393 0xB344) /* type = RRF_E LOAD ROUNDED (long to short BFP) */ \ 394 V(ldxbra, LDXBRA, \ 395 0xB345) /* type = RRF_E LOAD ROUNDED (extended to long BFP) */ \ 396 V(lexbra, LEXBRA, \ 397 0xB346) /* type = RRF_E LOAD ROUNDED (extended to short BFP) */ \ 398 V(fixbr, FIXBR, 0xB347) /* type = RRF_E LOAD FP INTEGER (extended BFP) */ \ 399 V(fixbra, FIXBRA, 0xB347) /* type = RRF_E LOAD FP INTEGER (extended BFP) */ \ 400 V(tbedr, TBEDR, \ 401 0xB350) /* type = RRF_E CONVERT HFP TO BFP (long to short) */ \ 402 V(tbdr, TBDR, 0xB351) /* type = RRF_E CONVERT HFP TO BFP (long) */ \ 403 V(fiebr, FIEBR, 0xB357) /* type = RRF_E LOAD FP INTEGER (short BFP) */ \ 404 V(fiebra, FIEBRA, 0xB357) /* type = RRF_E LOAD FP INTEGER (short BFP) */ \ 405 V(fidbr, FIDBR, 0xB35F) /* type = RRF_E LOAD FP INTEGER (long BFP) */ \ 406 V(fidbra, FIDBRA, 0xB35F) /* type = RRF_E LOAD FP INTEGER (long BFP) */ \ 407 V(celfbr, CELFBR, \ 408 0xB390) /* type = RRF_E CONVERT FROM LOGICAL (32 to short BFP) */ \ 409 V(cdlfbr, CDLFBR, \ 410 0xB391) /* type = RRF_E CONVERT FROM LOGICAL (32 to long BFP) */ \ 411 V(cxlfbr, CXLFBR, \ 412 0xB392) /* type = RRF_E CONVERT FROM LOGICAL (32 to extended BFP) */ \ 413 V(cefbra, CEFBRA, \ 414 0xB394) /* type = RRF_E CONVERT FROM FIXED (32 to short BFP) */ \ 415 V(cdfbra, CDFBRA, \ 416 0xB395) /* type = RRF_E CONVERT FROM FIXED (32 to long BFP) */ \ 417 V(cxfbra, CXFBRA, \ 418 0xB396) /* type = RRF_E CONVERT FROM FIXED (32 to extended BFP) */ \ 419 V(cfebr, CFEBR, \ 420 0xB398) /* type = RRF_E CONVERT TO FIXED (short BFP to 32) */ \ 421 V(cfebra, CFEBRA, \ 422 0xB398) /* type = RRF_E CONVERT TO FIXED (short BFP to 32) */ \ 423 V(cfdbr, CFDBR, 0xB399) /* type = RRF_E CONVERT TO FIXED (long BFP to 32) */ \ 424 V(cfdbra, CFDBRA, \ 425 0xB399) /* type = RRF_E CONVERT TO FIXED (long BFP to 32) */ \ 426 V(cfxbr, CFXBR, \ 427 0xB39A) /* type = RRF_E CONVERT TO FIXED (extended BFP to 32) */ \ 428 V(cfxbra, CFXBRA, \ 429 0xB39A) /* type = RRF_E CONVERT TO FIXED (extended BFP to 32) */ \ 430 V(clfebr, CLFEBR, \ 431 0xB39C) /* type = RRF_E CONVERT TO LOGICAL (short BFP to 32) */ \ 432 V(clfdbr, CLFDBR, \ 433 0xB39D) /* type = RRF_E CONVERT TO LOGICAL (long BFP to 32) */ \ 434 V(clfxbr, CLFXBR, \ 435 0xB39E) /* type = RRF_E CONVERT TO LOGICAL (extended BFP to 32) */ \ 436 V(celgbr, CELGBR, \ 437 0xB3A0) /* type = RRF_E CONVERT FROM LOGICAL (64 to short BFP) */ \ 438 V(cdlgbr, CDLGBR, \ 439 0xB3A1) /* type = RRF_E CONVERT FROM LOGICAL (64 to long BFP) */ \ 440 V(cxlgbr, CXLGBR, \ 441 0xB3A2) /* type = RRF_E CONVERT FROM LOGICAL (64 to extended BFP) */ \ 442 V(cegbra, CEGBRA, \ 443 0xB3A4) /* type = RRF_E CONVERT FROM FIXED (64 to short BFP) */ \ 444 V(cdgbra, CDGBRA, \ 445 0xB3A5) /* type = RRF_E CONVERT FROM FIXED (64 to long BFP) */ \ 446 V(cxgbra, CXGBRA, \ 447 0xB3A6) /* type = RRF_E CONVERT FROM FIXED (64 to extended BFP) */ \ 448 V(cgebr, CGEBR, \ 449 0xB3A8) /* type = RRF_E CONVERT TO FIXED (short BFP to 64) */ \ 450 V(cgebra, CGEBRA, \ 451 0xB3A8) /* type = RRF_E CONVERT TO FIXED (short BFP to 64) */ \ 452 V(cgdbr, CGDBR, 0xB3A9) /* type = RRF_E CONVERT TO FIXED (long BFP to 64) */ \ 453 V(cgdbra, CGDBRA, \ 454 0xB3A9) /* type = RRF_E CONVERT TO FIXED (long BFP to 64) */ \ 455 V(cgxbr, CGXBR, \ 456 0xB3AA) /* type = RRF_E CONVERT TO FIXED (extended BFP to 64) */ \ 457 V(cgxbra, CGXBRA, \ 458 0xB3AA) /* type = RRF_E CONVERT TO FIXED (extended BFP to 64) */ \ 459 V(clgebr, CLGEBR, \ 460 0xB3AC) /* type = RRF_E CONVERT TO LOGICAL (short BFP to 64) */ \ 461 V(clgdbr, CLGDBR, \ 462 0xB3AD) /* type = RRF_E CONVERT TO LOGICAL (long BFP to 64) */ \ 463 V(clgxbr, CLGXBR, \ 464 0xB3AE) /* type = RRF_E CONVERT TO LOGICAL (extended BFP to 64) */ \ 465 V(cfer, CFER, 0xB3B8) /* type = RRF_E CONVERT TO FIXED (short HFP to 32) */ \ 466 V(cfdr, CFDR, 0xB3B9) /* type = RRF_E CONVERT TO FIXED (long HFP to 32) */ \ 467 V(cfxr, CFXR, \ 468 0xB3BA) /* type = RRF_E CONVERT TO FIXED (extended HFP to 32) */ \ 469 V(cger, CGER, 0xB3C8) /* type = RRF_E CONVERT TO FIXED (short HFP to 64) */ \ 470 V(cgdr, CGDR, 0xB3C9) /* type = RRF_E CONVERT TO FIXED (long HFP to 64) */ \ 471 V(cgxr, CGXR, \ 472 0xB3CA) /* type = RRF_E CONVERT TO FIXED (extended HFP to 64) */ \ 473 V(ledtr, LEDTR, 0xB3D5) /* type = RRF_E LOAD ROUNDED (long to short DFP) */ \ 474 V(fidtr, FIDTR, 0xB3D7) /* type = RRF_E LOAD FP INTEGER (long DFP) */ \ 475 V(ldxtr, LDXTR, \ 476 0xB3DD) /* type = RRF_E LOAD ROUNDED (extended to long DFP) */ \ 477 V(fixtr, FIXTR, 0xB3DF) /* type = RRF_E LOAD FP INTEGER (extended DFP) */ \ 478 V(cgdtr, CGDTR, 0xB3E1) /* type = RRF_E CONVERT TO FIXED (long DFP to 64) */ \ 479 V(cgdtra, CGDTRA, \ 480 0xB3E1) /* type = RRF_E CONVERT TO FIXED (long DFP to 64) */ \ 481 V(cgxtr, CGXTR, \ 482 0xB3E9) /* type = RRF_E CONVERT TO FIXED (extended DFP to 64) */ \ 483 V(cgxtra, CGXTRA, \ 484 0xB3E9) /* type = RRF_E CONVERT TO FIXED (extended DFP to 64) */ \ 485 V(cdgtra, CDGTRA, \ 486 0xB3F1) /* type = RRF_E CONVERT FROM FIXED (64 to long DFP) */ \ 487 V(cxgtra, CXGTRA, \ 488 0xB3F9) /* type = RRF_E CONVERT FROM FIXED (64 to extended DFP) */ \ 489 V(cfdtr, CFDTR, 0xB941) /* type = RRF_E CONVERT TO FIXED (long DFP to 32) */ \ 490 V(clgdtr, CLGDTR, \ 491 0xB942) /* type = RRF_E CONVERT TO LOGICAL (long DFP to 64) */ \ 492 V(clfdtr, CLFDTR, \ 493 0xB943) /* type = RRF_E CONVERT TO LOGICAL (long DFP to 32) */ \ 494 V(cfxtr, CFXTR, \ 495 0xB949) /* type = RRF_E CONVERT TO FIXED (extended DFP to 32) */ \ 496 V(clgxtr, CLGXTR, \ 497 0xB94A) /* type = RRF_E CONVERT TO LOGICAL (extended DFP to 64) */ \ 498 V(clfxtr, CLFXTR, \ 499 0xB94B) /* type = RRF_E CONVERT TO LOGICAL (extended DFP to 32) */ \ 500 V(cdlgtr, CDLGTR, \ 501 0xB952) /* type = RRF_E CONVERT FROM LOGICAL (64 to long DFP) */ \ 502 V(cdlftr, CDLFTR, \ 503 0xB953) /* type = RRF_E CONVERT FROM LOGICAL (32 to long DFP) */ \ 504 V(cxlgtr, CXLGTR, \ 505 0xB95A) /* type = RRF_E CONVERT FROM LOGICAL (64 to extended DFP) */ \ 506 V(cxlftr, CXLFTR, \ 507 0xB95B) /* type = RRF_E CONVERT FROM LOGICAL (32 to extended DFP) */ 508 509 #define S390_VRR_A_OPCODE_LIST(V) \ 510 V(vpopct, VPOPCT, 0xE750) /* type = VRR_A VECTOR POPULATION COUNT */ \ 511 V(vctz, VCTZ, 0xE752) /* type = VRR_A VECTOR COUNT TRAILING ZEROS */ \ 512 V(vclz, VCLZ, 0xE753) /* type = VRR_A VECTOR COUNT LEADING ZEROS */ \ 513 V(vlr, VLR, 0xE756) /* type = VRR_A VECTOR LOAD */ \ 514 V(vistr, VISTR, 0xE75C) /* type = VRR_A VECTOR ISOLATE STRING */ \ 515 V(vseg, VSEG, 0xE75F) /* type = VRR_A VECTOR SIGN EXTEND TO DOUBLEWORD */ \ 516 V(vclgd, VCLGD, \ 517 0xE7C0) /* type = VRR_A VECTOR FP CONVERT TO LOGICAL 64-BIT */ \ 518 V(vcdlg, VCDLG, \ 519 0xE7C1) /* type = VRR_A VECTOR FP CONVERT FROM LOGICAL 64-BIT */ \ 520 V(vcgd, VCGD, 0xE7C2) /* type = VRR_A VECTOR FP CONVERT TO FIXED 64-BIT */ \ 521 V(vcdg, VCDG, 0xE7C3) /* type = VRR_A VECTOR FP CONVERT FROM FIXED 64-BIT */ \ 522 V(vlde, VLDE, 0xE7C4) /* type = VRR_A VECTOR FP LOAD LENGTHENED */ \ 523 V(vled, VLED, 0xE7C5) /* type = VRR_A VECTOR FP LOAD ROUNDED */ \ 524 V(vfi, VFI, 0xE7C7) /* type = VRR_A VECTOR LOAD FP INTEGER */ \ 525 V(wfk, WFK, 0xE7CA) /* type = VRR_A VECTOR FP COMPARE AND SIGNAL SCALAR */ \ 526 V(wfc, WFC, 0xE7CB) /* type = VRR_A VECTOR FP COMPARE SCALAR */ \ 527 V(vfpso, VFPSO, 0xE7CC) /* type = VRR_A VECTOR FP PERFORM SIGN OPERATION */ \ 528 V(vfsq, VFSQ, 0xE7CE) /* type = VRR_A VECTOR FP SQUARE ROOT */ \ 529 V(vupll, VUPLL, 0xE7D4) /* type = VRR_A VECTOR UNPACK LOGICAL LOW */ \ 530 V(vuplh, VUPLH, 0xE7D5) /* type = VRR_A VECTOR UNPACK LOGICAL HIGH */ \ 531 V(vupl, VUPL, 0xE7D6) /* type = VRR_A VECTOR UNPACK LOW */ \ 532 V(vuph, VUPH, 0xE7D7) /* type = VRR_A VECTOR UNPACK HIGH */ \ 533 V(vtm, VTM, 0xE7D8) /* type = VRR_A VECTOR TEST UNDER MASK */ \ 534 V(vecl, VECL, 0xE7D9) /* type = VRR_A VECTOR ELEMENT COMPARE LOGICAL */ \ 535 V(vec, VEC, 0xE7DB) /* type = VRR_A VECTOR ELEMENT COMPARE */ \ 536 V(vlc, VLC, 0xE7DE) /* type = VRR_A VECTOR LOAD COMPLEMENT */ \ 537 V(vlp, VLP, 0xE7DF) /* type = VRR_A VECTOR LOAD POSITIVE */ 538 539 #define S390_VRR_B_OPCODE_LIST(V) \ 540 V(vfee, VFEE, 0xE780) /* type = VRR_B VECTOR FIND ELEMENT EQUAL */ \ 541 V(vfene, VFENE, 0xE781) /* type = VRR_B VECTOR FIND ELEMENT NOT EQUAL */ \ 542 V(vfae, VFAE, 0xE782) /* type = VRR_B VECTOR FIND ANY ELEMENT EQUAL */ \ 543 V(vpkls, VPKLS, 0xE795) /* type = VRR_B VECTOR PACK LOGICAL SATURATE */ \ 544 V(vpks, VPKS, 0xE797) /* type = VRR_B VECTOR PACK SATURATE */ \ 545 V(vceq, VCEQ, 0xE7F8) /* type = VRR_B VECTOR COMPARE EQUAL */ \ 546 V(vchl, VCHL, 0xE7F9) /* type = VRR_B VECTOR COMPARE HIGH LOGICAL */ \ 547 V(vch, VCH, 0xE7FB) /* type = VRR_B VECTOR COMPARE HIGH */ 548 549 #define S390_VRR_C_OPCODE_LIST(V) \ 550 V(vmrl, VMRL, 0xE760) /* type = VRR_C VECTOR MERGE LOW */ \ 551 V(vmrh, VMRH, 0xE761) /* type = VRR_C VECTOR MERGE HIGH */ \ 552 V(vsum, VSUM, 0xE764) /* type = VRR_C VECTOR SUM ACROSS WORD */ \ 553 V(vsumg, VSUMG, 0xE765) /* type = VRR_C VECTOR SUM ACROSS DOUBLEWORD */ \ 554 V(vcksm, VCKSM, 0xE766) /* type = VRR_C VECTOR CHECKSUM */ \ 555 V(vsumq, VSUMQ, 0xE767) /* type = VRR_C VECTOR SUM ACROSS QUADWORD */ \ 556 V(vn, VN, 0xE768) /* type = VRR_C VECTOR AND */ \ 557 V(vnc, VNC, 0xE769) /* type = VRR_C VECTOR AND WITH COMPLEMENT */ \ 558 V(vo, VO, 0xE76A) /* type = VRR_C VECTOR OR */ \ 559 V(vno, VNO, 0xE76B) /* type = VRR_C VECTOR NOR */ \ 560 V(vx, VX, 0xE76D) /* type = VRR_C VECTOR EXCLUSIVE OR */ \ 561 V(veslv, VESLV, 0xE770) /* type = VRR_C VECTOR ELEMENT SHIFT LEFT */ \ 562 V(verllv, VERLLV, \ 563 0xE773) /* type = VRR_C VECTOR ELEMENT ROTATE LEFT LOGICAL */ \ 564 V(vsl, VSL, 0xE774) /* type = VRR_C VECTOR SHIFT LEFT */ \ 565 V(vslb, VSLB, 0xE775) /* type = VRR_C VECTOR SHIFT LEFT BY BYTE */ \ 566 V(vesrlv, VESRLV, \ 567 0xE778) /* type = VRR_C VECTOR ELEMENT SHIFT RIGHT LOGICAL */ \ 568 V(vesrav, VESRAV, \ 569 0xE77A) /* type = VRR_C VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */ \ 570 V(vsrl, VSRL, 0xE77C) /* type = VRR_C VECTOR SHIFT RIGHT LOGICAL */ \ 571 V(vsrlb, VSRLB, \ 572 0xE77D) /* type = VRR_C VECTOR SHIFT RIGHT LOGICAL BY BYTE */ \ 573 V(vsra, VSRA, 0xE77E) /* type = VRR_C VECTOR SHIFT RIGHT ARITHMETIC */ \ 574 V(vsrab, VSRAB, \ 575 0xE77F) /* type = VRR_C VECTOR SHIFT RIGHT ARITHMETIC BY BYTE */ \ 576 V(vpdi, VPDI, 0xE784) /* type = VRR_C VECTOR PERMUTE DOUBLEWORD IMMEDIATE */ \ 577 V(vpk, VPK, 0xE794) /* type = VRR_C VECTOR PACK */ \ 578 V(vmlh, VMLH, 0xE7A1) /* type = VRR_C VECTOR MULTIPLY LOGICAL HIGH */ \ 579 V(vml, VML, 0xE7A2) /* type = VRR_C VECTOR MULTIPLY LOW */ \ 580 V(vmh, VMH, 0xE7A3) /* type = VRR_C VECTOR MULTIPLY HIGH */ \ 581 V(vmle, VMLE, 0xE7A4) /* type = VRR_C VECTOR MULTIPLY LOGICAL EVEN */ \ 582 V(vmlo, VMLO, 0xE7A5) /* type = VRR_C VECTOR MULTIPLY LOGICAL ODD */ \ 583 V(vme, VME, 0xE7A6) /* type = VRR_C VECTOR MULTIPLY EVEN */ \ 584 V(vmo, VMO, 0xE7A7) /* type = VRR_C VECTOR MULTIPLY ODD */ \ 585 V(vgfm, VGFM, 0xE7B4) /* type = VRR_C VECTOR GALOIS FIELD MULTIPLY SUM */ \ 586 V(vfs, VFS, 0xE7E2) /* type = VRR_C VECTOR FP SUBTRACT */ \ 587 V(vfa, VFA, 0xE7E3) /* type = VRR_C VECTOR FP ADD */ \ 588 V(vfd, VFD, 0xE7E5) /* type = VRR_C VECTOR FP DIVIDE */ \ 589 V(vfm, VFM, 0xE7E7) /* type = VRR_C VECTOR FP MULTIPLY */ \ 590 V(vfce, VFCE, 0xE7E8) /* type = VRR_C VECTOR FP COMPARE EQUAL */ \ 591 V(vfche, VFCHE, 0xE7EA) /* type = VRR_C VECTOR FP COMPARE HIGH OR EQUAL */ \ 592 V(vfch, VFCH, 0xE7EB) /* type = VRR_C VECTOR FP COMPARE HIGH */ \ 593 V(vavgl, VAVGL, 0xE7F0) /* type = VRR_C VECTOR AVERAGE LOGICAL */ \ 594 V(vacc, VACC, 0xE7F1) /* type = VRR_C VECTOR ADD COMPUTE CARRY */ \ 595 V(vavg, VAVG, 0xE7F2) /* type = VRR_C VECTOR AVERAGE */ \ 596 V(va, VA, 0xE7F3) /* type = VRR_C VECTOR ADD */ \ 597 V(vscbi, VSCBI, \ 598 0xE7F5) /* type = VRR_C VECTOR SUBTRACT COMPUTE BORROW INDICATION */ \ 599 V(vs, VS, 0xE7F7) /* type = VRR_C VECTOR SUBTRACT */ \ 600 V(vmnl, VMNL, 0xE7FC) /* type = VRR_C VECTOR MINIMUM LOGICAL */ \ 601 V(vmxl, VMXL, 0xE7FD) /* type = VRR_C VECTOR MAXIMUM LOGICAL */ \ 602 V(vmn, VMN, 0xE7FE) /* type = VRR_C VECTOR MINIMUM */ \ 603 V(vmx, VMX, 0xE7FF) /* type = VRR_C VECTOR MAXIMUM */ 604 605 #define S390_VRI_A_OPCODE_LIST(V) \ 606 V(vleib, VLEIB, 0xE740) /* type = VRI_A VECTOR LOAD ELEMENT IMMEDIATE (8) */ \ 607 V(vleih, VLEIH, \ 608 0xE741) /* type = VRI_A VECTOR LOAD ELEMENT IMMEDIATE (16) */ \ 609 V(vleig, VLEIG, \ 610 0xE742) /* type = VRI_A VECTOR LOAD ELEMENT IMMEDIATE (64) */ \ 611 V(vleif, VLEIF, \ 612 0xE743) /* type = VRI_A VECTOR LOAD ELEMENT IMMEDIATE (32) */ \ 613 V(vgbm, VGBM, 0xE744) /* type = VRI_A VECTOR GENERATE BYTE MASK */ \ 614 V(vrepi, VREPI, 0xE745) /* type = VRI_A VECTOR REPLICATE IMMEDIATE */ 615 616 #define S390_VRR_D_OPCODE_LIST(V) \ 617 V(vstrc, VSTRC, 0xE78A) /* type = VRR_D VECTOR STRING RANGE COMPARE */ \ 618 V(vmalh, VMALH, \ 619 0xE7A9) /* type = VRR_D VECTOR MULTIPLY AND ADD LOGICAL HIGH */ \ 620 V(vmal, VMAL, 0xE7AA) /* type = VRR_D VECTOR MULTIPLY AND ADD LOW */ \ 621 V(vmah, VMAH, 0xE7AB) /* type = VRR_D VECTOR MULTIPLY AND ADD HIGH */ \ 622 V(vmale, VMALE, \ 623 0xE7AC) /* type = VRR_D VECTOR MULTIPLY AND ADD LOGICAL EVEN */ \ 624 V(vmalo, VMALO, \ 625 0xE7AD) /* type = VRR_D VECTOR MULTIPLY AND ADD LOGICAL ODD */ \ 626 V(vmae, VMAE, 0xE7AE) /* type = VRR_D VECTOR MULTIPLY AND ADD EVEN */ \ 627 V(vmao, VMAO, 0xE7AF) /* type = VRR_D VECTOR MULTIPLY AND ADD ODD */ \ 628 V(vaccc, VACCC, \ 629 0xE7B9) /* type = VRR_D VECTOR ADD WITH CARRY COMPUTE CARRY */ \ 630 V(vac, VAC, 0xE7BB) /* type = VRR_D VECTOR ADD WITH CARRY */ \ 631 V(vgfma, VGFMA, \ 632 0xE7BC) /* type = VRR_D VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */ \ 633 V(vsbcbi, VSBCBI, 0xE7BD) /* type = VRR_D VECTOR SUBTRACT WITH BORROW */ \ 634 /* COMPUTE BORROW INDICATION */ \ 635 V(vsbi, VSBI, \ 636 0xE7BF) /* type = VRR_D VECTOR SUBTRACT WITH BORROW INDICATION */ 637 638 #define S390_VRI_B_OPCODE_LIST(V) \ 639 V(vgm, VGM, 0xE746) /* type = VRI_B VECTOR GENERATE MASK */ 640 641 #define S390_VRR_E_OPCODE_LIST(V) \ 642 V(vperm, VPERM, 0xE78C) /* type = VRR_E VECTOR PERMUTE */ \ 643 V(vsel, VSEL, 0xE78D) /* type = VRR_E VECTOR SELECT */ \ 644 V(vfms, VFMS, 0xE78E) /* type = VRR_E VECTOR FP MULTIPLY AND SUBTRACT */ \ 645 V(vfma, VFMA, 0xE78F) /* type = VRR_E VECTOR FP MULTIPLY AND ADD */ 646 647 #define S390_VRI_C_OPCODE_LIST(V) \ 648 V(vrep, VREP, 0xE74D) /* type = VRI_C VECTOR REPLICATE */ 649 650 #define S390_VRI_D_OPCODE_LIST(V) \ 651 V(verim, VERIM, \ 652 0xE772) /* type = VRI_D VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */ \ 653 V(vsldb, VSLDB, 0xE777) /* type = VRI_D VECTOR SHIFT LEFT DOUBLE BY BYTE */ 654 655 #define S390_VRR_F_OPCODE_LIST(V) \ 656 V(vlvgp, VLVGP, 0xE762) /* type = VRR_F VECTOR LOAD VR FROM GRS DISJOINT */ 657 658 #define S390_RIS_OPCODE_LIST(V) \ 659 V(cgib, CGIB, \ 660 0xECFC) /* type = RIS COMPARE IMMEDIATE AND BRANCH (64<-8) */ \ 661 V(clgib, CLGIB, \ 662 0xECFD) /* type = RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) */ \ 663 V(cib, CIB, 0xECFE) /* type = RIS COMPARE IMMEDIATE AND BRANCH (32<-8) */ \ 664 V(clib, CLIB, \ 665 0xECFF) /* type = RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) */ 666 667 #define S390_VRI_E_OPCODE_LIST(V) \ 668 V(vftci, VFTCI, \ 669 0xE74A) /* type = VRI_E VECTOR FP TEST DATA CLASS IMMEDIATE */ 670 671 #define S390_RSL_A_OPCODE_LIST(V) \ 672 V(tp, TP, 0xEBC0) /* type = RSL_A TEST DECIMAL */ 673 674 #define S390_RSL_B_OPCODE_LIST(V) \ 675 V(cpdt, CPDT, 0xEDAC) /* type = RSL_B CONVERT TO PACKED (from long DFP) */ \ 676 V(cpxt, CPXT, \ 677 0xEDAD) /* type = RSL_B CONVERT TO PACKED (from extended DFP) */ \ 678 V(cdpt, CDPT, 0xEDAE) /* type = RSL_B CONVERT FROM PACKED (to long DFP) */ \ 679 V(cxpt, CXPT, \ 680 0xEDAF) /* type = RSL_B CONVERT FROM PACKED (to extended DFP) */ 681 682 #define S390_SI_OPCODE_LIST(V) \ 683 V(tm, TM, 0x91) /* type = SI TEST UNDER MASK */ \ 684 V(mvi, MVI, 0x92) /* type = SI MOVE (immediate) */ \ 685 V(ni, NI, 0x94) /* type = SI AND (immediate) */ \ 686 V(cli, CLI, 0x95) /* type = SI COMPARE LOGICAL (immediate) */ \ 687 V(oi, OI, 0x96) /* type = SI OR (immediate) */ \ 688 V(xi, XI, 0x97) /* type = SI EXCLUSIVE OR (immediate) */ \ 689 V(stnsm, STNSM, 0xAC) /* type = SI STORE THEN AND SYSTEM MASK */ \ 690 V(stosm, STOSM, 0xAD) /* type = SI STORE THEN OR SYSTEM MASK */ \ 691 V(mc, MC, 0xAF) /* type = SI MONITOR CALL */ 692 693 #define S390_SIL_OPCODE_LIST(V) \ 694 V(mvhhi, MVHHI, 0xE544) /* type = SIL MOVE (16<-16) */ \ 695 V(mvghi, MVGHI, 0xE548) /* type = SIL MOVE (64<-16) */ \ 696 V(mvhi, MVHI, 0xE54C) /* type = SIL MOVE (32<-16) */ \ 697 V(chhsi, CHHSI, \ 698 0xE554) /* type = SIL COMPARE HALFWORD IMMEDIATE (16<-16) */ \ 699 V(clhhsi, CLHHSI, \ 700 0xE555) /* type = SIL COMPARE LOGICAL IMMEDIATE (16<-16) */ \ 701 V(cghsi, CGHSI, \ 702 0xE558) /* type = SIL COMPARE HALFWORD IMMEDIATE (64<-16) */ \ 703 V(clghsi, CLGHSI, \ 704 0xE559) /* type = SIL COMPARE LOGICAL IMMEDIATE (64<-16) */ \ 705 V(chsi, CHSI, 0xE55C) /* type = SIL COMPARE HALFWORD IMMEDIATE (32<-16) */ \ 706 V(clfhsi, CLFHSI, \ 707 0xE55D) /* type = SIL COMPARE LOGICAL IMMEDIATE (32<-16) */ \ 708 V(tbegin, TBEGIN, \ 709 0xE560) /* type = SIL TRANSACTION BEGIN (nonconstrained) */ \ 710 V(tbeginc, TBEGINC, \ 711 0xE561) /* type = SIL TRANSACTION BEGIN (constrained) */ 712 713 #define S390_VRS_A_OPCODE_LIST(V) \ 714 V(vesl, VESL, 0xE730) /* type = VRS_A VECTOR ELEMENT SHIFT LEFT */ \ 715 V(verll, VERLL, \ 716 0xE733) /* type = VRS_A VECTOR ELEMENT ROTATE LEFT LOGICAL */ \ 717 V(vlm, VLM, 0xE736) /* type = VRS_A VECTOR LOAD MULTIPLE */ \ 718 V(vesrl, VESRL, \ 719 0xE738) /* type = VRS_A VECTOR ELEMENT SHIFT RIGHT LOGICAL */ \ 720 V(vesra, VESRA, \ 721 0xE73A) /* type = VRS_A VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */ \ 722 V(vstm, VSTM, 0xE73E) /* type = VRS_A VECTOR STORE MULTIPLE */ 723 724 #define S390_RIL_A_OPCODE_LIST(V) \ 725 V(lgfi, LGFI, 0xC01) /* type = RIL_A LOAD IMMEDIATE (64<-32) */ \ 726 V(xihf, XIHF, 0xC06) /* type = RIL_A EXCLUSIVE OR IMMEDIATE (high) */ \ 727 V(xilf, XILF, 0xC07) /* type = RIL_A EXCLUSIVE OR IMMEDIATE (low) */ \ 728 V(iihf, IIHF, 0xC08) /* type = RIL_A INSERT IMMEDIATE (high) */ \ 729 V(iilf, IILF, 0xC09) /* type = RIL_A INSERT IMMEDIATE (low) */ \ 730 V(nihf, NIHF, 0xC0A) /* type = RIL_A AND IMMEDIATE (high) */ \ 731 V(nilf, NILF, 0xC0B) /* type = RIL_A AND IMMEDIATE (low) */ \ 732 V(oihf, OIHF, 0xC0C) /* type = RIL_A OR IMMEDIATE (high) */ \ 733 V(oilf, OILF, 0xC0D) /* type = RIL_A OR IMMEDIATE (low) */ \ 734 V(llihf, LLIHF, 0xC0E) /* type = RIL_A LOAD LOGICAL IMMEDIATE (high) */ \ 735 V(llilf, LLILF, 0xC0F) /* type = RIL_A LOAD LOGICAL IMMEDIATE (low) */ \ 736 V(msgfi, MSGFI, 0xC20) /* type = RIL_A MULTIPLY SINGLE IMMEDIATE (64<-32) */ \ 737 V(msfi, MSFI, 0xC21) /* type = RIL_A MULTIPLY SINGLE IMMEDIATE (32) */ \ 738 V(slgfi, SLGFI, \ 739 0xC24) /* type = RIL_A SUBTRACT LOGICAL IMMEDIATE (64<-32) */ \ 740 V(slfi, SLFI, 0xC25) /* type = RIL_A SUBTRACT LOGICAL IMMEDIATE (32) */ \ 741 V(agfi, AGFI, 0xC28) /* type = RIL_A ADD IMMEDIATE (64<-32) */ \ 742 V(afi, AFI, 0xC29) /* type = RIL_A ADD IMMEDIATE (32) */ \ 743 V(algfi, ALGFI, 0xC2A) /* type = RIL_A ADD LOGICAL IMMEDIATE (64<-32) */ \ 744 V(alfi, ALFI, 0xC2B) /* type = RIL_A ADD LOGICAL IMMEDIATE (32) */ \ 745 V(cgfi, CGFI, 0xC2C) /* type = RIL_A COMPARE IMMEDIATE (64<-32) */ \ 746 V(cfi, CFI, 0xC2D) /* type = RIL_A COMPARE IMMEDIATE (32) */ \ 747 V(clgfi, CLGFI, 0xC2E) /* type = RIL_A COMPARE LOGICAL IMMEDIATE (64<-32) */ \ 748 V(clfi, CLFI, 0xC2F) /* type = RIL_A COMPARE LOGICAL IMMEDIATE (32) */ \ 749 V(aih, AIH, 0xCC8) /* type = RIL_A ADD IMMEDIATE HIGH (32) */ \ 750 V(alsih, ALSIH, \ 751 0xCCA) /* type = RIL_A ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) */ \ 752 V(alsihn, ALSIHN, \ 753 0xCCB) /* type = RIL_A ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) */ \ 754 V(cih, CIH, 0xCCD) /* type = RIL_A COMPARE IMMEDIATE HIGH (32) */ \ 755 V(clih, CLIH, 0xCCF) /* type = RIL_A COMPARE LOGICAL IMMEDIATE HIGH (32) */ 756 757 #define S390_RIL_B_OPCODE_LIST(V) \ 758 V(larl, LARL, 0xC00) /* type = RIL_B LOAD ADDRESS RELATIVE LONG */ \ 759 V(brasl, BRASL, 0xC05) /* type = RIL_B BRANCH RELATIVE AND SAVE LONG */ \ 760 V(llhrl, LLHRL, \ 761 0xC42) /* type = RIL_B LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) */ \ 762 V(lghrl, LGHRL, \ 763 0xC44) /* type = RIL_B LOAD HALFWORD RELATIVE LONG (64<-16) */ \ 764 V(lhrl, LHRL, 0xC45) /* type = RIL_B LOAD HALFWORD RELATIVE LONG (32<-16) */ \ 765 V(llghrl, LLGHRL, \ 766 0xC46) /* type = RIL_B LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) */ \ 767 V(sthrl, STHRL, 0xC47) /* type = RIL_B STORE HALFWORD RELATIVE LONG (16) */ \ 768 V(lgrl, LGRL, 0xC48) /* type = RIL_B LOAD RELATIVE LONG (64) */ \ 769 V(stgrl, STGRL, 0xC4B) /* type = RIL_B STORE RELATIVE LONG (64) */ \ 770 V(lgfrl, LGFRL, 0xC4C) /* type = RIL_B LOAD RELATIVE LONG (64<-32) */ \ 771 V(lrl, LRL, 0xC4D) /* type = RIL_B LOAD RELATIVE LONG (32) */ \ 772 V(llgfrl, LLGFRL, \ 773 0xC4E) /* type = RIL_B LOAD LOGICAL RELATIVE LONG (64<-32) */ \ 774 V(strl, STRL, 0xC4F) /* type = RIL_B STORE RELATIVE LONG (32) */ \ 775 V(exrl, EXRL, 0xC60) /* type = RIL_B EXECUTE RELATIVE LONG */ \ 776 V(cghrl, CGHRL, \ 777 0xC64) /* type = RIL_B COMPARE HALFWORD RELATIVE LONG (64<-16) */ \ 778 V(chrl, CHRL, \ 779 0xC65) /* type = RIL_B COMPARE HALFWORD RELATIVE LONG (32<-16) */ \ 780 V(clghrl, CLGHRL, \ 781 0xC66) /* type = RIL_B COMPARE LOGICAL RELATIVE LONG (64<-16) */ \ 782 V(clhrl, CLHRL, \ 783 0xC67) /* type = RIL_B COMPARE LOGICAL RELATIVE LONG (32<-16) */ \ 784 V(cgrl, CGRL, 0xC68) /* type = RIL_B COMPARE RELATIVE LONG (64) */ \ 785 V(clgrl, CLGRL, 0xC6A) /* type = RIL_B COMPARE LOGICAL RELATIVE LONG (64) */ \ 786 V(cgfrl, CGFRL, 0xC6C) /* type = RIL_B COMPARE RELATIVE LONG (64<-32) */ \ 787 V(crl, CRL, 0xC6D) /* type = RIL_B COMPARE RELATIVE LONG (32) */ \ 788 V(clgfrl, CLGFRL, \ 789 0xC6E) /* type = RIL_B COMPARE LOGICAL RELATIVE LONG (64<-32) */ \ 790 V(clrl, CLRL, 0xC6F) /* type = RIL_B COMPARE LOGICAL RELATIVE LONG (32) */ \ 791 V(brcth, BRCTH, 0xCC6) /* type = RIL_B BRANCH RELATIVE ON COUNT HIGH (32) */ 792 793 #define S390_VRS_B_OPCODE_LIST(V) \ 794 V(vlvg, VLVG, 0xE722) /* type = VRS_B VECTOR LOAD VR ELEMENT FROM GR */ \ 795 V(vll, VLL, 0xE737) /* type = VRS_B VECTOR LOAD WITH LENGTH */ \ 796 V(vstl, VSTL, 0xE73F) /* type = VRS_B VECTOR STORE WITH LENGTH */ 797 798 #define S390_RIL_C_OPCODE_LIST(V) \ 799 V(brcl, BRCL, 0xC04) /* type = RIL_C BRANCH RELATIVE ON CONDITION LONG */ \ 800 V(pfdrl, PFDRL, 0xC62) /* type = RIL_C PREFETCH DATA RELATIVE LONG */ 801 802 #define S390_VRS_C_OPCODE_LIST(V) \ 803 V(vlgv, VLGV, 0xE721) /* type = VRS_C VECTOR LOAD GR FROM VR ELEMENT */ 804 805 #define S390_RI_A_OPCODE_LIST(V) \ 806 V(iihh, IIHH, 0xA50) /* type = RI_A INSERT IMMEDIATE (high high) */ \ 807 V(iihl, IIHL, 0xA51) /* type = RI_A INSERT IMMEDIATE (high low) */ \ 808 V(iilh, IILH, 0xA52) /* type = RI_A INSERT IMMEDIATE (low high) */ \ 809 V(iill, IILL, 0xA53) /* type = RI_A INSERT IMMEDIATE (low low) */ \ 810 V(nihh, NIHH, 0xA54) /* type = RI_A AND IMMEDIATE (high high) */ \ 811 V(nihl, NIHL, 0xA55) /* type = RI_A AND IMMEDIATE (high low) */ \ 812 V(nilh, NILH, 0xA56) /* type = RI_A AND IMMEDIATE (low high) */ \ 813 V(nill, NILL, 0xA57) /* type = RI_A AND IMMEDIATE (low low) */ \ 814 V(oihh, OIHH, 0xA58) /* type = RI_A OR IMMEDIATE (high high) */ \ 815 V(oihl, OIHL, 0xA59) /* type = RI_A OR IMMEDIATE (high low) */ \ 816 V(oilh, OILH, 0xA5A) /* type = RI_A OR IMMEDIATE (low high) */ \ 817 V(oill, OILL, 0xA5B) /* type = RI_A OR IMMEDIATE (low low) */ \ 818 V(llihh, LLIHH, 0xA5C) /* type = RI_A LOAD LOGICAL IMMEDIATE (high high) */ \ 819 V(llihl, LLIHL, 0xA5D) /* type = RI_A LOAD LOGICAL IMMEDIATE (high low) */ \ 820 V(llilh, LLILH, 0xA5E) /* type = RI_A LOAD LOGICAL IMMEDIATE (low high) */ \ 821 V(llill, LLILL, 0xA5F) /* type = RI_A LOAD LOGICAL IMMEDIATE (low low) */ \ 822 V(tmlh, TMLH, 0xA70) /* type = RI_A TEST UNDER MASK (low high) */ \ 823 V(tmh, TMH, 0xA70) /* type = RI_A TEST UNDER MASK HIGH */ \ 824 V(tmll, TMLL, 0xA71) /* type = RI_A TEST UNDER MASK (low low) */ \ 825 V(tml, TML, 0xA71) /* type = RI_A TEST UNDER MASK LOW */ \ 826 V(tmhh, TMHH, 0xA72) /* type = RI_A TEST UNDER MASK (high high) */ \ 827 V(tmhl, TMHL, 0xA73) /* type = RI_A TEST UNDER MASK (high low) */ \ 828 V(lhi, LHI, 0xA78) /* type = RI_A LOAD HALFWORD IMMEDIATE (32)<-16 */ \ 829 V(lghi, LGHI, 0xA79) /* type = RI_A LOAD HALFWORD IMMEDIATE (64<-16) */ \ 830 V(ahi, AHI, 0xA7A) /* type = RI_A ADD HALFWORD IMMEDIATE (32<-16) */ \ 831 V(aghi, AGHI, 0xA7B) /* type = RI_A ADD HALFWORD IMMEDIATE (64<-16) */ \ 832 V(mhi, MHI, 0xA7C) /* type = RI_A MULTIPLY HALFWORD IMMEDIATE (32<-16) */ \ 833 V(mghi, MGHI, 0xA7D) /* type = RI_A MULTIPLY HALFWORD IMMEDIATE (64<-16) */ \ 834 V(chi, CHI, 0xA7E) /* type = RI_A COMPARE HALFWORD IMMEDIATE (32<-16) */ \ 835 V(cghi, CGHI, 0xA7F) /* type = RI_A COMPARE HALFWORD IMMEDIATE (64<-16) */ 836 837 #define S390_RSI_OPCODE_LIST(V) \ 838 V(brxh, BRXH, 0x84) /* type = RSI BRANCH RELATIVE ON INDEX HIGH (32) */ \ 839 V(brxle, BRXLE, \ 840 0x85) /* type = RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) */ 841 842 #define S390_RI_B_OPCODE_LIST(V) \ 843 V(bras, BRAS, 0xA75) /* type = RI_B BRANCH RELATIVE AND SAVE */ \ 844 V(brct, BRCT, 0xA76) /* type = RI_B BRANCH RELATIVE ON COUNT (32) */ \ 845 V(brctg, BRCTG, 0xA77) /* type = RI_B BRANCH RELATIVE ON COUNT (64) */ 846 847 #define S390_RI_C_OPCODE_LIST(V) \ 848 V(brc, BRC, 0xA74) /* type = RI_C BRANCH RELATIVE ON CONDITION */ 849 850 #define S390_RSL_OPCODE_LIST(V) \ 851 V(czdt, CZDT, 0xEDA8) /* type = RSL CONVERT TO ZONED (from long DFP) */ \ 852 V(czxt, CZXT, 0xEDA9) /* type = RSL CONVERT TO ZONED (from extended DFP) */ \ 853 V(cdzt, CDZT, 0xEDAA) /* type = RSL CONVERT FROM ZONED (to long DFP) */ \ 854 V(cxzt, CXZT, 0xEDAB) /* type = RSL CONVERT FROM ZONED (to extended DFP) */ 855 856 #define S390_SMI_OPCODE_LIST(V) \ 857 V(bpp, BPP, 0xC7) /* type = SMI BRANCH PREDICTION PRELOAD */ 858 859 #define S390_RXY_A_OPCODE_LIST(V) \ 860 V(ltg, LTG, 0xE302) /* type = RXY_A LOAD AND TEST (64) */ \ 861 V(lrag, LRAG, 0xE303) /* type = RXY_A LOAD REAL ADDRESS (64) */ \ 862 V(lg, LG, 0xE304) /* type = RXY_A LOAD (64) */ \ 863 V(cvby, CVBY, 0xE306) /* type = RXY_A CONVERT TO BINARY (32) */ \ 864 V(ag, AG, 0xE308) /* type = RXY_A ADD (64) */ \ 865 V(sg, SG, 0xE309) /* type = RXY_A SUBTRACT (64) */ \ 866 V(alg, ALG, 0xE30A) /* type = RXY_A ADD LOGICAL (64) */ \ 867 V(slg, SLG, 0xE30B) /* type = RXY_A SUBTRACT LOGICAL (64) */ \ 868 V(msg, MSG, 0xE30C) /* type = RXY_A MULTIPLY SINGLE (64) */ \ 869 V(dsg, DSG, 0xE30D) /* type = RXY_A DIVIDE SINGLE (64) */ \ 870 V(cvbg, CVBG, 0xE30E) /* type = RXY_A CONVERT TO BINARY (64) */ \ 871 V(lrvg, LRVG, 0xE30F) /* type = RXY_A LOAD REVERSED (64) */ \ 872 V(lt_z, LT, 0xE312) /* type = RXY_A LOAD AND TEST (32) */ \ 873 V(lray, LRAY, 0xE313) /* type = RXY_A LOAD REAL ADDRESS (32) */ \ 874 V(lgf, LGF, 0xE314) /* type = RXY_A LOAD (64<-32) */ \ 875 V(lgh, LGH, 0xE315) /* type = RXY_A LOAD HALFWORD (64<-16) */ \ 876 V(llgf, LLGF, 0xE316) /* type = RXY_A LOAD LOGICAL (64<-32) */ \ 877 V(llgt, LLGT, \ 878 0xE317) /* type = RXY_A LOAD LOGICAL THIRTY ONE BITS (64<-31) */ \ 879 V(agf, AGF, 0xE318) /* type = RXY_A ADD (64<-32) */ \ 880 V(sgf, SGF, 0xE319) /* type = RXY_A SUBTRACT (64<-32) */ \ 881 V(algf, ALGF, 0xE31A) /* type = RXY_A ADD LOGICAL (64<-32) */ \ 882 V(slgf, SLGF, 0xE31B) /* type = RXY_A SUBTRACT LOGICAL (64<-32) */ \ 883 V(msgf, MSGF, 0xE31C) /* type = RXY_A MULTIPLY SINGLE (64<-32) */ \ 884 V(dsgf, DSGF, 0xE31D) /* type = RXY_A DIVIDE SINGLE (64<-32) */ \ 885 V(lrv, LRV, 0xE31E) /* type = RXY_A LOAD REVERSED (32) */ \ 886 V(lrvh, LRVH, 0xE31F) /* type = RXY_A LOAD REVERSED (16) */ \ 887 V(cg, CG, 0xE320) /* type = RXY_A COMPARE (64) */ \ 888 V(clg, CLG, 0xE321) /* type = RXY_A COMPARE LOGICAL (64) */ \ 889 V(stg, STG, 0xE324) /* type = RXY_A STORE (64) */ \ 890 V(ntstg, NTSTG, 0xE325) /* type = RXY_A NONTRANSACTIONAL STORE (64) */ \ 891 V(cvdy, CVDY, 0xE326) /* type = RXY_A CONVERT TO DECIMAL (32) */ \ 892 V(lzrg, LZRG, 0xE32A) /* type = RXY_A LOAD AND ZERO RIGHTMOST BYTE (64) */ \ 893 V(cvdg, CVDG, 0xE32E) /* type = RXY_A CONVERT TO DECIMAL (64) */ \ 894 V(strvg, STRVG, 0xE32F) /* type = RXY_A STORE REVERSED (64) */ \ 895 V(cgf, CGF, 0xE330) /* type = RXY_A COMPARE (64<-32) */ \ 896 V(clgf, CLGF, 0xE331) /* type = RXY_A COMPARE LOGICAL (64<-32) */ \ 897 V(ltgf, LTGF, 0xE332) /* type = RXY_A LOAD AND TEST (64<-32) */ \ 898 V(cgh, CGH, 0xE334) /* type = RXY_A COMPARE HALFWORD (64<-16) */ \ 899 V(llzrgf, LLZRGF, \ 900 0xE33A) /* type = RXY_A LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64<-32) */ \ 901 V(lzrf, LZRF, 0xE33B) /* type = RXY_A LOAD AND ZERO RIGHTMOST BYTE (32) */ \ 902 V(strv, STRV, 0xE33E) /* type = RXY_A STORE REVERSED (32) */ \ 903 V(strvh, STRVH, 0xE33F) /* type = RXY_A STORE REVERSED (16) */ \ 904 V(bctg, BCTG, 0xE346) /* type = RXY_A BRANCH ON COUNT (64) */ \ 905 V(sty, STY, 0xE350) /* type = RXY_A STORE (32) */ \ 906 V(msy, MSY, 0xE351) /* type = RXY_A MULTIPLY SINGLE (32) */ \ 907 V(ny, NY, 0xE354) /* type = RXY_A AND (32) */ \ 908 V(cly, CLY, 0xE355) /* type = RXY_A COMPARE LOGICAL (32) */ \ 909 V(oy, OY, 0xE356) /* type = RXY_A OR (32) */ \ 910 V(xy, XY, 0xE357) /* type = RXY_A EXCLUSIVE OR (32) */ \ 911 V(ly, LY, 0xE358) /* type = RXY_A LOAD (32) */ \ 912 V(cy, CY, 0xE359) /* type = RXY_A COMPARE (32) */ \ 913 V(ay, AY, 0xE35A) /* type = RXY_A ADD (32) */ \ 914 V(sy, SY, 0xE35B) /* type = RXY_A SUBTRACT (32) */ \ 915 V(mfy, MFY, 0xE35C) /* type = RXY_A MULTIPLY (64<-32) */ \ 916 V(aly, ALY, 0xE35E) /* type = RXY_A ADD LOGICAL (32) */ \ 917 V(sly, SLY, 0xE35F) /* type = RXY_A SUBTRACT LOGICAL (32) */ \ 918 V(sthy, STHY, 0xE370) /* type = RXY_A STORE HALFWORD (16) */ \ 919 V(lay, LAY, 0xE371) /* type = RXY_A LOAD ADDRESS */ \ 920 V(stcy, STCY, 0xE372) /* type = RXY_A STORE CHARACTER */ \ 921 V(icy, ICY, 0xE373) /* type = RXY_A INSERT CHARACTER */ \ 922 V(laey, LAEY, 0xE375) /* type = RXY_A LOAD ADDRESS EXTENDED */ \ 923 V(lb, LB, 0xE376) /* type = RXY_A LOAD BYTE (32<-8) */ \ 924 V(lgb, LGB, 0xE377) /* type = RXY_A LOAD BYTE (64<-8) */ \ 925 V(lhy, LHY, 0xE378) /* type = RXY_A LOAD HALFWORD (32)<-16 */ \ 926 V(chy, CHY, 0xE379) /* type = RXY_A COMPARE HALFWORD (32<-16) */ \ 927 V(ahy, AHY, 0xE37A) /* type = RXY_A ADD HALFWORD (32<-16) */ \ 928 V(shy, SHY, 0xE37B) /* type = RXY_A SUBTRACT HALFWORD (32<-16) */ \ 929 V(mhy, MHY, 0xE37C) /* type = RXY_A MULTIPLY HALFWORD (32<-16) */ \ 930 V(ng, NG, 0xE380) /* type = RXY_A AND (64) */ \ 931 V(og, OG, 0xE381) /* type = RXY_A OR (64) */ \ 932 V(xg, XG, 0xE382) /* type = RXY_A EXCLUSIVE OR (64) */ \ 933 V(lgat, LGAT, 0xE385) /* type = RXY_A LOAD AND TRAP (64) */ \ 934 V(mlg, MLG, 0xE386) /* type = RXY_A MULTIPLY LOGICAL (128<-64) */ \ 935 V(dlg, DLG, 0xE387) /* type = RXY_A DIVIDE LOGICAL (64<-128) */ \ 936 V(alcg, ALCG, 0xE388) /* type = RXY_A ADD LOGICAL WITH CARRY (64) */ \ 937 V(slbg, SLBG, 0xE389) /* type = RXY_A SUBTRACT LOGICAL WITH BORROW (64) */ \ 938 V(stpq, STPQ, 0xE38E) /* type = RXY_A STORE PAIR TO QUADWORD */ \ 939 V(lpq, LPQ, 0xE38F) /* type = RXY_A LOAD PAIR FROM QUADWORD (64&64<-128) */ \ 940 V(llgc, LLGC, 0xE390) /* type = RXY_A LOAD LOGICAL CHARACTER (64<-8) */ \ 941 V(llgh, LLGH, 0xE391) /* type = RXY_A LOAD LOGICAL HALFWORD (64<-16) */ \ 942 V(llc, LLC, 0xE394) /* type = RXY_A LOAD LOGICAL CHARACTER (32<-8) */ \ 943 V(llh, LLH, 0xE395) /* type = RXY_A LOAD LOGICAL HALFWORD (32<-16) */ \ 944 V(ml, ML, 0xE396) /* type = RXY_A MULTIPLY LOGICAL (64<-32) */ \ 945 V(dl, DL, 0xE397) /* type = RXY_A DIVIDE LOGICAL (32<-64) */ \ 946 V(alc, ALC, 0xE398) /* type = RXY_A ADD LOGICAL WITH CARRY (32) */ \ 947 V(slb, SLB, 0xE399) /* type = RXY_A SUBTRACT LOGICAL WITH BORROW (32) */ \ 948 V(llgtat, LLGTAT, \ 949 0xE39C) /* type = RXY_A LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) */ \ 950 V(llgfat, LLGFAT, 0xE39D) /* type = RXY_A LOAD LOGICAL AND TRAP (64<-32) */ \ 951 V(lat, LAT, 0xE39F) /* type = RXY_A LOAD AND TRAP (32L<-32) */ \ 952 V(lbh, LBH, 0xE3C0) /* type = RXY_A LOAD BYTE HIGH (32<-8) */ \ 953 V(llch, LLCH, 0xE3C2) /* type = RXY_A LOAD LOGICAL CHARACTER HIGH (32<-8) */ \ 954 V(stch, STCH, 0xE3C3) /* type = RXY_A STORE CHARACTER HIGH (8) */ \ 955 V(lhh, LHH, 0xE3C4) /* type = RXY_A LOAD HALFWORD HIGH (32<-16) */ \ 956 V(llhh, LLHH, 0xE3C6) /* type = RXY_A LOAD LOGICAL HALFWORD HIGH (32<-16) */ \ 957 V(sthh, STHH, 0xE3C7) /* type = RXY_A STORE HALFWORD HIGH (16) */ \ 958 V(lfhat, LFHAT, 0xE3C8) /* type = RXY_A LOAD HIGH AND TRAP (32H<-32) */ \ 959 V(lfh, LFH, 0xE3CA) /* type = RXY_A LOAD HIGH (32) */ \ 960 V(stfh, STFH, 0xE3CB) /* type = RXY_A STORE HIGH (32) */ \ 961 V(chf, CHF, 0xE3CD) /* type = RXY_A COMPARE HIGH (32) */ \ 962 V(clhf, CLHF, 0xE3CF) /* type = RXY_A COMPARE LOGICAL HIGH (32) */ \ 963 V(ley, LEY, 0xED64) /* type = RXY_A LOAD (short) */ \ 964 V(ldy, LDY, 0xED65) /* type = RXY_A LOAD (long) */ \ 965 V(stey, STEY, 0xED66) /* type = RXY_A STORE (short) */ \ 966 V(stdy, STDY, 0xED67) /* type = RXY_A STORE (long) */ 967 968 #define S390_RXY_B_OPCODE_LIST(V) \ 969 V(pfd, PFD, 0xE336) /* type = RXY_B PREFETCH DATA */ 970 971 #define S390_SIY_OPCODE_LIST(V) \ 972 V(tmy, TMY, 0xEB51) /* type = SIY TEST UNDER MASK */ \ 973 V(mviy, MVIY, 0xEB52) /* type = SIY MOVE (immediate) */ \ 974 V(niy, NIY, 0xEB54) /* type = SIY AND (immediate) */ \ 975 V(cliy, CLIY, 0xEB55) /* type = SIY COMPARE LOGICAL (immediate) */ \ 976 V(oiy, OIY, 0xEB56) /* type = SIY OR (immediate) */ \ 977 V(xiy, XIY, 0xEB57) /* type = SIY EXCLUSIVE OR (immediate) */ \ 978 V(asi, ASI, 0xEB6A) /* type = SIY ADD IMMEDIATE (32<-8) */ \ 979 V(alsi, ALSI, \ 980 0xEB6E) /* type = SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) */ \ 981 V(agsi, AGSI, 0xEB7A) /* type = SIY ADD IMMEDIATE (64<-8) */ \ 982 V(algsi, ALGSI, \ 983 0xEB7E) /* type = SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) */ 984 985 #define S390_SS_A_OPCODE_LIST(V) \ 986 V(trtr, TRTR, 0xD0) /* type = SS_A TRANSLATE AND TEST REVERSE */ \ 987 V(mvn, MVN, 0xD1) /* type = SS_A MOVE NUMERICS */ \ 988 V(mvc, MVC, 0xD2) /* type = SS_A MOVE (character) */ \ 989 V(mvz, MVZ, 0xD3) /* type = SS_A MOVE ZONES */ \ 990 V(nc, NC, 0xD4) /* type = SS_A AND (character) */ \ 991 V(clc, CLC, 0xD5) /* type = SS_A COMPARE LOGICAL (character) */ \ 992 V(oc, OC, 0xD6) /* type = SS_A OR (character) */ \ 993 V(xc, XC, 0xD7) /* type = SS_A EXCLUSIVE OR (character) */ \ 994 V(tr, TR, 0xDC) /* type = SS_A TRANSLATE */ \ 995 V(trt, TRT, 0xDD) /* type = SS_A TRANSLATE AND TEST */ \ 996 V(ed, ED, 0xDE) /* type = SS_A EDIT */ \ 997 V(edmk, EDMK, 0xDF) /* type = SS_A EDIT AND MARK */ \ 998 V(unpku, UNPKU, 0xE2) /* type = SS_A UNPACK UNICODE */ \ 999 V(mvcin, MVCIN, 0xE8) /* type = SS_A MOVE INVERSE */ \ 1000 V(unpka, UNPKA, 0xEA) /* type = SS_A UNPACK ASCII */ 1001 1002 #define S390_E_OPCODE_LIST(V) \ 1003 V(pr, PR, 0x0101) /* type = E PROGRAM RETURN */ \ 1004 V(upt, UPT, 0x0102) /* type = E UPDATE TREE */ \ 1005 V(ptff, PTFF, 0x0104) /* type = E PERFORM TIMING FACILITY FUNCTION */ \ 1006 V(sckpf, SCKPF, 0x0107) /* type = E SET CLOCK PROGRAMMABLE FIELD */ \ 1007 V(pfpo, PFPO, 0x010A) /* type = E PERFORM FLOATING-POINT OPERATION */ \ 1008 V(tam, TAM, 0x010B) /* type = E TEST ADDRESSING MODE */ \ 1009 V(sam24, SAM24, 0x010C) /* type = E SET ADDRESSING MODE (24) */ \ 1010 V(sam31, SAM31, 0x010D) /* type = E SET ADDRESSING MODE (31) */ \ 1011 V(sam64, SAM64, 0x010E) /* type = E SET ADDRESSING MODE (64) */ \ 1012 V(trap2, TRAP2, 0x01FF) /* type = E TRAP */ 1013 1014 #define S390_SS_B_OPCODE_LIST(V) \ 1015 V(mvo, MVO, 0xF1) /* type = SS_B MOVE WITH OFFSET */ \ 1016 V(pack, PACK, 0xF2) /* type = SS_B PACK */ \ 1017 V(unpk, UNPK, 0xF3) /* type = SS_B UNPACK */ \ 1018 V(zap, ZAP, 0xF8) /* type = SS_B ZERO AND ADD */ \ 1019 V(cp, CP, 0xF9) /* type = SS_B COMPARE DECIMAL */ \ 1020 V(ap, AP, 0xFA) /* type = SS_B ADD DECIMAL */ \ 1021 V(sp, SP, 0xFB) /* type = SS_B SUBTRACT DECIMAL */ \ 1022 V(mp, MP, 0xFC) /* type = SS_B MULTIPLY DECIMAL */ \ 1023 V(dp, DP, 0xFD) /* type = SS_B DIVIDE DECIMAL */ 1024 1025 #define S390_SS_C_OPCODE_LIST(V) \ 1026 V(srp, SRP, 0xF0) /* type = SS_C SHIFT AND ROUND DECIMAL */ 1027 1028 #define S390_SS_D_OPCODE_LIST(V) \ 1029 V(mvck, MVCK, 0xD9) /* type = SS_D MOVE WITH KEY */ \ 1030 V(mvcp, MVCP, 0xDA) /* type = SS_D MOVE TO PRIMARY */ \ 1031 V(mvcs, MVCS, 0xDB) /* type = SS_D MOVE TO SECONDARY */ 1032 1033 #define S390_SS_E_OPCODE_LIST(V) \ 1034 V(plo, PLO, 0xEE) /* type = SS_E PERFORM LOCKED OPERATION */ \ 1035 V(lmd, LMD, 0xEF) /* type = SS_E LOAD MULTIPLE DISJOINT (64<-32&32) */ 1036 1037 #define S390_I_OPCODE_LIST(V) \ 1038 V(svc, SVC, 0x0A) /* type = I SUPERVISOR CALL */ 1039 1040 #define S390_SS_F_OPCODE_LIST(V) \ 1041 V(pku, PKU, 0xE1) /* type = SS_F PACK UNICODE */ \ 1042 V(pka, PKA, 0xE9) /* type = SS_F PACK ASCII */ 1043 1044 #define S390_SSE_OPCODE_LIST(V) \ 1045 V(lasp, LASP, 0xE500) /* type = SSE LOAD ADDRESS SPACE PARAMETERS */ \ 1046 V(tprot, TPROT, 0xE501) /* type = SSE TEST PROTECTION */ \ 1047 V(strag, STRAG, 0xE502) /* type = SSE STORE REAL ADDRESS */ \ 1048 V(mvcsk, MVCSK, 0xE50E) /* type = SSE MOVE WITH SOURCE KEY */ \ 1049 V(mvcdk, MVCDK, 0xE50F) /* type = SSE MOVE WITH DESTINATION KEY */ 1050 1051 #define S390_SSF_OPCODE_LIST(V) \ 1052 V(mvcos, MVCOS, 0xC80) /* type = SSF MOVE WITH OPTIONAL SPECIFICATIONS */ \ 1053 V(ectg, ECTG, 0xC81) /* type = SSF EXTRACT CPU TIME */ \ 1054 V(csst, CSST, 0xC82) /* type = SSF COMPARE AND SWAP AND STORE */ \ 1055 V(lpd, LPD, 0xC84) /* type = SSF LOAD PAIR DISJOINT (32) */ \ 1056 V(lpdg, LPDG, 0xC85) /* type = SSF LOAD PAIR DISJOINT (64) */ 1057 1058 #define S390_RS_A_OPCODE_LIST(V) \ 1059 V(bxh, BXH, 0x86) /* type = RS_A BRANCH ON INDEX HIGH (32) */ \ 1060 V(bxle, BXLE, 0x87) /* type = RS_A BRANCH ON INDEX LOW OR EQUAL (32) */ \ 1061 V(srl, SRL, 0x88) /* type = RS_A SHIFT RIGHT SINGLE LOGICAL (32) */ \ 1062 V(sll, SLL, 0x89) /* type = RS_A SHIFT LEFT SINGLE LOGICAL (32) */ \ 1063 V(sra, SRA, 0x8A) /* type = RS_A SHIFT RIGHT SINGLE (32) */ \ 1064 V(sla, SLA, 0x8B) /* type = RS_A SHIFT LEFT SINGLE (32) */ \ 1065 V(srdl, SRDL, 0x8C) /* type = RS_A SHIFT RIGHT DOUBLE LOGICAL (64) */ \ 1066 V(sldl, SLDL, 0x8D) /* type = RS_A SHIFT LEFT DOUBLE LOGICAL (64) */ \ 1067 V(srda, SRDA, 0x8E) /* type = RS_A SHIFT RIGHT DOUBLE (64) */ \ 1068 V(slda, SLDA, 0x8F) /* type = RS_A SHIFT LEFT DOUBLE (64) */ \ 1069 V(stm, STM, 0x90) /* type = RS_A STORE MULTIPLE (32) */ \ 1070 V(lm, LM, 0x98) /* type = RS_A LOAD MULTIPLE (32) */ \ 1071 V(trace, TRACE, 0x99) /* type = RS_A TRACE (32) */ \ 1072 V(lam, LAM, 0x9A) /* type = RS_A LOAD ACCESS MULTIPLE */ \ 1073 V(stam, STAM, 0x9B) /* type = RS_A STORE ACCESS MULTIPLE */ \ 1074 V(mvcle, MVCLE, 0xA8) /* type = RS_A MOVE LONG EXTENDED */ \ 1075 V(clcle, CLCLE, 0xA9) /* type = RS_A COMPARE LOGICAL LONG EXTENDED */ \ 1076 V(sigp, SIGP, 0xAE) /* type = RS_A SIGNAL PROCESSOR */ \ 1077 V(stctl, STCTL, 0xB6) /* type = RS_A STORE CONTROL (32) */ \ 1078 V(lctl, LCTL, 0xB7) /* type = RS_A LOAD CONTROL (32) */ \ 1079 V(cs, CS, 0xBA) /* type = RS_A COMPARE AND SWAP (32) */ \ 1080 V(cds, CDS, 0xBB) /* type = RS_A COMPARE DOUBLE AND SWAP (32) */ 1081 1082 #define S390_RS_B_OPCODE_LIST(V) \ 1083 V(clm, CLM, 0xBD) /* type = RS_B COMPARE LOGICAL CHAR. UNDER MASK (low) */ \ 1084 V(stcm, STCM, 0xBE) /* type = RS_B STORE CHARACTERS UNDER MASK (low) */ \ 1085 V(icm, ICM, 0xBF) /* type = RS_B INSERT CHARACTERS UNDER MASK (low) */ 1086 1087 #define S390_S_OPCODE_LIST(V) \ 1088 V(awr, AWR, 0x2E) /* type = S ADD UNNORMALIZED (long HFP) */ \ 1089 V(lpsw, LPSW, 0x82) /* type = S LOAD PSW */ \ 1090 V(diagnose, DIAGNOSE, 0x83) /* type = S DIAGNOSE */ \ 1091 V(ts, TS, 0x93) /* type = S TEST AND SET */ \ 1092 V(stidp, STIDP, 0xB202) /* type = S STORE CPU ID */ \ 1093 V(sck, SCK, 0xB204) /* type = S SET CLOCK */ \ 1094 V(stck, STCK, 0xB205) /* type = S STORE CLOCK */ \ 1095 V(sckc, SCKC, 0xB206) /* type = S SET CLOCK COMPARATOR */ \ 1096 V(stckc, STCKC, 0xB207) /* type = S STORE CLOCK COMPARATOR */ \ 1097 V(spt, SPT, 0xB208) /* type = S SET CPU TIMER */ \ 1098 V(stpt, STPT, 0xB209) /* type = S STORE CPU TIMER */ \ 1099 V(spka, SPKA, 0xB20A) /* type = S SET PSW KEY FROM ADDRESS */ \ 1100 V(ipk, IPK, 0xB20B) /* type = S INSERT PSW KEY */ \ 1101 V(ptlb, PTLB, 0xB20D) /* type = S PURGE TLB */ \ 1102 V(spx, SPX, 0xB210) /* type = S SET PREFIX */ \ 1103 V(stpx, STPX, 0xB211) /* type = S STORE PREFIX */ \ 1104 V(stap, STAP, 0xB212) /* type = S STORE CPU ADDRESS */ \ 1105 V(pc, PC, 0xB218) /* type = S PROGRAM CALL */ \ 1106 V(sac, SAC, 0xB219) /* type = S SET ADDRESS SPACE CONTROL */ \ 1107 V(cfc, CFC, 0xB21A) /* type = S COMPARE AND FORM CODEWORD */ \ 1108 V(csch, CSCH, 0xB230) /* type = S CLEAR SUBCHANNEL */ \ 1109 V(hsch, HSCH, 0xB231) /* type = S HALT SUBCHANNEL */ \ 1110 V(msch, MSCH, 0xB232) /* type = S MODIFY SUBCHANNEL */ \ 1111 V(ssch, SSCH, 0xB233) /* type = S START SUBCHANNEL */ \ 1112 V(stsch, STSCH, 0xB234) /* type = S STORE SUBCHANNEL */ \ 1113 V(tsch, TSCH, 0xB235) /* type = S TEST SUBCHANNEL */ \ 1114 V(tpi, TPI, 0xB236) /* type = S TEST PENDING INTERRUPTION */ \ 1115 V(sal, SAL, 0xB237) /* type = S SET ADDRESS LIMIT */ \ 1116 V(rsch, RSCH, 0xB238) /* type = S RESUME SUBCHANNEL */ \ 1117 V(stcrw, STCRW, 0xB239) /* type = S STORE CHANNEL REPORT WORD */ \ 1118 V(stcps, STCPS, 0xB23A) /* type = S STORE CHANNEL PATH STATUS */ \ 1119 V(rchp, RCHP, 0xB23B) /* type = S RESET CHANNEL PATH */ \ 1120 V(schm, SCHM, 0xB23C) /* type = S SET CHANNEL MONITOR */ \ 1121 V(xsch, XSCH, 0xB276) /* type = S CANCEL SUBCHANNEL */ \ 1122 V(rp, RP_Z, 0xB277) /* type = S RESUME PROGRAM */ \ 1123 V(stcke, STCKE, 0xB278) /* type = S STORE CLOCK EXTENDED */ \ 1124 V(sacf, SACF, 0xB279) /* type = S SET ADDRESS SPACE CONTROL FAST */ \ 1125 V(stckf, STCKF, 0xB27C) /* type = S STORE CLOCK FAST */ \ 1126 V(stsi, STSI, 0xB27D) /* type = S STORE SYSTEM INFORMATION */ \ 1127 V(srnm, SRNM, 0xB299) /* type = S SET BFP ROUNDING MODE (2 bit) */ \ 1128 V(stfpc, STFPC, 0xB29C) /* type = S STORE FPC */ \ 1129 V(lfpc, LFPC, 0xB29D) /* type = S LOAD FPC */ \ 1130 V(stfle, STFLE, 0xB2B0) /* type = S STORE FACILITY LIST EXTENDED */ \ 1131 V(stfl, STFL, 0xB2B1) /* type = S STORE FACILITY LIST */ \ 1132 V(lpswe, LPSWE, 0xB2B2) /* type = S LOAD PSW EXTENDED */ \ 1133 V(srnmb, SRNMB, 0xB2B8) /* type = S SET BFP ROUNDING MODE (3 bit) */ \ 1134 V(srnmt, SRNMT, 0xB2B9) /* type = S SET DFP ROUNDING MODE */ \ 1135 V(lfas, LFAS, 0xB2BD) /* type = S LOAD FPC AND SIGNAL */ \ 1136 V(tend, TEND, 0xB2F8) /* type = S TRANSACTION END */ \ 1137 V(tabort, TABORT, 0xB2FC) /* type = S TRANSACTION ABORT */ \ 1138 V(trap4, TRAP4, 0xB2FF) /* type = S TRAP */ 1139 1140 #define S390_RX_A_OPCODE_LIST(V) \ 1141 V(la, LA, 0x41) /* type = RX_A LOAD ADDRESS */ \ 1142 V(stc, STC, 0x42) /* type = RX_A STORE CHARACTER */ \ 1143 V(ic_z, IC_z, 0x43) /* type = RX_A INSERT CHARACTER */ \ 1144 V(ex, EX, 0x44) /* type = RX_A EXECUTE */ \ 1145 V(bal, BAL, 0x45) /* type = RX_A BRANCH AND LINK */ \ 1146 V(bct, BCT, 0x46) /* type = RX_A BRANCH ON COUNT (32) */ \ 1147 V(lh, LH, 0x48) /* type = RX_A LOAD HALFWORD (32<-16) */ \ 1148 V(ch, CH, 0x49) /* type = RX_A COMPARE HALFWORD (32<-16) */ \ 1149 V(ah, AH, 0x4A) /* type = RX_A ADD HALFWORD (32<-16) */ \ 1150 V(sh, SH, 0x4B) /* type = RX_A SUBTRACT HALFWORD (32<-16) */ \ 1151 V(mh, MH, 0x4C) /* type = RX_A MULTIPLY HALFWORD (32<-16) */ \ 1152 V(bas, BAS, 0x4D) /* type = RX_A BRANCH AND SAVE */ \ 1153 V(cvd, CVD, 0x4E) /* type = RX_A CONVERT TO DECIMAL (32) */ \ 1154 V(cvb, CVB, 0x4F) /* type = RX_A CONVERT TO BINARY (32) */ \ 1155 V(st, ST, 0x50) /* type = RX_A STORE (32) */ \ 1156 V(lae, LAE, 0x51) /* type = RX_A LOAD ADDRESS EXTENDED */ \ 1157 V(n, N, 0x54) /* type = RX_A AND (32) */ \ 1158 V(cl, CL, 0x55) /* type = RX_A COMPARE LOGICAL (32) */ \ 1159 V(o, O, 0x56) /* type = RX_A OR (32) */ \ 1160 V(x, X, 0x57) /* type = RX_A EXCLUSIVE OR (32) */ \ 1161 V(l, L, 0x58) /* type = RX_A LOAD (32) */ \ 1162 V(c, C, 0x59) /* type = RX_A COMPARE (32) */ \ 1163 V(a, A, 0x5A) /* type = RX_A ADD (32) */ \ 1164 V(s, S, 0x5B) /* type = RX_A SUBTRACT (32) */ \ 1165 V(m, M, 0x5C) /* type = RX_A MULTIPLY (64<-32) */ \ 1166 V(d, D, 0x5D) /* type = RX_A DIVIDE (32<-64) */ \ 1167 V(al_z, AL, 0x5E) /* type = RX_A ADD LOGICAL (32) */ \ 1168 V(sl, SL, 0x5F) /* type = RX_A SUBTRACT LOGICAL (32) */ \ 1169 V(std, STD, 0x60) /* type = RX_A STORE (long) */ \ 1170 V(mxd, MXD, 0x67) /* type = RX_A MULTIPLY (long to extended HFP) */ \ 1171 V(ld, LD, 0x68) /* type = RX_A LOAD (long) */ \ 1172 V(cd, CD, 0x69) /* type = RX_A COMPARE (long HFP) */ \ 1173 V(ad, AD, 0x6A) /* type = RX_A ADD NORMALIZED (long HFP) */ \ 1174 V(sd, SD, 0x6B) /* type = RX_A SUBTRACT NORMALIZED (long HFP) */ \ 1175 V(md, MD, 0x6C) /* type = RX_A MULTIPLY (long HFP) */ \ 1176 V(dd, DD, 0x6D) /* type = RX_A DIVIDE (long HFP) */ \ 1177 V(aw, AW, 0x6E) /* type = RX_A ADD UNNORMALIZED (long HFP) */ \ 1178 V(sw, SW, 0x6F) /* type = RX_A SUBTRACT UNNORMALIZED (long HFP) */ \ 1179 V(ste, STE, 0x70) /* type = RX_A STORE (short) */ \ 1180 V(ms, MS, 0x71) /* type = RX_A MULTIPLY SINGLE (32) */ \ 1181 V(le_z, LE, 0x78) /* type = RX_A LOAD (short) */ \ 1182 V(ce, CE, 0x79) /* type = RX_A COMPARE (short HFP) */ \ 1183 V(ae, AE, 0x7A) /* type = RX_A ADD NORMALIZED (short HFP) */ \ 1184 V(se, SE, 0x7B) /* type = RX_A SUBTRACT NORMALIZED (short HFP) */ \ 1185 V(mde, MDE, 0x7C) /* type = RX_A MULTIPLY (short to long HFP) */ \ 1186 V(me, ME, 0x7C) /* type = RX_A MULTIPLY (short to long HFP) */ \ 1187 V(de, DE, 0x7D) /* type = RX_A DIVIDE (short HFP) */ \ 1188 V(au, AU, 0x7E) /* type = RX_A ADD UNNORMALIZED (short HFP) */ \ 1189 V(su, SU, 0x7F) /* type = RX_A SUBTRACT UNNORMALIZED (short HFP) */ \ 1190 V(ssm, SSM, 0x80) /* type = RX_A SET SYSTEM MASK */ \ 1191 V(lra, LRA, 0xB1) /* type = RX_A LOAD REAL ADDRESS (32) */ \ 1192 V(sth, STH, 0x40) /* type = RX_A STORE HALFWORD (16) */ 1193 1194 #define S390_RX_B_OPCODE_LIST(V) \ 1195 V(bc, BC, 0x47) /* type = RX_B BRANCH ON CONDITION */ 1196 1197 #define S390_RIE_A_OPCODE_LIST(V) \ 1198 V(cgit, CGIT, 0xEC70) /* type = RIE_A COMPARE IMMEDIATE AND TRAP (64<-16) */ \ 1199 V(clgit, CLGIT, \ 1200 0xEC71) /* type = RIE_A COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) */ \ 1201 V(cit, CIT, 0xEC72) /* type = RIE_A COMPARE IMMEDIATE AND TRAP (32<-16) */ \ 1202 V(clfit, CLFIT, \ 1203 0xEC73) /* type = RIE_A COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) */ 1204 1205 #define S390_RRD_OPCODE_LIST(V) \ 1206 V(maebr, MAEBR, 0xB30E) /* type = RRD MULTIPLY AND ADD (short BFP) */ \ 1207 V(msebr, MSEBR, 0xB30F) /* type = RRD MULTIPLY AND SUBTRACT (short BFP) */ \ 1208 V(madbr, MADBR, 0xB31E) /* type = RRD MULTIPLY AND ADD (long BFP) */ \ 1209 V(msdbr, MSDBR, 0xB31F) /* type = RRD MULTIPLY AND SUBTRACT (long BFP) */ \ 1210 V(maer, MAER, 0xB32E) /* type = RRD MULTIPLY AND ADD (short HFP) */ \ 1211 V(mser, MSER, 0xB32F) /* type = RRD MULTIPLY AND SUBTRACT (short HFP) */ \ 1212 V(maylr, MAYLR, \ 1213 0xB338) /* type = RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) */ \ 1214 V(mylr, MYLR, \ 1215 0xB339) /* type = RRD MULTIPLY UNNORM. (long to ext. low HFP) */ \ 1216 V(mayr, MAYR, \ 1217 0xB33A) /* type = RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) */ \ 1218 V(myr, MYR, \ 1219 0xB33B) /* type = RRD MULTIPLY UNNORMALIZED (long to ext. HFP) */ \ 1220 V(mayhr, MAYHR, \ 1221 0xB33C) /* type = RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) */ \ 1222 V(myhr, MYHR, \ 1223 0xB33D) /* type = RRD MULTIPLY UNNORM. (long to ext. high HFP) */ \ 1224 V(madr, MADR, 0xB33E) /* type = RRD MULTIPLY AND ADD (long HFP) */ \ 1225 V(msdr, MSDR, 0xB33F) /* type = RRD MULTIPLY AND SUBTRACT (long HFP) */ 1226 1227 #define S390_RIE_B_OPCODE_LIST(V) \ 1228 V(cgrj, CGRJ, 0xEC64) /* type = RIE_B COMPARE AND BRANCH RELATIVE (64) */ \ 1229 V(clgrj, CLGRJ, \ 1230 0xEC65) /* type = RIE_B COMPARE LOGICAL AND BRANCH RELATIVE (64) */ \ 1231 V(crj, CRJ, 0xEC76) /* type = RIE_B COMPARE AND BRANCH RELATIVE (32) */ \ 1232 V(clrj, CLRJ, \ 1233 0xEC77) /* type = RIE_B COMPARE LOGICAL AND BRANCH RELATIVE (32) */ 1234 1235 #define S390_RRE_OPCODE_LIST(V) \ 1236 V(ipm, IPM, 0xB222) /* type = RRE INSERT PROGRAM MASK */ \ 1237 V(ivsk, IVSK, 0xB223) /* type = RRE INSERT VIRTUAL STORAGE KEY */ \ 1238 V(iac, IAC, 0xB224) /* type = RRE INSERT ADDRESS SPACE CONTROL */ \ 1239 V(ssar, SSAR, 0xB225) /* type = RRE SET SECONDARY ASN */ \ 1240 V(epar, EPAR, 0xB226) /* type = RRE EXTRACT PRIMARY ASN */ \ 1241 V(esar, ESAR, 0xB227) /* type = RRE EXTRACT SECONDARY ASN */ \ 1242 V(pt, PT, 0xB228) /* type = RRE PROGRAM TRANSFER */ \ 1243 V(iske, ISKE, 0xB229) /* type = RRE INSERT STORAGE KEY EXTENDED */ \ 1244 V(rrbe, RRBE, 0xB22A) /* type = RRE RESET REFERENCE BIT EXTENDED */ \ 1245 V(tb, TB, 0xB22C) /* type = RRE TEST BLOCK */ \ 1246 V(dxr, DXR, 0xB22D) /* type = RRE DIVIDE (extended HFP) */ \ 1247 V(pgin, PGIN, 0xB22E) /* type = RRE PAGE IN */ \ 1248 V(pgout, PGOUT, 0xB22F) /* type = RRE PAGE OUT */ \ 1249 V(bakr, BAKR, 0xB240) /* type = RRE BRANCH AND STACK */ \ 1250 V(cksm, CKSM, 0xB241) /* type = RRE CHECKSUM */ \ 1251 V(sqdr, SQDR, 0xB244) /* type = RRE SQUARE ROOT (long HFP) */ \ 1252 V(sqer, SQER, 0xB245) /* type = RRE SQUARE ROOT (short HFP) */ \ 1253 V(stura, STURA, 0xB246) /* type = RRE STORE USING REAL ADDRESS (32) */ \ 1254 V(msta, MSTA, 0xB247) /* type = RRE MODIFY STACKED STATE */ \ 1255 V(palb, PALB, 0xB248) /* type = RRE PURGE ALB */ \ 1256 V(ereg, EREG, 0xB249) /* type = RRE EXTRACT STACKED REGISTERS (32) */ \ 1257 V(esta, ESTA, 0xB24A) /* type = RRE EXTRACT STACKED STATE */ \ 1258 V(lura, LURA, 0xB24B) /* type = RRE LOAD USING REAL ADDRESS (32) */ \ 1259 V(tar, TAR, 0xB24C) /* type = RRE TEST ACCESS */ \ 1260 V(cpya, CPYA, 0xB24D) /* type = RRE COPY ACCESS */ \ 1261 V(sar, SAR, 0xB24E) /* type = RRE SET ACCESS */ \ 1262 V(ear, EAR, 0xB24F) /* type = RRE EXTRACT ACCESS */ \ 1263 V(csp, CSP, 0xB250) /* type = RRE COMPARE AND SWAP AND PURGE (32) */ \ 1264 V(msr, MSR, 0xB252) /* type = RRE MULTIPLY SINGLE (32) */ \ 1265 V(mvpg, MVPG, 0xB254) /* type = RRE MOVE PAGE */ \ 1266 V(mvst, MVST, 0xB255) /* type = RRE MOVE STRING */ \ 1267 V(cuse, CUSE, 0xB257) /* type = RRE COMPARE UNTIL SUBSTRING EQUAL */ \ 1268 V(bsg, BSG, 0xB258) /* type = RRE BRANCH IN SUBSPACE GROUP */ \ 1269 V(bsa, BSA, 0xB25A) /* type = RRE BRANCH AND SET AUTHORITY */ \ 1270 V(clst, CLST, 0xB25D) /* type = RRE COMPARE LOGICAL STRING */ \ 1271 V(srst, SRST, 0xB25E) /* type = RRE SEARCH STRING */ \ 1272 V(cmpsc, CMPSC, 0xB263) /* type = RRE COMPRESSION CALL */ \ 1273 V(tre, TRE, 0xB2A5) /* type = RRE TRANSLATE EXTENDED */ \ 1274 V(etnd, ETND, 0xB2EC) /* type = RRE EXTRACT TRANSACTION NESTING DEPTH */ \ 1275 V(lpebr, LPEBR, 0xB300) /* type = RRE LOAD POSITIVE (short BFP) */ \ 1276 V(lnebr, LNEBR, 0xB301) /* type = RRE LOAD NEGATIVE (short BFP) */ \ 1277 V(ltebr, LTEBR, 0xB302) /* type = RRE LOAD AND TEST (short BFP) */ \ 1278 V(lcebr, LCEBR, 0xB303) /* type = RRE LOAD COMPLEMENT (short BFP) */ \ 1279 V(ldebr, LDEBR, \ 1280 0xB304) /* type = RRE LOAD LENGTHENED (short to long BFP) */ \ 1281 V(lxdbr, LXDBR, \ 1282 0xB305) /* type = RRE LOAD LENGTHENED (long to extended BFP) */ \ 1283 V(lxebr, LXEBR, \ 1284 0xB306) /* type = RRE LOAD LENGTHENED (short to extended BFP) */ \ 1285 V(mxdbr, MXDBR, 0xB307) /* type = RRE MULTIPLY (long to extended BFP) */ \ 1286 V(kebr, KEBR, 0xB308) /* type = RRE COMPARE AND SIGNAL (short BFP) */ \ 1287 V(cebr, CEBR, 0xB309) /* type = RRE COMPARE (short BFP) */ \ 1288 V(aebr, AEBR, 0xB30A) /* type = RRE ADD (short BFP) */ \ 1289 V(sebr, SEBR, 0xB30B) /* type = RRE SUBTRACT (short BFP) */ \ 1290 V(mdebr, MDEBR, 0xB30C) /* type = RRE MULTIPLY (short to long BFP) */ \ 1291 V(debr, DEBR, 0xB30D) /* type = RRE DIVIDE (short BFP) */ \ 1292 V(lpdbr, LPDBR, 0xB310) /* type = RRE LOAD POSITIVE (long BFP) */ \ 1293 V(lndbr, LNDBR, 0xB311) /* type = RRE LOAD NEGATIVE (long BFP) */ \ 1294 V(ltdbr, LTDBR, 0xB312) /* type = RRE LOAD AND TEST (long BFP) */ \ 1295 V(lcdbr, LCDBR, 0xB313) /* type = RRE LOAD COMPLEMENT (long BFP) */ \ 1296 V(sqebr, SQEBR, 0xB314) /* type = RRE SQUARE ROOT (short BFP) */ \ 1297 V(sqdbr, SQDBR, 0xB315) /* type = RRE SQUARE ROOT (long BFP) */ \ 1298 V(sqxbr, SQXBR, 0xB316) /* type = RRE SQUARE ROOT (extended BFP) */ \ 1299 V(meebr, MEEBR, 0xB317) /* type = RRE MULTIPLY (short BFP) */ \ 1300 V(kdbr, KDBR, 0xB318) /* type = RRE COMPARE AND SIGNAL (long BFP) */ \ 1301 V(cdbr, CDBR, 0xB319) /* type = RRE COMPARE (long BFP) */ \ 1302 V(adbr, ADBR, 0xB31A) /* type = RRE ADD (long BFP) */ \ 1303 V(sdbr, SDBR, 0xB31B) /* type = RRE SUBTRACT (long BFP) */ \ 1304 V(mdbr, MDBR, 0xB31C) /* type = RRE MULTIPLY (long BFP) */ \ 1305 V(ddbr, DDBR, 0xB31D) /* type = RRE DIVIDE (long BFP) */ \ 1306 V(lder, LDER, 0xB324) /* type = RRE LOAD LENGTHENED (short to long HFP) */ \ 1307 V(lxdr, LXDR, \ 1308 0xB325) /* type = RRE LOAD LENGTHENED (long to extended HFP) */ \ 1309 V(lxer, LXER, \ 1310 0xB326) /* type = RRE LOAD LENGTHENED (short to extended HFP) */ \ 1311 V(sqxr, SQXR, 0xB336) /* type = RRE SQUARE ROOT (extended HFP) */ \ 1312 V(meer, MEER, 0xB337) /* type = RRE MULTIPLY (short HFP) */ \ 1313 V(lpxbr, LPXBR, 0xB340) /* type = RRE LOAD POSITIVE (extended BFP) */ \ 1314 V(lnxbr, LNXBR, 0xB341) /* type = RRE LOAD NEGATIVE (extended BFP) */ \ 1315 V(ltxbr, LTXBR, 0xB342) /* type = RRE LOAD AND TEST (extended BFP) */ \ 1316 V(lcxbr, LCXBR, 0xB343) /* type = RRE LOAD COMPLEMENT (extended BFP) */ \ 1317 V(ledbr, LEDBR, 0xB344) /* type = RRE LOAD ROUNDED (long to short BFP) */ \ 1318 V(ldxbr, LDXBR, \ 1319 0xB345) /* type = RRE LOAD ROUNDED (extended to long BFP) */ \ 1320 V(lexbr, LEXBR, \ 1321 0xB346) /* type = RRE LOAD ROUNDED (extended to short BFP) */ \ 1322 V(kxbr, KXBR, 0xB348) /* type = RRE COMPARE AND SIGNAL (extended BFP) */ \ 1323 V(cxbr, CXBR, 0xB349) /* type = RRE COMPARE (extended BFP) */ \ 1324 V(axbr, AXBR, 0xB34A) /* type = RRE ADD (extended BFP) */ \ 1325 V(sxbr, SXBR, 0xB34B) /* type = RRE SUBTRACT (extended BFP) */ \ 1326 V(mxbr, MXBR, 0xB34C) /* type = RRE MULTIPLY (extended BFP) */ \ 1327 V(dxbr, DXBR, 0xB34D) /* type = RRE DIVIDE (extended BFP) */ \ 1328 V(thder, THDER, \ 1329 0xB358) /* type = RRE CONVERT BFP TO HFP (short to long) */ \ 1330 V(thdr, THDR, 0xB359) /* type = RRE CONVERT BFP TO HFP (long) */ \ 1331 V(lpxr, LPXR, 0xB360) /* type = RRE LOAD POSITIVE (extended HFP) */ \ 1332 V(lnxr, LNXR, 0xB361) /* type = RRE LOAD NEGATIVE (extended HFP) */ \ 1333 V(ltxr, LTXR, 0xB362) /* type = RRE LOAD AND TEST (extended HFP) */ \ 1334 V(lcxr, LCXR, 0xB363) /* type = RRE LOAD COMPLEMENT (extended HFP) */ \ 1335 V(lxr, LXR, 0xB365) /* type = RRE LOAD (extended) */ \ 1336 V(lexr, LEXR, \ 1337 0xB366) /* type = RRE LOAD ROUNDED (extended to short HFP) */ \ 1338 V(fixr, FIXR, 0xB367) /* type = RRE LOAD FP INTEGER (extended HFP) */ \ 1339 V(cxr, CXR, 0xB369) /* type = RRE COMPARE (extended HFP) */ \ 1340 V(lpdfr, LPDFR, 0xB370) /* type = RRE LOAD POSITIVE (long) */ \ 1341 V(lndfr, LNDFR, 0xB371) /* type = RRE LOAD NEGATIVE (long) */ \ 1342 V(lcdfr, LCDFR, 0xB373) /* type = RRE LOAD COMPLEMENT (long) */ \ 1343 V(lzer, LZER, 0xB374) /* type = RRE LOAD ZERO (short) */ \ 1344 V(lzdr, LZDR, 0xB375) /* type = RRE LOAD ZERO (long) */ \ 1345 V(lzxr, LZXR, 0xB376) /* type = RRE LOAD ZERO (extended) */ \ 1346 V(fier, FIER, 0xB377) /* type = RRE LOAD FP INTEGER (short HFP) */ \ 1347 V(fidr, FIDR, 0xB37F) /* type = RRE LOAD FP INTEGER (long HFP) */ \ 1348 V(sfpc, SFPC, 0xB384) /* type = RRE SET FPC */ \ 1349 V(sfasr, SFASR, 0xB385) /* type = RRE SET FPC AND SIGNAL */ \ 1350 V(efpc, EFPC, 0xB38C) /* type = RRE EXTRACT FPC */ \ 1351 V(cefbr, CEFBR, \ 1352 0xB394) /* type = RRE CONVERT FROM FIXED (32 to short BFP) */ \ 1353 V(cdfbr, CDFBR, \ 1354 0xB395) /* type = RRE CONVERT FROM FIXED (32 to long BFP) */ \ 1355 V(cxfbr, CXFBR, \ 1356 0xB396) /* type = RRE CONVERT FROM FIXED (32 to extended BFP) */ \ 1357 V(cegbr, CEGBR, \ 1358 0xB3A4) /* type = RRE CONVERT FROM FIXED (64 to short BFP) */ \ 1359 V(cdgbr, CDGBR, \ 1360 0xB3A5) /* type = RRE CONVERT FROM FIXED (64 to long BFP) */ \ 1361 V(cxgbr, CXGBR, \ 1362 0xB3A6) /* type = RRE CONVERT FROM FIXED (64 to extended BFP) */ \ 1363 V(cefr, CEFR, \ 1364 0xB3B4) /* type = RRE CONVERT FROM FIXED (32 to short HFP) */ \ 1365 V(cdfr, CDFR, 0xB3B5) /* type = RRE CONVERT FROM FIXED (32 to long HFP) */ \ 1366 V(cxfr, CXFR, \ 1367 0xB3B6) /* type = RRE CONVERT FROM FIXED (32 to extended HFP) */ \ 1368 V(ldgr, LDGR, 0xB3C1) /* type = RRE LOAD FPR FROM GR (64 to long) */ \ 1369 V(cegr, CEGR, \ 1370 0xB3C4) /* type = RRE CONVERT FROM FIXED (64 to short HFP) */ \ 1371 V(cdgr, CDGR, 0xB3C5) /* type = RRE CONVERT FROM FIXED (64 to long HFP) */ \ 1372 V(cxgr, CXGR, \ 1373 0xB3C6) /* type = RRE CONVERT FROM FIXED (64 to extended HFP) */ \ 1374 V(lgdr, LGDR, 0xB3CD) /* type = RRE LOAD GR FROM FPR (long to 64) */ \ 1375 V(ltdtr, LTDTR, 0xB3D6) /* type = RRE LOAD AND TEST (long DFP) */ \ 1376 V(ltxtr, LTXTR, 0xB3DE) /* type = RRE LOAD AND TEST (extended DFP) */ \ 1377 V(kdtr, KDTR, 0xB3E0) /* type = RRE COMPARE AND SIGNAL (long DFP) */ \ 1378 V(cudtr, CUDTR, 0xB3E2) /* type = RRE CONVERT TO UNSIGNED PACKED (long */ \ 1379 /* DFP to 64) CUDTR */ \ 1380 V(cdtr, CDTR, 0xB3E4) /* type = RRE COMPARE (long DFP) */ \ 1381 V(eedtr, EEDTR, \ 1382 0xB3E5) /* type = RRE EXTRACT BIASED EXPONENT (long DFP to 64) */ \ 1383 V(esdtr, ESDTR, \ 1384 0xB3E7) /* type = RRE EXTRACT SIGNIFICANCE (long DFP to 64) */ \ 1385 V(kxtr, KXTR, 0xB3E8) /* type = RRE COMPARE AND SIGNAL (extended DFP) */ \ 1386 V(cuxtr, CUXTR, \ 1387 0xB3EA) /* type = RRE CONVERT TO UNSIGNED PACKED (extended DFP */ \ 1388 /* CUXTR to 128) */ \ 1389 V(cxtr, CXTR, 0xB3EC) /* type = RRE COMPARE (extended DFP) */ \ 1390 V(eextr, EEXTR, \ 1391 0xB3ED) /* type = RRE EXTRACT BIASED EXPONENT (extended DFP to 64) */ \ 1392 V(esxtr, ESXTR, \ 1393 0xB3EF) /* type = RRE EXTRACT SIGNIFICANCE (extended DFP to 64) */ \ 1394 V(cdgtr, CDGTR, \ 1395 0xB3F1) /* type = RRE CONVERT FROM FIXED (64 to long DFP) */ \ 1396 V(cdutr, CDUTR, \ 1397 0xB3F2) /* type = RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) */ \ 1398 V(cdstr, CDSTR, \ 1399 0xB3F3) /* type = RRE CONVERT FROM SIGNED PACKED (64 to long DFP) */ \ 1400 V(cedtr, CEDTR, \ 1401 0xB3F4) /* type = RRE COMPARE BIASED EXPONENT (long DFP) */ \ 1402 V(cxgtr, CXGTR, \ 1403 0xB3F9) /* type = RRE CONVERT FROM FIXED (64 to extended DFP) */ \ 1404 V(cxutr, CXUTR, \ 1405 0xB3FA) /* type = RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) */ \ 1406 V(cxstr, CXSTR, 0xB3FB) /* type = RRE CONVERT FROM SIGNED PACKED (128 to*/ \ 1407 /* extended DFP) */ \ 1408 V(cextr, CEXTR, \ 1409 0xB3FC) /* type = RRE COMPARE BIASED EXPONENT (extended DFP) */ \ 1410 V(lpgr, LPGR, 0xB900) /* type = RRE LOAD POSITIVE (64) */ \ 1411 V(lngr, LNGR, 0xB901) /* type = RRE LOAD NEGATIVE (64) */ \ 1412 V(ltgr, LTGR, 0xB902) /* type = RRE LOAD AND TEST (64) */ \ 1413 V(lcgr, LCGR, 0xB903) /* type = RRE LOAD COMPLEMENT (64) */ \ 1414 V(lgr, LGR, 0xB904) /* type = RRE LOAD (64) */ \ 1415 V(lurag, LURAG, 0xB905) /* type = RRE LOAD USING REAL ADDRESS (64) */ \ 1416 V(lgbr, LGBR, 0xB906) /* type = RRE LOAD BYTE (64<-8) */ \ 1417 V(lghr, LGHR, 0xB907) /* type = RRE LOAD HALFWORD (64<-16) */ \ 1418 V(agr, AGR, 0xB908) /* type = RRE ADD (64) */ \ 1419 V(sgr, SGR, 0xB909) /* type = RRE SUBTRACT (64) */ \ 1420 V(algr, ALGR, 0xB90A) /* type = RRE ADD LOGICAL (64) */ \ 1421 V(slgr, SLGR, 0xB90B) /* type = RRE SUBTRACT LOGICAL (64) */ \ 1422 V(msgr, MSGR, 0xB90C) /* type = RRE MULTIPLY SINGLE (64) */ \ 1423 V(dsgr, DSGR, 0xB90D) /* type = RRE DIVIDE SINGLE (64) */ \ 1424 V(eregg, EREGG, 0xB90E) /* type = RRE EXTRACT STACKED REGISTERS (64) */ \ 1425 V(lrvgr, LRVGR, 0xB90F) /* type = RRE LOAD REVERSED (64) */ \ 1426 V(lpgfr, LPGFR, 0xB910) /* type = RRE LOAD POSITIVE (64<-32) */ \ 1427 V(lngfr, LNGFR, 0xB911) /* type = RRE LOAD NEGATIVE (64<-32) */ \ 1428 V(ltgfr, LTGFR, 0xB912) /* type = RRE LOAD AND TEST (64<-32) */ \ 1429 V(lcgfr, LCGFR, 0xB913) /* type = RRE LOAD COMPLEMENT (64<-32) */ \ 1430 V(lgfr, LGFR, 0xB914) /* type = RRE LOAD (64<-32) */ \ 1431 V(llgfr, LLGFR, 0xB916) /* type = RRE LOAD LOGICAL (64<-32) */ \ 1432 V(llgtr, LLGTR, \ 1433 0xB917) /* type = RRE LOAD LOGICAL THIRTY ONE BITS (64<-31) */ \ 1434 V(agfr, AGFR, 0xB918) /* type = RRE ADD (64<-32) */ \ 1435 V(sgfr, SGFR, 0xB919) /* type = RRE SUBTRACT (64<-32) */ \ 1436 V(algfr, ALGFR, 0xB91A) /* type = RRE ADD LOGICAL (64<-32) */ \ 1437 V(slgfr, SLGFR, 0xB91B) /* type = RRE SUBTRACT LOGICAL (64<-32) */ \ 1438 V(msgfr, MSGFR, 0xB91C) /* type = RRE MULTIPLY SINGLE (64<-32) */ \ 1439 V(dsgfr, DSGFR, 0xB91D) /* type = RRE DIVIDE SINGLE (64<-32) */ \ 1440 V(kmac, KMAC, 0xB91E) /* type = RRE COMPUTE MESSAGE AUTHENTICATION CODE */ \ 1441 V(lrvr, LRVR, 0xB91F) /* type = RRE LOAD REVERSED (32) */ \ 1442 V(cgr, CGR, 0xB920) /* type = RRE COMPARE (64) */ \ 1443 V(clgr, CLGR, 0xB921) /* type = RRE COMPARE LOGICAL (64) */ \ 1444 V(sturg, STURG, 0xB925) /* type = RRE STORE USING REAL ADDRESS (64) */ \ 1445 V(lbr, LBR, 0xB926) /* type = RRE LOAD BYTE (32<-8) */ \ 1446 V(lhr, LHR, 0xB927) /* type = RRE LOAD HALFWORD (32<-16) */ \ 1447 V(pckmo, PCKMO, \ 1448 0xB928) /* type = RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS */ \ 1449 V(kmf, KMF, 0xB92A) /* type = RRE CIPHER MESSAGE WITH CIPHER FEEDBACK */ \ 1450 V(kmo, KMO, 0xB92B) /* type = RRE CIPHER MESSAGE WITH OUTPUT FEEDBACK */ \ 1451 V(pcc, PCC, 0xB92C) /* type = RRE PERFORM CRYPTOGRAPHIC COMPUTATION */ \ 1452 V(km, KM, 0xB92E) /* type = RRE CIPHER MESSAGE */ \ 1453 V(kmc, KMC, 0xB92F) /* type = RRE CIPHER MESSAGE WITH CHAINING */ \ 1454 V(cgfr, CGFR, 0xB930) /* type = RRE COMPARE (64<-32) */ \ 1455 V(clgfr, CLGFR, 0xB931) /* type = RRE COMPARE LOGICAL (64<-32) */ \ 1456 V(ppno, PPNO, \ 1457 0xB93C) /* type = RRE PERFORM PSEUDORANDOM NUMBER OPERATION */ \ 1458 V(kimd, KIMD, 0xB93E) /* type = RRE COMPUTE INTERMEDIATE MESSAGE DIGEST */ \ 1459 V(klmd, KLMD, 0xB93F) /* type = RRE COMPUTE LAST MESSAGE DIGEST */ \ 1460 V(bctgr, BCTGR, 0xB946) /* type = RRE BRANCH ON COUNT (64) */ \ 1461 V(cdftr, CDFTR, \ 1462 0xB951) /* type = RRE CONVERT FROM FIXED (32 to long DFP) */ \ 1463 V(cxftr, CXFTR, \ 1464 0xB959) /* type = RRE CONVERT FROM FIXED (32 to extended DFP) */ \ 1465 V(ngr, NGR, 0xB980) /* type = RRE AND (64) */ \ 1466 V(ogr, OGR, 0xB981) /* type = RRE OR (64) */ \ 1467 V(xgr, XGR, 0xB982) /* type = RRE EXCLUSIVE OR (64) */ \ 1468 V(flogr, FLOGR, 0xB983) /* type = RRE FIND LEFTMOST ONE */ \ 1469 V(llgcr, LLGCR, 0xB984) /* type = RRE LOAD LOGICAL CHARACTER (64<-8) */ \ 1470 V(llghr, LLGHR, 0xB985) /* type = RRE LOAD LOGICAL HALFWORD (64<-16) */ \ 1471 V(mlgr, MLGR, 0xB986) /* type = RRE MULTIPLY LOGICAL (128<-64) */ \ 1472 V(dlgr, DLGR, 0xB987) /* type = RRE DIVIDE LOGICAL (64<-128) */ \ 1473 V(alcgr, ALCGR, 0xB988) /* type = RRE ADD LOGICAL WITH CARRY (64) */ \ 1474 V(slbgr, SLBGR, 0xB989) /* type = RRE SUBTRACT LOGICAL WITH BORROW (64) */ \ 1475 V(cspg, CSPG, 0xB98A) /* type = RRE COMPARE AND SWAP AND PURGE (64) */ \ 1476 V(epsw, EPSW, 0xB98D) /* type = RRE EXTRACT PSW */ \ 1477 V(llcr, LLCR, 0xB994) /* type = RRE LOAD LOGICAL CHARACTER (32<-8) */ \ 1478 V(llhr, LLHR, 0xB995) /* type = RRE LOAD LOGICAL HALFWORD (32<-16) */ \ 1479 V(mlr, MLR, 0xB996) /* type = RRE MULTIPLY LOGICAL (64<-32) */ \ 1480 V(dlr, DLR, 0xB997) /* type = RRE DIVIDE LOGICAL (32<-64) */ \ 1481 V(alcr, ALCR, 0xB998) /* type = RRE ADD LOGICAL WITH CARRY (32) */ \ 1482 V(slbr, SLBR, 0xB999) /* type = RRE SUBTRACT LOGICAL WITH BORROW (32) */ \ 1483 V(epair, EPAIR, 0xB99A) /* type = RRE EXTRACT PRIMARY ASN AND INSTANCE */ \ 1484 V(esair, ESAIR, \ 1485 0xB99B) /* type = RRE EXTRACT SECONDARY ASN AND INSTANCE */ \ 1486 V(esea, ESEA, 0xB99D) /* type = RRE EXTRACT AND SET EXTENDED AUTHORITY */ \ 1487 V(pti, PTI, 0xB99E) /* type = RRE PROGRAM TRANSFER WITH INSTANCE */ \ 1488 V(ssair, SSAIR, 0xB99F) /* type = RRE SET SECONDARY ASN WITH INSTANCE */ \ 1489 V(ptf, PTF, 0xB9A2) /* type = RRE PERFORM TOPOLOGY FUNCTION */ \ 1490 V(rrbm, RRBM, 0xB9AE) /* type = RRE RESET REFERENCE BITS MULTIPLE */ \ 1491 V(pfmf, PFMF, 0xB9AF) /* type = RRE PERFORM FRAME MANAGEMENT FUNCTION */ \ 1492 V(cu41, CU41, 0xB9B2) /* type = RRE CONVERT UTF-32 TO UTF-8 */ \ 1493 V(cu42, CU42, 0xB9B3) /* type = RRE CONVERT UTF-32 TO UTF-16 */ \ 1494 V(srstu, SRSTU, 0xB9BE) /* type = RRE SEARCH STRING UNICODE */ \ 1495 V(chhr, CHHR, 0xB9CD) /* type = RRE COMPARE HIGH (32) */ \ 1496 V(clhhr, CLHHR, 0xB9CF) /* type = RRE COMPARE LOGICAL HIGH (32) */ \ 1497 V(chlr, CHLR, 0xB9DD) /* type = RRE COMPARE HIGH (32) */ \ 1498 V(clhlr, CLHLR, 0xB9DF) /* type = RRE COMPARE LOGICAL HIGH (32) */ \ 1499 V(popcnt, POPCNT_Z, 0xB9E1) /* type = RRE POPULATION COUNT */ 1500 1501 #define S390_RIE_C_OPCODE_LIST(V) \ 1502 V(cgij, CGIJ, \ 1503 0xEC7C) /* type = RIE_C COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) */ \ 1504 V(clgij, CLGIJ, \ 1505 0xEC7D) /* type = RIE_C COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE */ \ 1506 /* (64<-8) */ \ 1507 V(cij, CIJ, \ 1508 0xEC7E) /* type = RIE_C COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) */ \ 1509 V(clij, CLIJ, 0xEC7F) /* type = RIE_C COMPARE LOGICAL IMMEDIATE AND */ \ 1510 /* BRANCH RELATIVE (32<-8) */ 1511 1512 #define S390_RIE_D_OPCODE_LIST(V) \ 1513 V(ahik, AHIK, 0xECD8) /* type = RIE_D ADD IMMEDIATE (32<-16) */ \ 1514 V(aghik, AGHIK, 0xECD9) /* type = RIE_D ADD IMMEDIATE (64<-16) */ \ 1515 V(alhsik, ALHSIK, \ 1516 0xECDA) /* type = RIE_D ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) */ \ 1517 V(alghsik, ALGHSIK, \ 1518 0xECDB) /* type = RIE_D ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) */ 1519 1520 #define S390_VRV_OPCODE_LIST(V) \ 1521 V(vgeg, VGEG, 0xE712) /* type = VRV VECTOR GATHER ELEMENT (64) */ \ 1522 V(vgef, VGEF, 0xE713) /* type = VRV VECTOR GATHER ELEMENT (32) */ \ 1523 V(vsceg, VSCEG, 0xE71A) /* type = VRV VECTOR SCATTER ELEMENT (64) */ \ 1524 V(vscef, VSCEF, 0xE71B) /* type = VRV VECTOR SCATTER ELEMENT (32) */ 1525 1526 #define S390_RIE_E_OPCODE_LIST(V) \ 1527 V(brxhg, BRXHG, \ 1528 0xEC44) /* type = RIE_E BRANCH RELATIVE ON INDEX HIGH (64) */ \ 1529 V(brxlg, BRXLG, \ 1530 0xEC45) /* type = RIE_E BRANCH RELATIVE ON INDEX LOW OR EQ. (64) */ 1531 1532 #define S390_RR_OPCODE_LIST(V) \ 1533 V(spm, SPM, 0x04) /* type = RR SET PROGRAM MASK */ \ 1534 V(balr, BALR, 0x05) /* type = RR BRANCH AND LINK */ \ 1535 V(bctr, BCTR, 0x06) /* type = RR BRANCH ON COUNT (32) */ \ 1536 V(bcr, BCR, 0x07) /* type = RR BRANCH ON CONDITION */ \ 1537 V(bsm, BSM, 0x0B) /* type = RR BRANCH AND SET MODE */ \ 1538 V(bassm, BASSM, 0x0C) /* type = RR BRANCH AND SAVE AND SET MODE */ \ 1539 V(basr, BASR, 0x0D) /* type = RR BRANCH AND SAVE */ \ 1540 V(mvcl, MVCL, 0x0E) /* type = RR MOVE LONG */ \ 1541 V(clcl, CLCL, 0x0F) /* type = RR COMPARE LOGICAL LONG */ \ 1542 V(lpr, LPR, 0x10) /* type = RR LOAD POSITIVE (32) */ \ 1543 V(lnr, LNR, 0x11) /* type = RR LOAD NEGATIVE (32) */ \ 1544 V(ltr, LTR, 0x12) /* type = RR LOAD AND TEST (32) */ \ 1545 V(lcr, LCR, 0x13) /* type = RR LOAD COMPLEMENT (32) */ \ 1546 V(nr, NR, 0x14) /* type = RR AND (32) */ \ 1547 V(clr, CLR, 0x15) /* type = RR COMPARE LOGICAL (32) */ \ 1548 V(or_z, OR, 0x16) /* type = RR OR (32) */ \ 1549 V(xr, XR, 0x17) /* type = RR EXCLUSIVE OR (32) */ \ 1550 V(lr, LR, 0x18) /* type = RR LOAD (32) */ \ 1551 V(cr_z, CR, 0x19) /* type = RR COMPARE (32) */ \ 1552 V(ar, AR, 0x1A) /* type = RR ADD (32) */ \ 1553 V(sr, SR, 0x1B) /* type = RR SUBTRACT (32) */ \ 1554 V(mr_z, MR, 0x1C) /* type = RR MULTIPLY (64<-32) */ \ 1555 V(dr, DR, 0x1D) /* type = RR DIVIDE (32<-64) */ \ 1556 V(alr, ALR, 0x1E) /* type = RR ADD LOGICAL (32) */ \ 1557 V(slr, SLR, 0x1F) /* type = RR SUBTRACT LOGICAL (32) */ \ 1558 V(lpdr, LPDR, 0x20) /* type = RR LOAD POSITIVE (long HFP) */ \ 1559 V(lndr, LNDR, 0x21) /* type = RR LOAD NEGATIVE (long HFP) */ \ 1560 V(ltdr, LTDR, 0x22) /* type = RR LOAD AND TEST (long HFP) */ \ 1561 V(lcdr, LCDR, 0x23) /* type = RR LOAD COMPLEMENT (long HFP) */ \ 1562 V(hdr, HDR, 0x24) /* type = RR HALVE (long HFP) */ \ 1563 V(ldxr, LDXR, 0x25) /* type = RR LOAD ROUNDED (extended to long HFP) */ \ 1564 V(lrdr, LRDR, 0x25) /* type = RR LOAD ROUNDED (extended to long HFP) */ \ 1565 V(mxr, MXR, 0x26) /* type = RR MULTIPLY (extended HFP) */ \ 1566 V(mxdr, MXDR, 0x27) /* type = RR MULTIPLY (long to extended HFP) */ \ 1567 V(ldr, LDR, 0x28) /* type = RR LOAD (long) */ \ 1568 V(cdr, CDR, 0x29) /* type = RR COMPARE (long HFP) */ \ 1569 V(adr, ADR, 0x2A) /* type = RR ADD NORMALIZED (long HFP) */ \ 1570 V(sdr, SDR, 0x2B) /* type = RR SUBTRACT NORMALIZED (long HFP) */ \ 1571 V(mdr, MDR, 0x2C) /* type = RR MULTIPLY (long HFP) */ \ 1572 V(ddr, DDR, 0x2D) /* type = RR DIVIDE (long HFP) */ \ 1573 V(swr, SWR, 0x2F) /* type = RR SUBTRACT UNNORMALIZED (long HFP) */ \ 1574 V(lper, LPER, 0x30) /* type = RR LOAD POSITIVE (short HFP) */ \ 1575 V(lner, LNER, 0x31) /* type = RR LOAD NEGATIVE (short HFP) */ \ 1576 V(lter, LTER, 0x32) /* type = RR LOAD AND TEST (short HFP) */ \ 1577 V(lcer, LCER, 0x33) /* type = RR LOAD COMPLEMENT (short HFP) */ \ 1578 V(her_z, HER_Z, 0x34) /* type = RR HALVE (short HFP) */ \ 1579 V(ledr, LEDR, 0x35) /* type = RR LOAD ROUNDED (long to short HFP) */ \ 1580 V(lrer, LRER, 0x35) /* type = RR LOAD ROUNDED (long to short HFP) */ \ 1581 V(axr, AXR, 0x36) /* type = RR ADD NORMALIZED (extended HFP) */ \ 1582 V(sxr, SXR, 0x37) /* type = RR SUBTRACT NORMALIZED (extended HFP) */ \ 1583 V(ler, LER, 0x38) /* type = RR LOAD (short) */ \ 1584 V(cer, CER, 0x39) /* type = RR COMPARE (short HFP) */ \ 1585 V(aer, AER, 0x3A) /* type = RR ADD NORMALIZED (short HFP) */ \ 1586 V(ser, SER, 0x3B) /* type = RR SUBTRACT NORMALIZED (short HFP) */ \ 1587 V(mder, MDER, 0x3C) /* type = RR MULTIPLY (short to long HFP) */ \ 1588 V(mer, MER, 0x3C) /* type = RR MULTIPLY (short to long HFP) */ \ 1589 V(der, DER, 0x3D) /* type = RR DIVIDE (short HFP) */ \ 1590 V(aur, AUR, 0x3E) /* type = RR ADD UNNORMALIZED (short HFP) */ \ 1591 V(sur, SUR, 0x3F) /* type = RR SUBTRACT UNNORMALIZED (short HFP) */ 1592 1593 #define S390_RIE_F_OPCODE_LIST(V) \ 1594 V(risblg, RISBLG, \ 1595 0xEC51) /* type = RIE_F ROTATE THEN INSERT SELECTED BITS LOW (64) */ \ 1596 V(rnsbg, RNSBG, \ 1597 0xEC54) /* type = RIE_F ROTATE THEN AND SELECTED BITS (64) */ \ 1598 V(risbg, RISBG, \ 1599 0xEC55) /* type = RIE_F ROTATE THEN INSERT SELECTED BITS (64) */ \ 1600 V(rosbg, ROSBG, 0xEC56) /* type = RIE_F ROTATE THEN OR SELECTED BITS (64) */ \ 1601 V(rxsbg, RXSBG, \ 1602 0xEC57) /* type = RIE_F ROTATE THEN EXCLUSIVE OR SELECT. BITS (64) */ \ 1603 V(risbgn, RISBGN, \ 1604 0xEC59) /* type = RIE_F ROTATE THEN INSERT SELECTED BITS (64) */ \ 1605 V(risbhg, RISBHG, \ 1606 0xEC5D) /* type = RIE_F ROTATE THEN INSERT SELECTED BITS HIGH (64) */ 1607 1608 #define S390_VRX_OPCODE_LIST(V) \ 1609 V(vleb, VLEB, 0xE700) /* type = VRX VECTOR LOAD ELEMENT (8) */ \ 1610 V(vleh, VLEH, 0xE701) /* type = VRX VECTOR LOAD ELEMENT (16) */ \ 1611 V(vleg, VLEG, 0xE702) /* type = VRX VECTOR LOAD ELEMENT (64) */ \ 1612 V(vlef, VLEF, 0xE703) /* type = VRX VECTOR LOAD ELEMENT (32) */ \ 1613 V(vllez, VLLEZ, \ 1614 0xE704) /* type = VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO */ \ 1615 V(vlrep, VLREP, 0xE705) /* type = VRX VECTOR LOAD AND REPLICATE */ \ 1616 V(vl, VL, 0xE706) /* type = VRX VECTOR LOAD */ \ 1617 V(vlbb, VLBB, 0xE707) /* type = VRX VECTOR LOAD TO BLOCK BOUNDARY */ \ 1618 V(vsteb, VSTEB, 0xE708) /* type = VRX VECTOR STORE ELEMENT (8) */ \ 1619 V(vsteh, VSTEH, 0xE709) /* type = VRX VECTOR STORE ELEMENT (16) */ \ 1620 V(vsteg, VSTEG, 0xE70A) /* type = VRX VECTOR STORE ELEMENT (64) */ \ 1621 V(vstef, VSTEF, 0xE70B) /* type = VRX VECTOR STORE ELEMENT (32) */ \ 1622 V(vst, VST, 0xE70E) /* type = VRX VECTOR STORE */ 1623 1624 #define S390_RIE_G_OPCODE_LIST(V) \ 1625 V(lochi, LOCHI, \ 1626 0xEC42) /* type = RIE_G LOAD HALFWORD IMMEDIATE ON CONDITION (32<-16) */ \ 1627 V(locghi, LOCGHI, \ 1628 0xEC46) /* type = RIE_G LOAD HALFWORD IMMEDIATE ON CONDITION (64<-16) */ \ 1629 V(lochhi, LOCHHI, 0xEC4E) /* type = RIE_G LOAD HALFWORD HIGH IMMEDIATE */ \ 1630 /* ON CONDITION (32<-16) */ 1631 1632 #define S390_RRS_OPCODE_LIST(V) \ 1633 V(cgrb, CGRB, 0xECE4) /* type = RRS COMPARE AND BRANCH (64) */ \ 1634 V(clgrb, CLGRB, 0xECE5) /* type = RRS COMPARE LOGICAL AND BRANCH (64) */ \ 1635 V(crb, CRB, 0xECF6) /* type = RRS COMPARE AND BRANCH (32) */ \ 1636 V(clrb, CLRB, 0xECF7) /* type = RRS COMPARE LOGICAL AND BRANCH (32) */ 1637 1638 #define S390_OPCODE_LIST(V) \ 1639 S390_RSY_A_OPCODE_LIST(V) \ 1640 S390_RSY_B_OPCODE_LIST(V) \ 1641 S390_RXE_OPCODE_LIST(V) \ 1642 S390_RRF_A_OPCODE_LIST(V) \ 1643 S390_RXF_OPCODE_LIST(V) \ 1644 S390_IE_OPCODE_LIST(V) \ 1645 S390_RRF_B_OPCODE_LIST(V) \ 1646 S390_RRF_C_OPCODE_LIST(V) \ 1647 S390_MII_OPCODE_LIST(V) \ 1648 S390_RRF_D_OPCODE_LIST(V) \ 1649 S390_RRF_E_OPCODE_LIST(V) \ 1650 S390_VRR_A_OPCODE_LIST(V) \ 1651 S390_VRR_B_OPCODE_LIST(V) \ 1652 S390_VRR_C_OPCODE_LIST(V) \ 1653 S390_VRI_A_OPCODE_LIST(V) \ 1654 S390_VRR_D_OPCODE_LIST(V) \ 1655 S390_VRI_B_OPCODE_LIST(V) \ 1656 S390_VRR_E_OPCODE_LIST(V) \ 1657 S390_VRI_C_OPCODE_LIST(V) \ 1658 S390_VRI_D_OPCODE_LIST(V) \ 1659 S390_VRR_F_OPCODE_LIST(V) \ 1660 S390_RIS_OPCODE_LIST(V) \ 1661 S390_VRI_E_OPCODE_LIST(V) \ 1662 S390_RSL_A_OPCODE_LIST(V) \ 1663 S390_RSL_B_OPCODE_LIST(V) \ 1664 S390_SI_OPCODE_LIST(V) \ 1665 S390_SIL_OPCODE_LIST(V) \ 1666 S390_VRS_A_OPCODE_LIST(V) \ 1667 S390_RIL_A_OPCODE_LIST(V) \ 1668 S390_RIL_B_OPCODE_LIST(V) \ 1669 S390_VRS_B_OPCODE_LIST(V) \ 1670 S390_RIL_C_OPCODE_LIST(V) \ 1671 S390_VRS_C_OPCODE_LIST(V) \ 1672 S390_RI_A_OPCODE_LIST(V) \ 1673 S390_RSI_OPCODE_LIST(V) \ 1674 S390_RI_B_OPCODE_LIST(V) \ 1675 S390_RI_C_OPCODE_LIST(V) \ 1676 S390_RSL_OPCODE_LIST(V) \ 1677 S390_SMI_OPCODE_LIST(V) \ 1678 S390_RXY_A_OPCODE_LIST(V) \ 1679 S390_RXY_B_OPCODE_LIST(V) \ 1680 S390_SIY_OPCODE_LIST(V) \ 1681 S390_SS_A_OPCODE_LIST(V) \ 1682 S390_E_OPCODE_LIST(V) \ 1683 S390_SS_B_OPCODE_LIST(V) \ 1684 S390_SS_C_OPCODE_LIST(V) \ 1685 S390_SS_D_OPCODE_LIST(V) \ 1686 S390_SS_E_OPCODE_LIST(V) \ 1687 S390_I_OPCODE_LIST(V) \ 1688 S390_SS_F_OPCODE_LIST(V) \ 1689 S390_SSE_OPCODE_LIST(V) \ 1690 S390_SSF_OPCODE_LIST(V) \ 1691 S390_RS_A_OPCODE_LIST(V) \ 1692 S390_RS_B_OPCODE_LIST(V) \ 1693 S390_S_OPCODE_LIST(V) \ 1694 S390_RX_A_OPCODE_LIST(V) \ 1695 S390_RX_B_OPCODE_LIST(V) \ 1696 S390_RIE_A_OPCODE_LIST(V) \ 1697 S390_RRD_OPCODE_LIST(V) \ 1698 S390_RIE_B_OPCODE_LIST(V) \ 1699 S390_RRE_OPCODE_LIST(V) \ 1700 S390_RIE_C_OPCODE_LIST(V) \ 1701 S390_RIE_D_OPCODE_LIST(V) \ 1702 S390_VRV_OPCODE_LIST(V) \ 1703 S390_RIE_E_OPCODE_LIST(V) \ 1704 S390_RR_OPCODE_LIST(V) \ 1705 S390_RIE_F_OPCODE_LIST(V) \ 1706 S390_VRX_OPCODE_LIST(V) \ 1707 S390_RIE_G_OPCODE_LIST(V) \ 1708 S390_RRS_OPCODE_LIST(V) 1709 1710 // Opcodes as defined in Appendix B-2 table 1711 enum Opcode { 1712 #define DECLARE_OPCODES(name, opcode_name, opcode_value) \ 1713 opcode_name = opcode_value, 1714 S390_OPCODE_LIST(DECLARE_OPCODES) 1715 #undef DECLARE_OPCODES 1716 1717 BKPT = 0x0001, // GDB Software Breakpoint 1718 DUMY = 0xE353 // Special dummy opcode 1719 }; 1720 1721 // Instruction encoding bits and masks. 1722 enum { 1723 // Instruction encoding bit 1724 B1 = 1 << 1, 1725 B4 = 1 << 4, 1726 B5 = 1 << 5, 1727 B7 = 1 << 7, 1728 B8 = 1 << 8, 1729 B9 = 1 << 9, 1730 B12 = 1 << 12, 1731 B18 = 1 << 18, 1732 B19 = 1 << 19, 1733 B20 = 1 << 20, 1734 B22 = 1 << 22, 1735 B23 = 1 << 23, 1736 B24 = 1 << 24, 1737 B25 = 1 << 25, 1738 B26 = 1 << 26, 1739 B27 = 1 << 27, 1740 B28 = 1 << 28, 1741 1742 B6 = 1 << 6, 1743 B10 = 1 << 10, 1744 B11 = 1 << 11, 1745 B16 = 1 << 16, 1746 B17 = 1 << 17, 1747 B21 = 1 << 21, 1748 1749 // Instruction bit masks 1750 kCondMask = 0x1F << 21, 1751 kOff12Mask = (1 << 12) - 1, 1752 kImm24Mask = (1 << 24) - 1, 1753 kOff16Mask = (1 << 16) - 1, 1754 kImm16Mask = (1 << 16) - 1, 1755 kImm26Mask = (1 << 26) - 1, 1756 kBOfieldMask = 0x1f << 21, 1757 kOpcodeMask = 0x3f << 26, 1758 kExt2OpcodeMask = 0x1f << 1, 1759 kExt5OpcodeMask = 0x3 << 2, 1760 kBIMask = 0x1F << 16, 1761 kBDMask = 0x14 << 2, 1762 kAAMask = 0x01 << 1, 1763 kLKMask = 0x01, 1764 kRCMask = 0x01, 1765 kTOMask = 0x1f << 21 1766 }; 1767 1768 // S390 instructions requires bigger shifts, 1769 // make them macros instead of enum because of the typing issue 1770 #define B32 ((uint64_t)1 << 32) 1771 #define B36 ((uint64_t)1 << 36) 1772 #define B40 ((uint64_t)1 << 40) 1773 const FourByteInstr kFourByteBrCondMask = 0xF << 20; 1774 const SixByteInstr kSixByteBrCondMask = static_cast<SixByteInstr>(0xF) << 36; 1775 1776 // ----------------------------------------------------------------------------- 1777 // Addressing modes and instruction variants. 1778 1779 // Overflow Exception 1780 enum OEBit { 1781 SetOE = 1 << 10, // Set overflow exception 1782 LeaveOE = 0 << 10 // No overflow exception 1783 }; 1784 1785 // Record bit 1786 enum RCBit { // Bit 0 1787 SetRC = 1, // LT,GT,EQ,SO 1788 LeaveRC = 0 // None 1789 }; 1790 1791 // Link bit 1792 enum LKBit { // Bit 0 1793 SetLK = 1, // Load effective address of next instruction 1794 LeaveLK = 0 // No action 1795 }; 1796 1797 enum BOfield { // Bits 25-21 1798 DCBNZF = 0 << 21, // Decrement CTR; branch if CTR != 0 and condition false 1799 DCBEZF = 2 << 21, // Decrement CTR; branch if CTR == 0 and condition false 1800 BF = 4 << 21, // Branch if condition false 1801 DCBNZT = 8 << 21, // Decrement CTR; branch if CTR != 0 and condition true 1802 DCBEZT = 10 << 21, // Decrement CTR; branch if CTR == 0 and condition true 1803 BT = 12 << 21, // Branch if condition true 1804 DCBNZ = 16 << 21, // Decrement CTR; branch if CTR != 0 1805 DCBEZ = 18 << 21, // Decrement CTR; branch if CTR == 0 1806 BA = 20 << 21 // Branch always 1807 }; 1808 1809 #ifdef _AIX 1810 #undef CR_LT 1811 #undef CR_GT 1812 #undef CR_EQ 1813 #undef CR_SO 1814 #endif 1815 1816 enum CRBit { CR_LT = 0, CR_GT = 1, CR_EQ = 2, CR_SO = 3, CR_FU = 3 }; 1817 1818 #define CRWIDTH 4 1819 1820 // ----------------------------------------------------------------------------- 1821 // Supervisor Call (svc) specific support. 1822 1823 // Special Software Interrupt codes when used in the presence of the S390 1824 // simulator. 1825 // SVC provides a 24bit immediate value. Use bits 22:0 for standard 1826 // SoftwareInterrupCode. Bit 23 is reserved for the stop feature. 1827 enum SoftwareInterruptCodes { 1828 // Transition to C code 1829 kCallRtRedirected = 0x0010, 1830 // Breakpoint 1831 kBreakpoint = 0x0000, 1832 // Stop 1833 kStopCode = 1 << 23 1834 }; 1835 const uint32_t kStopCodeMask = kStopCode - 1; 1836 const uint32_t kMaxStopCode = kStopCode - 1; 1837 const int32_t kDefaultStopCode = -1; 1838 1839 // FP rounding modes. 1840 enum FPRoundingMode { 1841 RN = 0, // Round to Nearest. 1842 RZ = 1, // Round towards zero. 1843 RP = 2, // Round towards Plus Infinity. 1844 RM = 3, // Round towards Minus Infinity. 1845 1846 // Aliases. 1847 kRoundToNearest = RN, 1848 kRoundToZero = RZ, 1849 kRoundToPlusInf = RP, 1850 kRoundToMinusInf = RM 1851 }; 1852 1853 const uint32_t kFPRoundingModeMask = 3; 1854 1855 enum CheckForInexactConversion { 1856 kCheckForInexactConversion, 1857 kDontCheckForInexactConversion 1858 }; 1859 1860 // ----------------------------------------------------------------------------- 1861 // Specific instructions, constants, and masks. 1862 1863 // use TRAP4 to indicate redirection call for simulation mode 1864 const Instr rtCallRedirInstr = TRAP4; 1865 1866 // ----------------------------------------------------------------------------- 1867 // Instruction abstraction. 1868 1869 // The class Instruction enables access to individual fields defined in the 1870 // z/Architecture instruction set encoding. 1871 class Instruction { 1872 public: 1873 // S390 Opcode Format Types 1874 // Based on the first byte of the opcode, we can determine how to extract 1875 // the entire opcode of the instruction. The various favours include: 1876 enum OpcodeFormatType { 1877 ONE_BYTE_OPCODE, // One Byte - Bits 0 to 7 1878 TWO_BYTE_OPCODE, // Two Bytes - Bits 0 to 15 1879 TWO_BYTE_DISJOINT_OPCODE, // Two Bytes - Bits 0 to 7, 40 to 47 1880 THREE_NIBBLE_OPCODE // Three Nibbles - Bits 0 to 7, 12 to 15 1881 }; 1882 1883 static OpcodeFormatType OpcodeFormatTable[256]; 1884 // Helper macro to define static accessors. 1885 // We use the cast to char* trick to bypass the strict anti-aliasing rules. 1886 #define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \ 1887 static inline return_type Name(Instr instr) { \ 1888 char* temp = reinterpret_cast<char*>(&instr); \ 1889 return reinterpret_cast<Instruction*>(temp)->Name(); \ 1890 } 1891 1892 #define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name) 1893 1894 // Get the raw instruction bits. 1895 template <typename T> 1896 inline T InstructionBits() const { 1897 return Instruction::InstructionBits<T>(reinterpret_cast<const byte*>(this)); 1898 } 1899 inline Instr InstructionBits() const { 1900 return *reinterpret_cast<const Instr*>(this); 1901 } 1902 1903 // Set the raw instruction bits to value. 1904 template <typename T> 1905 inline void SetInstructionBits(T value) const { 1906 Instruction::SetInstructionBits<T>(reinterpret_cast<const byte*>(this), 1907 value); 1908 } 1909 inline void SetInstructionBits(Instr value) { 1910 *reinterpret_cast<Instr*>(this) = value; 1911 } 1912 1913 // Read one particular bit out of the instruction bits. 1914 inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; } 1915 1916 // Read a bit field's value out of the instruction bits. 1917 inline int Bits(int hi, int lo) const { 1918 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); 1919 } 1920 1921 // Read bits according to instruction type 1922 template <typename T, typename U> 1923 inline U Bits(int hi, int lo) const { 1924 return (InstructionBits<T>() >> lo) & ((2 << (hi - lo)) - 1); 1925 } 1926 1927 // Read a bit field out of the instruction bits. 1928 inline int BitField(int hi, int lo) const { 1929 return InstructionBits() & (((2 << (hi - lo)) - 1) << lo); 1930 } 1931 1932 // Determine the instruction length 1933 inline int InstructionLength() { 1934 return Instruction::InstructionLength(reinterpret_cast<const byte*>(this)); 1935 } 1936 // Extract the Instruction Opcode 1937 inline Opcode S390OpcodeValue() { 1938 return Instruction::S390OpcodeValue(reinterpret_cast<const byte*>(this)); 1939 } 1940 1941 // Static support. 1942 1943 // Read one particular bit out of the instruction bits. 1944 static inline int Bit(Instr instr, int nr) { return (instr >> nr) & 1; } 1945 1946 // Read the value of a bit field out of the instruction bits. 1947 static inline int Bits(Instr instr, int hi, int lo) { 1948 return (instr >> lo) & ((2 << (hi - lo)) - 1); 1949 } 1950 1951 // Read a bit field out of the instruction bits. 1952 static inline int BitField(Instr instr, int hi, int lo) { 1953 return instr & (((2 << (hi - lo)) - 1) << lo); 1954 } 1955 1956 // Determine the instruction length of the given instruction 1957 static inline int InstructionLength(const byte* instr) { 1958 // Length can be determined by the first nibble. 1959 // 0x0 to 0x3 => 2-bytes 1960 // 0x4 to 0xB => 4-bytes 1961 // 0xC to 0xF => 6-bytes 1962 byte topNibble = (*instr >> 4) & 0xF; 1963 if (topNibble <= 3) 1964 return 2; 1965 else if (topNibble <= 0xB) 1966 return 4; 1967 return 6; 1968 } 1969 1970 // Returns the instruction bits of the given instruction 1971 static inline uint64_t InstructionBits(const byte* instr) { 1972 int length = InstructionLength(instr); 1973 if (2 == length) 1974 return static_cast<uint64_t>(InstructionBits<TwoByteInstr>(instr)); 1975 else if (4 == length) 1976 return static_cast<uint64_t>(InstructionBits<FourByteInstr>(instr)); 1977 else 1978 return InstructionBits<SixByteInstr>(instr); 1979 } 1980 1981 // Extract the raw instruction bits 1982 template <typename T> 1983 static inline T InstructionBits(const byte* instr) { 1984 #if !V8_TARGET_LITTLE_ENDIAN 1985 if (sizeof(T) <= 4) { 1986 return *reinterpret_cast<const T*>(instr); 1987 } else { 1988 // We cannot read 8-byte instructon address directly, because for a 1989 // six-byte instruction, the extra 2-byte address might not be 1990 // allocated. 1991 uint64_t fourBytes = *reinterpret_cast<const uint32_t*>(instr); 1992 uint16_t twoBytes = *reinterpret_cast<const uint16_t*>(instr + 4); 1993 return (fourBytes << 16 | twoBytes); 1994 } 1995 #else 1996 // Even on little endian hosts (simulation), the instructions 1997 // are stored as big-endian in order to decode the opcode and 1998 // instruction length. 1999 T instr_bits = 0; 2000 2001 // 6-byte instrs are represented by uint64_t 2002 uint32_t size = (sizeof(T) == 8) ? 6 : sizeof(T); 2003 2004 for (T i = 0; i < size; i++) { 2005 instr_bits <<= 8; 2006 instr_bits |= *(instr + i); 2007 } 2008 return instr_bits; 2009 #endif 2010 } 2011 2012 // Set the Instruction Bits to value 2013 template <typename T> 2014 static inline void SetInstructionBits(byte* instr, T value) { 2015 #if V8_TARGET_LITTLE_ENDIAN 2016 // The instruction bits are stored in big endian format even on little 2017 // endian hosts, in order to decode instruction length and opcode. 2018 // The following code will reverse the bytes so that the stores later 2019 // (which are in native endianess) will effectively save the instruction 2020 // in big endian. 2021 if (sizeof(T) == 2) { 2022 // Two Byte Instruction 2023 value = ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8); 2024 } else if (sizeof(T) == 4) { 2025 // Four Byte Instruction 2026 value = ((value & 0x000000FF) << 24) | ((value & 0x0000FF00) << 8) | 2027 ((value & 0x00FF0000) >> 8) | ((value & 0xFF000000) >> 24); 2028 } else if (sizeof(T) == 8) { 2029 // Six Byte Instruction 2030 uint64_t orig_value = static_cast<uint64_t>(value); 2031 value = (static_cast<uint64_t>(orig_value & 0xFF) << 40) | 2032 (static_cast<uint64_t>((orig_value >> 8) & 0xFF) << 32) | 2033 (static_cast<uint64_t>((orig_value >> 16) & 0xFF) << 24) | 2034 (static_cast<uint64_t>((orig_value >> 24) & 0xFF) << 16) | 2035 (static_cast<uint64_t>((orig_value >> 32) & 0xFF) << 8) | 2036 (static_cast<uint64_t>((orig_value >> 40) & 0xFF)); 2037 } 2038 #endif 2039 if (sizeof(T) <= 4) { 2040 *reinterpret_cast<T*>(instr) = value; 2041 } else { 2042 #if V8_TARGET_LITTLE_ENDIAN 2043 uint64_t orig_value = static_cast<uint64_t>(value); 2044 *reinterpret_cast<uint32_t*>(instr) = static_cast<uint32_t>(value); 2045 *reinterpret_cast<uint16_t*>(instr + 4) = 2046 static_cast<uint16_t>((orig_value >> 32) & 0xFFFF); 2047 #else 2048 *reinterpret_cast<uint32_t*>(instr) = static_cast<uint32_t>(value >> 16); 2049 *reinterpret_cast<uint16_t*>(instr + 4) = 2050 static_cast<uint16_t>(value & 0xFFFF); 2051 #endif 2052 } 2053 } 2054 2055 // Get Instruction Format Type 2056 static OpcodeFormatType getOpcodeFormatType(const byte* instr) { 2057 const byte firstByte = *instr; 2058 return OpcodeFormatTable[firstByte]; 2059 } 2060 2061 // Extract the full opcode from the instruction. 2062 static inline Opcode S390OpcodeValue(const byte* instr) { 2063 OpcodeFormatType opcodeType = getOpcodeFormatType(instr); 2064 2065 // The native instructions are encoded in big-endian format 2066 // even if running on little-endian host. Hence, we need 2067 // to ensure we use byte* based bit-wise logic. 2068 switch (opcodeType) { 2069 case ONE_BYTE_OPCODE: 2070 // One Byte - Bits 0 to 7 2071 return static_cast<Opcode>(*instr); 2072 case TWO_BYTE_OPCODE: 2073 // Two Bytes - Bits 0 to 15 2074 return static_cast<Opcode>((*instr << 8) | (*(instr + 1))); 2075 case TWO_BYTE_DISJOINT_OPCODE: 2076 // Two Bytes - Bits 0 to 7, 40 to 47 2077 return static_cast<Opcode>((*instr << 8) | (*(instr + 5) & 0xFF)); 2078 default: 2079 // case THREE_NIBBLE_OPCODE: 2080 // Three Nibbles - Bits 0 to 7, 12 to 15 2081 return static_cast<Opcode>((*instr << 4) | (*(instr + 1) & 0xF)); 2082 } 2083 2084 UNREACHABLE(); 2085 return static_cast<Opcode>(-1); 2086 } 2087 2088 // Fields used in Software interrupt instructions 2089 inline SoftwareInterruptCodes SvcValue() const { 2090 return static_cast<SoftwareInterruptCodes>(Bits<FourByteInstr, int>(15, 0)); 2091 } 2092 2093 // Instructions are read of out a code stream. The only way to get a 2094 // reference to an instruction is to convert a pointer. There is no way 2095 // to allocate or create instances of class Instruction. 2096 // Use the At(pc) function to create references to Instruction. 2097 static Instruction* At(byte* pc) { 2098 return reinterpret_cast<Instruction*>(pc); 2099 } 2100 2101 private: 2102 // We need to prevent the creation of instances of class Instruction. 2103 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); 2104 }; 2105 2106 #define DECLARE_FIELD_FOR_TWO_BYTE_INSTR(name, T, lo, hi) \ 2107 inline int name() const { \ 2108 return Bits<TwoByteInstr, T>(15 - (lo), 15 - (hi) + 1); \ 2109 } 2110 2111 #define DECLARE_FIELD_FOR_FOUR_BYTE_INSTR(name, T, lo, hi) \ 2112 inline int name() const { \ 2113 return Bits<FourByteInstr, T>(31 - (lo), 31 - (hi) + 1); \ 2114 } 2115 2116 #define DECLARE_FIELD_FOR_SIX_BYTE_INSTR(name, T, lo, hi) \ 2117 inline int name() const { \ 2118 return Bits<SixByteInstr, T>(47 - (lo), 47 - (hi) + 1); \ 2119 } 2120 2121 class TwoByteInstruction : public Instruction { 2122 public: 2123 inline int size() const { return 2; } 2124 }; 2125 2126 class FourByteInstruction : public Instruction { 2127 public: 2128 inline int size() const { return 4; } 2129 }; 2130 2131 class SixByteInstruction : public Instruction { 2132 public: 2133 inline int size() const { return 6; } 2134 }; 2135 2136 // I Instruction 2137 class IInstruction : public TwoByteInstruction { 2138 public: 2139 DECLARE_FIELD_FOR_TWO_BYTE_INSTR(IValue, int, 8, 16); 2140 }; 2141 2142 // E Instruction 2143 class EInstruction : public TwoByteInstruction {}; 2144 2145 // IE Instruction 2146 class IEInstruction : public FourByteInstruction { 2147 public: 2148 DECLARE_FIELD_FOR_FOUR_BYTE_INSTR(I1Value, int, 24, 28); 2149 DECLARE_FIELD_FOR_FOUR_BYTE_INSTR(I2Value, int, 28, 32); 2150 }; 2151 2152 // MII Instruction 2153 class MIIInstruction : public SixByteInstruction { 2154 public: 2155 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(M1Value, uint32_t, 8, 12); 2156 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(RI2Value, int, 12, 24); 2157 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(RI3Value, int, 24, 47); 2158 }; 2159 2160 // RI Instruction 2161 class RIInstruction : public FourByteInstruction { 2162 public: 2163 DECLARE_FIELD_FOR_FOUR_BYTE_INSTR(R1Value, int, 8, 12); 2164 DECLARE_FIELD_FOR_FOUR_BYTE_INSTR(I2Value, int, 16, 32); 2165 DECLARE_FIELD_FOR_FOUR_BYTE_INSTR(I2UnsignedValue, uint32_t, 16, 32); 2166 DECLARE_FIELD_FOR_FOUR_BYTE_INSTR(M1Value, uint32_t, 8, 12); 2167 }; 2168 2169 // RR Instruction 2170 class RRInstruction : Instruction { 2171 public: 2172 inline int R1Value() const { 2173 // the high and low parameters of Bits is the number of bits from 2174 // rightmost place 2175 return Bits<TwoByteInstr, int>(7, 4); 2176 } 2177 inline int R2Value() const { return Bits<TwoByteInstr, int>(3, 0); } 2178 inline Condition M1Value() const { 2179 return static_cast<Condition>(Bits<TwoByteInstr, int>(7, 4)); 2180 } 2181 2182 inline int size() const { return 2; } 2183 }; 2184 2185 // RRE Instruction 2186 class RREInstruction : Instruction { 2187 public: 2188 inline int R1Value() const { return Bits<FourByteInstr, int>(7, 4); } 2189 inline int R2Value() const { return Bits<FourByteInstr, int>(3, 0); } 2190 inline int M3Value() const { return Bits<FourByteInstr, int>(15, 12); } 2191 inline int M4Value() const { return Bits<FourByteInstr, int>(19, 16); } 2192 inline int size() const { return 4; } 2193 }; 2194 2195 // RRF Instruction 2196 class RRFInstruction : Instruction { 2197 public: 2198 inline int R1Value() const { return Bits<FourByteInstr, int>(7, 4); } 2199 inline int R2Value() const { return Bits<FourByteInstr, int>(3, 0); } 2200 inline int R3Value() const { return Bits<FourByteInstr, int>(15, 12); } 2201 inline int M3Value() const { return Bits<FourByteInstr, int>(15, 12); } 2202 inline int M4Value() const { return Bits<FourByteInstr, int>(11, 8); } 2203 inline int size() const { return 4; } 2204 }; 2205 2206 // RRD Isntruction 2207 class RRDInstruction : Instruction { 2208 public: 2209 inline int R1Value() const { return Bits<FourByteInstr, int>(15, 12); } 2210 inline int R2Value() const { return Bits<FourByteInstr, int>(3, 0); } 2211 inline int R3Value() const { return Bits<FourByteInstr, int>(7, 4); } 2212 inline int size() const { return 4; } 2213 }; 2214 2215 // RS Instruction 2216 class RSInstruction : Instruction { 2217 public: 2218 inline int R1Value() const { return Bits<FourByteInstr, int>(23, 20); } 2219 inline int R3Value() const { return Bits<FourByteInstr, int>(19, 16); } 2220 inline int B2Value() const { return Bits<FourByteInstr, int>(15, 12); } 2221 inline unsigned int D2Value() const { 2222 return Bits<FourByteInstr, unsigned int>(11, 0); 2223 } 2224 inline int size() const { return 4; } 2225 }; 2226 2227 // RSY Instruction 2228 class RSYInstruction : Instruction { 2229 public: 2230 inline int R1Value() const { return Bits<SixByteInstr, int>(39, 36); } 2231 inline int R3Value() const { return Bits<SixByteInstr, int>(35, 32); } 2232 inline int B2Value() const { return Bits<SixByteInstr, int>(31, 28); } 2233 inline int32_t D2Value() const { 2234 int32_t value = Bits<SixByteInstr, int32_t>(27, 16); 2235 value += Bits<SixByteInstr, int8_t>(15, 8) << 12; 2236 return value; 2237 } 2238 inline int size() const { return 6; } 2239 }; 2240 2241 // RX Instruction 2242 class RXInstruction : Instruction { 2243 public: 2244 inline int R1Value() const { return Bits<FourByteInstr, int>(23, 20); } 2245 inline int X2Value() const { return Bits<FourByteInstr, int>(19, 16); } 2246 inline int B2Value() const { return Bits<FourByteInstr, int>(15, 12); } 2247 inline uint32_t D2Value() const { 2248 return Bits<FourByteInstr, uint32_t>(11, 0); 2249 } 2250 inline int size() const { return 4; } 2251 }; 2252 2253 // RXY Instruction 2254 class RXYInstruction : Instruction { 2255 public: 2256 inline int R1Value() const { return Bits<SixByteInstr, int>(39, 36); } 2257 inline int X2Value() const { return Bits<SixByteInstr, int>(35, 32); } 2258 inline int B2Value() const { return Bits<SixByteInstr, int>(31, 28); } 2259 inline int32_t D2Value() const { 2260 int32_t value = Bits<SixByteInstr, uint32_t>(27, 16); 2261 value += Bits<SixByteInstr, int8_t>(15, 8) << 12; 2262 return value; 2263 } 2264 inline int size() const { return 6; } 2265 }; 2266 2267 // RIL Instruction 2268 class RILInstruction : Instruction { 2269 public: 2270 inline int R1Value() const { return Bits<SixByteInstr, int>(39, 36); } 2271 inline int32_t I2Value() const { return Bits<SixByteInstr, int32_t>(31, 0); } 2272 inline uint32_t I2UnsignedValue() const { 2273 return Bits<SixByteInstr, uint32_t>(31, 0); 2274 } 2275 inline int size() const { return 6; } 2276 }; 2277 2278 // SI Instruction 2279 class SIInstruction : Instruction { 2280 public: 2281 inline int B1Value() const { return Bits<FourByteInstr, int>(15, 12); } 2282 inline uint32_t D1Value() const { 2283 return Bits<FourByteInstr, uint32_t>(11, 0); 2284 } 2285 inline uint8_t I2Value() const { 2286 return Bits<FourByteInstr, uint8_t>(23, 16); 2287 } 2288 inline int size() const { return 4; } 2289 }; 2290 2291 // SIY Instruction 2292 class SIYInstruction : Instruction { 2293 public: 2294 inline int B1Value() const { return Bits<SixByteInstr, int>(31, 28); } 2295 inline int32_t D1Value() const { 2296 int32_t value = Bits<SixByteInstr, uint32_t>(27, 16); 2297 value += Bits<SixByteInstr, int8_t>(15, 8) << 12; 2298 return value; 2299 } 2300 inline uint8_t I2Value() const { return Bits<SixByteInstr, uint8_t>(39, 32); } 2301 inline int size() const { return 6; } 2302 }; 2303 2304 // SIL Instruction 2305 class SILInstruction : Instruction { 2306 public: 2307 inline int B1Value() const { return Bits<SixByteInstr, int>(31, 28); } 2308 inline int D1Value() const { return Bits<SixByteInstr, int>(27, 16); } 2309 inline int I2Value() const { return Bits<SixByteInstr, int>(15, 0); } 2310 inline int size() const { return 6; } 2311 }; 2312 2313 // SS Instruction 2314 class SSInstruction : Instruction { 2315 public: 2316 inline int B1Value() const { return Bits<SixByteInstr, int>(31, 28); } 2317 inline int B2Value() const { return Bits<SixByteInstr, int>(15, 12); } 2318 inline int D1Value() const { return Bits<SixByteInstr, int>(27, 16); } 2319 inline int D2Value() const { return Bits<SixByteInstr, int>(11, 0); } 2320 inline int Length() const { return Bits<SixByteInstr, int>(39, 32); } 2321 inline int size() const { return 6; } 2322 }; 2323 2324 // RXE Instruction 2325 class RXEInstruction : Instruction { 2326 public: 2327 inline int R1Value() const { return Bits<SixByteInstr, int>(39, 36); } 2328 inline int X2Value() const { return Bits<SixByteInstr, int>(35, 32); } 2329 inline int B2Value() const { return Bits<SixByteInstr, int>(31, 28); } 2330 inline int D2Value() const { return Bits<SixByteInstr, int>(27, 16); } 2331 inline int size() const { return 6; } 2332 }; 2333 2334 // RIE Instruction 2335 class RIEInstruction : Instruction { 2336 public: 2337 inline int R1Value() const { return Bits<SixByteInstr, int>(39, 36); } 2338 inline int R2Value() const { return Bits<SixByteInstr, int>(35, 32); } 2339 inline int I3Value() const { return Bits<SixByteInstr, uint32_t>(31, 24); } 2340 inline int I4Value() const { return Bits<SixByteInstr, uint32_t>(23, 16); } 2341 inline int I5Value() const { return Bits<SixByteInstr, uint32_t>(15, 8); } 2342 inline int I6Value() const { 2343 return static_cast<int32_t>(Bits<SixByteInstr, int16_t>(31, 16)); 2344 } 2345 inline int size() const { return 6; } 2346 }; 2347 2348 // VRR Instruction 2349 class VRR_C_Instruction : SixByteInstruction { 2350 public: 2351 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(R1Value, int, 8, 12); 2352 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(R2Value, int, 12, 16); 2353 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(R3Value, int, 16, 20); 2354 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(M6Value, uint32_t, 24, 28); 2355 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(M5Value, uint32_t, 28, 32); 2356 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(M4Value, uint32_t, 32, 36); 2357 }; 2358 2359 // Helper functions for converting between register numbers and names. 2360 class Registers { 2361 public: 2362 // Lookup the register number for the name provided. 2363 static int Number(const char* name); 2364 2365 private: 2366 static const char* names_[kNumRegisters]; 2367 }; 2368 2369 // Helper functions for converting between FP register numbers and names. 2370 class DoubleRegisters { 2371 public: 2372 // Lookup the register number for the name provided. 2373 static int Number(const char* name); 2374 2375 private: 2376 static const char* names_[kNumDoubleRegisters]; 2377 }; 2378 2379 } // namespace internal 2380 } // namespace v8 2381 2382 #endif // V8_S390_CONSTANTS_S390_H_ 2383
