| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| gen8_ps_state.c | 36 uint32_t dw1 = 0; local
38 dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
39 dw1 |= prog_data->computed_depth_mode << GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT;
42 dw1 |= GEN8_PSX_KILL_ENABLE;
45 dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
48 dw1 |= GEN8_PSX_USES_SOURCE_DEPTH;
51 dw1 |= GEN8_PSX_USES_SOURCE_W;
54 dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
60 dw1 |= BRW_PCICMS_DEPTH << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
62 dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT
144 uint32_t dw1 = 0; local
[all...] |
| gen8_sf_state.c | 47 uint32_t dw1 = local
62 dw1 |= GEN6_SF_POINT_SPRITE_LOWERLEFT;
64 dw1 |= GEN6_SF_POINT_SPRITE_UPPERLEFT;
84 dw1 |=
115 OUT_BATCH(dw1);
159 uint32_t dw1 = 0, dw2 = 0, dw3 = 0; local
162 dw1 = GEN6_SF_STATISTICS_ENABLE;
165 dw1 |= GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
170 dw1 |= line_width_u3_7 << GEN9_SF_LINE_WIDTH_SHIFT;
208 OUT_BATCH(dw1);
232 uint32_t dw1 = 0; local
[all...] |
| gen7_sf_state.c | 41 uint32_t dw1; local
50 dw1 = GEN7_SBE_SWIZZLE_ENABLE | num_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT;
62 dw1 |= point_sprite_origin;
73 dw1 |= urb_entry_read_length << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
78 OUT_BATCH(dw1);
115 uint32_t dw1, dw2, dw3; local
121 dw1 = GEN6_SF_STATISTICS_ENABLE;
124 dw1 |= GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
127 dw1 |= (brw_depthbuffer_format(brw) << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
131 dw1 |= GEN6_SF_WINDING_CCW
[all...] |
| gen8_wm_depth_stencil.c | 35 uint32_t dw1 = 0, dw2 = 0, dw3 = 0; local
48 dw1 |=
56 dw1 |= GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE;
65 dw1 |=
89 dw1 |=
94 dw1 |= GEN8_WM_DS_DEPTH_BUFFER_WRITE_ENABLE;
101 OUT_BATCH(dw1);
|
| gen7_wm_state.c | 44 uint32_t dw1, dw2; local
49 dw1 = dw2 = 0;
50 dw1 |= GEN7_WM_STATISTICS_ENABLE;
51 dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
52 dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
56 dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
60 dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
63 dw1 |= GEN7_WM_USES_SOURCE_DEPTH;
66 dw1 |= GEN7_WM_USES_SOURCE_W;
68 dw1 |= prog_data->computed_depth_mode << GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT
[all...] |
| gen6_clip_state.c | 95 uint32_t dw1 = brw->meta_in_progress ? 0 : GEN6_CLIP_STATISTICS_ENABLE; local
108 dw1 |= brw_vue_prog_data(brw->vs.base.prog_data)->cull_distance_mask;
111 dw1 |= GEN7_CLIP_EARLY_CULL;
116 dw1 |= GEN7_CLIP_WINDING_CCW;
121 dw1 |= GEN7_CLIP_CULLMODE_FRONT;
124 dw1 |= GEN7_CLIP_CULLMODE_BACK;
127 dw1 |= GEN7_CLIP_CULLMODE_BOTH;
133 dw1 |= GEN7_CLIP_CULLMODE_NONE;
163 dw1 |= GEN8_CLIP_FORCE_USER_CLIP_DISTANCE_BITMASK;
199 OUT_BATCH(dw1);
[all...] |
| gen8_blend_state.c | 211 uint32_t dw1 = 0; local
219 dw1 |= GEN8_PS_BLEND_HAS_WRITEABLE_RT;
224 dw1 |= GEN8_PS_BLEND_ALPHA_TEST_ENABLE;
229 dw1 |= GEN8_PS_BLEND_ALPHA_TO_COVERAGE_ENABLE;
271 dw1 |=
279 dw1 |= GEN8_PS_BLEND_INDEPENDENT_ALPHA_BLEND_ENABLE;
284 OUT_BATCH(dw1);
|
| gen8_depth_state.c | 469 uint32_t dw1 = 0; local
473 dw1 |= GEN8_WM_HZ_DEPTH_RESOLVE;
476 dw1 |= GEN8_WM_HZ_HIZ_RESOLVE;
479 dw1 |= GEN8_WM_HZ_DEPTH_CLEAR;
491 dw1 |= GEN8_WM_HZ_FULL_SURFACE_DEPTH_CLEAR;
498 dw1 |= SET_FIELD(ffs(mt->num_samples) - 1, GEN8_WM_HZ_NUM_SAMPLES);
502 OUT_BATCH(dw1);
|
| gen6_sf_state.c | 276 uint32_t dw1, dw2, dw3, dw4; local
287 dw1 = GEN6_SF_SWIZZLE_ENABLE | num_outputs << GEN6_SF_NUM_OUTPUTS_SHIFT;
394 dw1 |= point_sprite_origin;
414 dw1 |= (urb_entry_read_length << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
419 OUT_BATCH(dw1);
|
| gen8_draw_upload.c | 83 unsigned dw1 = 0; local
85 dw1 |= GEN8_SGVS_ENABLE_VERTEX_ID |
91 dw1 |= GEN8_SGVS_ENABLE_INSTANCE_ID |
98 OUT_BATCH(dw1);
|
| gen7_sol_state.c | 231 uint32_t dw1 = 0, dw2 = 0, dw3 = 0, dw4 = 0; local
241 dw1 |= SO_FUNCTION_ENABLE;
242 dw1 |= SO_STATISTICS_ENABLE;
247 dw1 |= SO_RENDERING_DISABLE;
256 dw1 |= SO_REORDER_TRAILING;
261 dw1 |= SO_BUFFER_ENABLE(i);
299 OUT_BATCH(dw1);
|
| /external/mesa3d/src/gallium/drivers/ilo/core/ |
| ilo_state_cc.c | 90 uint32_t dw0, dw1, dw2; local
99 dw1 = 0;
140 dw1 |= front_p->test_mask << GEN6_ZS_DW1_STENCIL_TEST_MASK__SHIFT |
160 cc->ds[1] = dw1;
174 uint32_t dw1, dw2; local
182 dw1 = 0;
191 dw1 |= GEN8_ZS_DW1_STENCIL_TEST_ENABLE;
194 dw1 |= GEN8_ZS_DW1_STENCIL1_ENABLE;
203 dw1 |= front->fail_op << GEN8_ZS_DW1_STENCIL_FAIL_OP__SHIFT |
213 dw1 |= GEN8_ZS_DW1_STENCIL_WRITE_ENABLE
490 uint32_t dw0, dw1; local
593 uint32_t dw_rt[2 * ILO_STATE_CC_BLEND_MAX_RT_COUNT], dw0, dw1; local
678 uint32_t dw1; local
786 uint32_t dw1 = cc->ds[0]; local
813 uint32_t dw1 = cc->ds[1]; local
[all...] |
| ilo_state_raster.c | 65 uint32_t dw1, dw2, dw3; local
72 dw1 = clip->user_cull_enables << GEN6_CLIP_DW1_UCP_CULL_ENABLES__SHIFT;
75 dw1 |= GEN6_CLIP_DW1_STATISTICS;
87 dw1 |= GEN7_CLIP_DW1_SUBPIXEL_8BITS |
91 dw1 |= tri->front_winding << GEN7_CLIP_DW1_FRONT_WINDING__SHIFT |
139 rs->clip[0] = dw1;
313 uint32_t dw1, dw2, dw3; local
320 dw1 = tri->fill_mode_front << GEN7_SF_DW1_FILL_MODE_FRONT__SHIFT |
340 dw1 |= format << GEN7_SF_DW1_DEPTH_FORMAT__SHIFT;
352 dw1 |= GEN7_SF_DW1_STATISTICS
442 uint32_t dw1, dw2, dw3; local
498 uint32_t dw1; local
597 uint32_t dw1; local
635 uint32_t dw1; local
771 uint32_t dw1; local
829 uint32_t dw1, dw4; local
903 uint32_t dw1, dw2; local
[all...] |
| ilo_state_zs.c | 38 uint32_t dw1; local
43 dw1 = GEN6_SURFTYPE_NULL << GEN7_DEPTH_DW1_TYPE__SHIFT |
46 dw1 = GEN6_SURFTYPE_NULL << GEN6_DEPTH_DW1_TYPE__SHIFT |
52 zs->depth[0] = dw1;
389 uint32_t dw1, dw2, dw3, dw4; local
400 dw1 = info->type << GEN6_DEPTH_DW1_TYPE__SHIFT |
405 dw1 |= (info->z_img->bo_stride - 1) << GEN6_DEPTH_DW1_PITCH__SHIFT;
408 dw1 |= GEN6_DEPTH_DW1_HIZ_ENABLE |
422 zs->depth[0] = dw1;
438 uint32_t dw1, dw2, dw3, dw4, dw6 local
509 uint32_t dw1, dw2; local
576 uint32_t dw1, dw2; local
[all...] |
| ilo_state_sol.c | 147 uint32_t dw1, dw2; local
167 dw1 = info->render_stream << GEN7_SO_DW1_RENDER_STREAM_SELECT__SHIFT |
171 dw1 |= GEN7_SO_DW1_SO_ENABLE;
174 dw1 |= GEN7_SO_DW1_RENDER_DISABLE;
177 dw1 |= GEN7_SO_DW1_STATISTICS;
184 dw1 |= buffer_enables << GEN7_SO_DW1_BUFFER_ENABLES__SHIFT;
197 sol->streamout[0] = dw1;
214 uint32_t dw1, dw2; local
247 dw1 = buffer_selects[3] << GEN7_SO_DECL_DW1_STREAM3_BUFFER_SELECTS__SHIFT |
257 sol->so_decl[0] = dw1;
348 uint32_t dw1; local
[all...] |
| ilo_state_shader_ps.c | 490 uint32_t dw1, dw2; local
494 dw1 = io->pscdepth << GEN7_WM_DW1_PSCDEPTH__SHIFT;
497 dw1 |= GEN7_WM_DW1_PS_DISPATCH_ENABLE;
499 dw1 |= GEN7_WM_DW1_PS_KILL_PIXEL;
502 dw1 |= GEN7_WM_DW1_PS_USE_DEPTH;
504 dw1 |= GEN7_WM_DW1_PS_USE_W;
506 dw1 |= GEN7_WM_DW1_PS_USE_COVERAGE_MASK;
512 ps->ps[0] = dw1;
637 uint32_t dw1; local
641 dw1 = io->pscdepth << GEN8_PSX_DW1_PSCDEPTH__SHIFT
[all...] |
| ilo_state_sbe.c | 224 uint32_t dw1, dw2, dw3; local
238 dw1 = attr_count << GEN7_SBE_DW1_ATTR_COUNT__SHIFT |
242 dw1 |= GEN8_SBE_DW1_FORCE_URB_READ_LEN |
246 dw1 |= vue_read_offset << GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT;
250 dw1 |= GEN7_SBE_DW1_ATTR_SWIZZLE_16_31;
253 dw1 |= GEN7_SBE_DW1_ATTR_SWIZZLE_ENABLE;
255 dw1 |= (info->point_sprite_origin_lower_left) ?
263 sbe->sbe[0] = dw1;
|
| ilo_state_urb.c | 559 uint32_t dw1[5]; local
575 dw1[i] = offset_kb << GEN7_PCB_ALLOC_DW1_OFFSET__SHIFT |
579 dw1[i] = 0;
584 memcpy(urb->pcb, dw1, sizeof(dw1));
595 uint32_t dw1, dw2; local
601 dw1 = (conf->vs_entry_rows - 1) << GEN6_URB_DW1_VS_ENTRY_SIZE__SHIFT |
607 urb->urb[0] = dw1;
619 uint32_t dw1[4]; local
651 dw1[i]
[all...] |
| ilo_builder_render.h | 79 gen6_PIPE_CONTROL(struct ilo_builder *builder, uint32_t dw1,
90 if (dw1 & GEN6_PIPE_CONTROL_CS_STALL) {
96 * * Depth Cache Flush Enable ([0] of DW1)
97 * * Stall at Pixel Scoreboard ([1] of DW1)
98 * * Depth Stall ([13] of DW1)
99 * * Post-Sync Operation ([13] of DW1)
100 * * Render Target Cache Flush Enable ([12] of DW1)
101 * * Notify Enable ([8] of DW1)"
107 * * Render Target Cache Flush Enable ([12] of DW1)
108 * * Depth Cache Flush Enable ([0] of DW1)
[all...] |
| ilo_state_vf.c | 136 uint32_t dw0, dw1; local
168 dw1 = get_gen6_component_controls(dev,
174 vf->user_ve[i][1] = dw1;
186 vf->last_user_ve[0][1] = dw1;
203 dw1 = get_gen6_component_controls(dev, GEN6_VFCOMP_STORE_SRC,
208 vf->last_user_ve[1][1] = dw1;
308 uint32_t dw1[2]; local
335 dw1[internal_ve_count++] = get_gen6_component_zeros(dev);
340 dw1[internal_ve_count++] = get_gen6_component_zeros(dev);
342 dw1[internal_ve_count++] = get_gen6_component_ids(dev
364 uint32_t dw1; local
[all...] |
| /external/mesa3d/src/gallium/drivers/ilo/ |
| ilo_render_gen6.c | 45 gen6_wa_pre_pipe_control(struct ilo_render *r, uint32_t dw1)
63 const bool direct_wa_cond = (dw1 & GEN6_PIPE_CONTROL_WRITE__MASK) &&
64 !(dw1 & GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH);
65 const bool indirect_wa_cond = (dw1 & GEN6_PIPE_CONTROL_DEPTH_STALL) |
66 (dw1 & GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH);
79 * - Depth Cache Flush Enable ([0] of DW1)
80 * - Stall at Pixel Scoreboard ([1] of DW1)
81 * - Depth Stall ([13] of DW1)
82 * - Post-Sync Operation ([13] of DW1)
83 * - Render Target Cache Flush Enable ([12] of DW1)
126 const uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL; local
142 const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_STALL | local
166 const uint32_t dw1 = GEN6_PIPE_CONTROL_WRITE_IMM | local
185 const uint32_t dw1 = GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL; local
206 const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH | local
[all...] |
| ilo_render_gen.h | 365 ilo_render_pipe_control(struct ilo_render *r, uint32_t dw1)
367 const uint32_t write_mask = (dw1 & GEN6_PIPE_CONTROL_WRITE__MASK);
375 if (dw1 & GEN6_PIPE_CONTROL_CS_STALL) {
382 if (!(dw1 & mask))
383 dw1 |= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL;
386 gen6_PIPE_CONTROL(r->builder, dw1, bo, 0, 0);
388 r->state.current_pipe_control_dw1 |= dw1;
389 r->state.deferred_pipe_control_dw1 &= ~dw1;
415 gen6_wa_pre_pipe_control(struct ilo_render *r, uint32_t dw1);
|
| ilo_render_gen7.c | 48 const uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL; local
52 r->state.deferred_pipe_control_dw1 |= dw1;
67 const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_STALL | local
72 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
73 ilo_render_pipe_control(r, dw1);
86 const uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL; local
90 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
91 ilo_render_pipe_control(r, dw1);
105 const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH | local
128 const uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL | local
163 const uint32_t dw1 = GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL; local
189 const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_STALL; local
[all...] |
| /external/mesa3d/src/gallium/drivers/ilo/shader/ |
| toy_compiler_disasm.c | 296 disasm_inst_decode_dw1_low_gen6(struct disasm_inst *inst, uint32_t dw1)
300 inst->dst.base.file = GEN_EXTRACT(dw1, GEN6_INST_DST_FILE);
301 inst->dst.base.type = GEN_EXTRACT(dw1, GEN6_INST_DST_TYPE);
302 inst->src0.base.file = GEN_EXTRACT(dw1, GEN6_INST_SRC0_FILE);
303 inst->src0.base.type = GEN_EXTRACT(dw1, GEN6_INST_SRC0_TYPE);
304 inst->src1.base.file = GEN_EXTRACT(dw1, GEN6_INST_SRC1_FILE);
305 inst->src1.base.type = GEN_EXTRACT(dw1, GEN6_INST_SRC1_TYPE);
308 inst->nib_ctrl = (bool) (dw1 & GEN7_INST_NIBCTRL);
312 disasm_inst_decode_dw1_low_gen8(struct disasm_inst *inst, uint32_t dw1)
316 inst->flag_subreg = GEN_EXTRACT(dw1, GEN8_INST_FLAG_SUBREG)
[all...] |
| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| sb_bc_decoder.cpp | 34 uint32_t dw1 = dw[i+1]; local
37 if ((dw1 >> 29) & 1) { // CF_ALU
42 CF_WORD1_EG(dw1).get_CF_INST() :
43 CF_WORD1_R6R7(dw1).get_CF_INST();
59 CF_WORD1_EG w1(dw1);
71 CF_WORD1_CM w1(dw1);
86 CF_WORD1_R6R7 w1(dw1);
112 uint32_t dw1 = dw[i++]; local
125 CF_ALU_WORD1_R6 w1(dw1);
139 CF_ALU_WORD1_R7EGCM w1(dw1);
178 uint32_t dw1 = dw[i++]; local
232 uint32_t dw1 = dw[i++]; local
293 uint32_t dw1 = dw[i++]; local
407 uint32_t dw1 = dw[i+1]; local
495 uint32_t dw1 = dw[i+1]; local
527 uint32_t dw1 = dw[i+1]; local
[all...] |
