1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/SystemZMCTargetDesc.h" 11 #include "llvm/ADT/STLExtras.h" 12 #include "llvm/MC/MCContext.h" 13 #include "llvm/MC/MCExpr.h" 14 #include "llvm/MC/MCInst.h" 15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 16 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 17 #include "llvm/MC/MCStreamer.h" 18 #include "llvm/MC/MCSubtargetInfo.h" 19 #include "llvm/Support/TargetRegistry.h" 20 21 using namespace llvm; 22 23 // Return true if Expr is in the range [MinValue, MaxValue]. 24 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) { 25 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) { 26 int64_t Value = CE->getValue(); 27 return Value >= MinValue && Value <= MaxValue; 28 } 29 return false; 30 } 31 32 namespace { 33 enum RegisterKind { 34 GR32Reg, 35 GRH32Reg, 36 GR64Reg, 37 GR128Reg, 38 ADDR32Reg, 39 ADDR64Reg, 40 FP32Reg, 41 FP64Reg, 42 FP128Reg, 43 VR32Reg, 44 VR64Reg, 45 VR128Reg 46 }; 47 48 enum MemoryKind { 49 BDMem, 50 BDXMem, 51 BDLMem, 52 BDVMem 53 }; 54 55 class SystemZOperand : public MCParsedAsmOperand { 56 public: 57 private: 58 enum OperandKind { 59 KindInvalid, 60 KindToken, 61 KindReg, 62 KindAccessReg, 63 KindImm, 64 KindImmTLS, 65 KindMem 66 }; 67 68 OperandKind Kind; 69 SMLoc StartLoc, EndLoc; 70 71 // A string of length Length, starting at Data. 72 struct TokenOp { 73 const char *Data; 74 unsigned Length; 75 }; 76 77 // LLVM register Num, which has kind Kind. In some ways it might be 78 // easier for this class to have a register bank (general, floating-point 79 // or access) and a raw register number (0-15). This would postpone the 80 // interpretation of the operand to the add*() methods and avoid the need 81 // for context-dependent parsing. However, we do things the current way 82 // because of the virtual getReg() method, which needs to distinguish 83 // between (say) %r0 used as a single register and %r0 used as a pair. 84 // Context-dependent parsing can also give us slightly better error 85 // messages when invalid pairs like %r1 are used. 86 struct RegOp { 87 RegisterKind Kind; 88 unsigned Num; 89 }; 90 91 // Base + Disp + Index, where Base and Index are LLVM registers or 0. 92 // MemKind says what type of memory this is and RegKind says what type 93 // the base register has (ADDR32Reg or ADDR64Reg). Length is the operand 94 // length for D(L,B)-style operands, otherwise it is null. 95 struct MemOp { 96 unsigned Base : 12; 97 unsigned Index : 12; 98 unsigned MemKind : 4; 99 unsigned RegKind : 4; 100 const MCExpr *Disp; 101 const MCExpr *Length; 102 }; 103 104 // Imm is an immediate operand, and Sym is an optional TLS symbol 105 // for use with a __tls_get_offset marker relocation. 106 struct ImmTLSOp { 107 const MCExpr *Imm; 108 const MCExpr *Sym; 109 }; 110 111 union { 112 TokenOp Token; 113 RegOp Reg; 114 unsigned AccessReg; 115 const MCExpr *Imm; 116 ImmTLSOp ImmTLS; 117 MemOp Mem; 118 }; 119 120 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 121 // Add as immediates when possible. Null MCExpr = 0. 122 if (!Expr) 123 Inst.addOperand(MCOperand::createImm(0)); 124 else if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) 125 Inst.addOperand(MCOperand::createImm(CE->getValue())); 126 else 127 Inst.addOperand(MCOperand::createExpr(Expr)); 128 } 129 130 public: 131 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc) 132 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {} 133 134 // Create particular kinds of operand. 135 static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc, 136 SMLoc EndLoc) { 137 return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc); 138 } 139 static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) { 140 auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc); 141 Op->Token.Data = Str.data(); 142 Op->Token.Length = Str.size(); 143 return Op; 144 } 145 static std::unique_ptr<SystemZOperand> 146 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { 147 auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc); 148 Op->Reg.Kind = Kind; 149 Op->Reg.Num = Num; 150 return Op; 151 } 152 static std::unique_ptr<SystemZOperand> 153 createAccessReg(unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { 154 auto Op = make_unique<SystemZOperand>(KindAccessReg, StartLoc, EndLoc); 155 Op->AccessReg = Num; 156 return Op; 157 } 158 static std::unique_ptr<SystemZOperand> 159 createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) { 160 auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc); 161 Op->Imm = Expr; 162 return Op; 163 } 164 static std::unique_ptr<SystemZOperand> 165 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, 166 const MCExpr *Disp, unsigned Index, const MCExpr *Length, 167 SMLoc StartLoc, SMLoc EndLoc) { 168 auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc); 169 Op->Mem.MemKind = MemKind; 170 Op->Mem.RegKind = RegKind; 171 Op->Mem.Base = Base; 172 Op->Mem.Index = Index; 173 Op->Mem.Disp = Disp; 174 Op->Mem.Length = Length; 175 return Op; 176 } 177 static std::unique_ptr<SystemZOperand> 178 createImmTLS(const MCExpr *Imm, const MCExpr *Sym, 179 SMLoc StartLoc, SMLoc EndLoc) { 180 auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc); 181 Op->ImmTLS.Imm = Imm; 182 Op->ImmTLS.Sym = Sym; 183 return Op; 184 } 185 186 // Token operands 187 bool isToken() const override { 188 return Kind == KindToken; 189 } 190 StringRef getToken() const { 191 assert(Kind == KindToken && "Not a token"); 192 return StringRef(Token.Data, Token.Length); 193 } 194 195 // Register operands. 196 bool isReg() const override { 197 return Kind == KindReg; 198 } 199 bool isReg(RegisterKind RegKind) const { 200 return Kind == KindReg && Reg.Kind == RegKind; 201 } 202 unsigned getReg() const override { 203 assert(Kind == KindReg && "Not a register"); 204 return Reg.Num; 205 } 206 207 // Access register operands. Access registers aren't exposed to LLVM 208 // as registers. 209 bool isAccessReg() const { 210 return Kind == KindAccessReg; 211 } 212 213 // Immediate operands. 214 bool isImm() const override { 215 return Kind == KindImm; 216 } 217 bool isImm(int64_t MinValue, int64_t MaxValue) const { 218 return Kind == KindImm && inRange(Imm, MinValue, MaxValue); 219 } 220 const MCExpr *getImm() const { 221 assert(Kind == KindImm && "Not an immediate"); 222 return Imm; 223 } 224 225 // Immediate operands with optional TLS symbol. 226 bool isImmTLS() const { 227 return Kind == KindImmTLS; 228 } 229 230 // Memory operands. 231 bool isMem() const override { 232 return Kind == KindMem; 233 } 234 bool isMem(MemoryKind MemKind) const { 235 return (Kind == KindMem && 236 (Mem.MemKind == MemKind || 237 // A BDMem can be treated as a BDXMem in which the index 238 // register field is 0. 239 (Mem.MemKind == BDMem && MemKind == BDXMem))); 240 } 241 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { 242 return isMem(MemKind) && Mem.RegKind == RegKind; 243 } 244 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { 245 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff); 246 } 247 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { 248 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287); 249 } 250 bool isMemDisp12Len8(RegisterKind RegKind) const { 251 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length, 1, 0x100); 252 } 253 void addBDVAddrOperands(MCInst &Inst, unsigned N) const { 254 assert(N == 3 && "Invalid number of operands"); 255 assert(isMem(BDVMem) && "Invalid operand type"); 256 Inst.addOperand(MCOperand::createReg(Mem.Base)); 257 addExpr(Inst, Mem.Disp); 258 Inst.addOperand(MCOperand::createReg(Mem.Index)); 259 } 260 261 // Override MCParsedAsmOperand. 262 SMLoc getStartLoc() const override { return StartLoc; } 263 SMLoc getEndLoc() const override { return EndLoc; } 264 void print(raw_ostream &OS) const override; 265 266 // Used by the TableGen code to add particular types of operand 267 // to an instruction. 268 void addRegOperands(MCInst &Inst, unsigned N) const { 269 assert(N == 1 && "Invalid number of operands"); 270 Inst.addOperand(MCOperand::createReg(getReg())); 271 } 272 void addAccessRegOperands(MCInst &Inst, unsigned N) const { 273 assert(N == 1 && "Invalid number of operands"); 274 assert(Kind == KindAccessReg && "Invalid operand type"); 275 Inst.addOperand(MCOperand::createImm(AccessReg)); 276 } 277 void addImmOperands(MCInst &Inst, unsigned N) const { 278 assert(N == 1 && "Invalid number of operands"); 279 addExpr(Inst, getImm()); 280 } 281 void addBDAddrOperands(MCInst &Inst, unsigned N) const { 282 assert(N == 2 && "Invalid number of operands"); 283 assert(isMem(BDMem) && "Invalid operand type"); 284 Inst.addOperand(MCOperand::createReg(Mem.Base)); 285 addExpr(Inst, Mem.Disp); 286 } 287 void addBDXAddrOperands(MCInst &Inst, unsigned N) const { 288 assert(N == 3 && "Invalid number of operands"); 289 assert(isMem(BDXMem) && "Invalid operand type"); 290 Inst.addOperand(MCOperand::createReg(Mem.Base)); 291 addExpr(Inst, Mem.Disp); 292 Inst.addOperand(MCOperand::createReg(Mem.Index)); 293 } 294 void addBDLAddrOperands(MCInst &Inst, unsigned N) const { 295 assert(N == 3 && "Invalid number of operands"); 296 assert(isMem(BDLMem) && "Invalid operand type"); 297 Inst.addOperand(MCOperand::createReg(Mem.Base)); 298 addExpr(Inst, Mem.Disp); 299 addExpr(Inst, Mem.Length); 300 } 301 void addImmTLSOperands(MCInst &Inst, unsigned N) const { 302 assert(N == 2 && "Invalid number of operands"); 303 assert(Kind == KindImmTLS && "Invalid operand type"); 304 addExpr(Inst, ImmTLS.Imm); 305 if (ImmTLS.Sym) 306 addExpr(Inst, ImmTLS.Sym); 307 } 308 309 // Used by the TableGen code to check for particular operand types. 310 bool isGR32() const { return isReg(GR32Reg); } 311 bool isGRH32() const { return isReg(GRH32Reg); } 312 bool isGRX32() const { return false; } 313 bool isGR64() const { return isReg(GR64Reg); } 314 bool isGR128() const { return isReg(GR128Reg); } 315 bool isADDR32() const { return isReg(ADDR32Reg); } 316 bool isADDR64() const { return isReg(ADDR64Reg); } 317 bool isADDR128() const { return false; } 318 bool isFP32() const { return isReg(FP32Reg); } 319 bool isFP64() const { return isReg(FP64Reg); } 320 bool isFP128() const { return isReg(FP128Reg); } 321 bool isVR32() const { return isReg(VR32Reg); } 322 bool isVR64() const { return isReg(VR64Reg); } 323 bool isVF128() const { return false; } 324 bool isVR128() const { return isReg(VR128Reg); } 325 bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); } 326 bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); } 327 bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); } 328 bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); } 329 bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); } 330 bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); } 331 bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); } 332 bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); } 333 bool isU1Imm() const { return isImm(0, 1); } 334 bool isU2Imm() const { return isImm(0, 3); } 335 bool isU3Imm() const { return isImm(0, 7); } 336 bool isU4Imm() const { return isImm(0, 15); } 337 bool isU6Imm() const { return isImm(0, 63); } 338 bool isU8Imm() const { return isImm(0, 255); } 339 bool isS8Imm() const { return isImm(-128, 127); } 340 bool isU12Imm() const { return isImm(0, 4095); } 341 bool isU16Imm() const { return isImm(0, 65535); } 342 bool isS16Imm() const { return isImm(-32768, 32767); } 343 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); } 344 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); } 345 }; 346 347 class SystemZAsmParser : public MCTargetAsmParser { 348 #define GET_ASSEMBLER_HEADER 349 #include "SystemZGenAsmMatcher.inc" 350 351 private: 352 MCAsmParser &Parser; 353 enum RegisterGroup { 354 RegGR, 355 RegFP, 356 RegV, 357 RegAccess 358 }; 359 struct Register { 360 RegisterGroup Group; 361 unsigned Num; 362 SMLoc StartLoc, EndLoc; 363 }; 364 365 bool parseRegister(Register &Reg); 366 367 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, 368 bool IsAddress = false); 369 370 OperandMatchResultTy parseRegister(OperandVector &Operands, 371 RegisterGroup Group, const unsigned *Regs, 372 RegisterKind Kind); 373 374 bool parseAddress(unsigned &Base, const MCExpr *&Disp, 375 unsigned &Index, bool &IsVector, const MCExpr *&Length, 376 const unsigned *Regs, RegisterKind RegKind); 377 378 OperandMatchResultTy parseAddress(OperandVector &Operands, 379 MemoryKind MemKind, const unsigned *Regs, 380 RegisterKind RegKind); 381 382 OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal, 383 int64_t MaxVal, bool AllowTLS); 384 385 bool parseOperand(OperandVector &Operands, StringRef Mnemonic); 386 387 public: 388 SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, 389 const MCInstrInfo &MII, 390 const MCTargetOptions &Options) 391 : MCTargetAsmParser(Options, sti), Parser(parser) { 392 MCAsmParserExtension::Initialize(Parser); 393 394 // Alias the .word directive to .short. 395 parser.addAliasForDirective(".word", ".short"); 396 397 // Initialize the set of available features. 398 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); 399 } 400 401 // Override MCTargetAsmParser. 402 bool ParseDirective(AsmToken DirectiveID) override; 403 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 404 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 405 SMLoc NameLoc, OperandVector &Operands) override; 406 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 407 OperandVector &Operands, MCStreamer &Out, 408 uint64_t &ErrorInfo, 409 bool MatchingInlineAsm) override; 410 411 // Used by the TableGen code to parse particular operand types. 412 OperandMatchResultTy parseGR32(OperandVector &Operands) { 413 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg); 414 } 415 OperandMatchResultTy parseGRH32(OperandVector &Operands) { 416 return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg); 417 } 418 OperandMatchResultTy parseGRX32(OperandVector &Operands) { 419 llvm_unreachable("GRX32 should only be used for pseudo instructions"); 420 } 421 OperandMatchResultTy parseGR64(OperandVector &Operands) { 422 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg); 423 } 424 OperandMatchResultTy parseGR128(OperandVector &Operands) { 425 return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg); 426 } 427 OperandMatchResultTy parseADDR32(OperandVector &Operands) { 428 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg); 429 } 430 OperandMatchResultTy parseADDR64(OperandVector &Operands) { 431 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg); 432 } 433 OperandMatchResultTy parseADDR128(OperandVector &Operands) { 434 llvm_unreachable("Shouldn't be used as an operand"); 435 } 436 OperandMatchResultTy parseFP32(OperandVector &Operands) { 437 return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg); 438 } 439 OperandMatchResultTy parseFP64(OperandVector &Operands) { 440 return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg); 441 } 442 OperandMatchResultTy parseFP128(OperandVector &Operands) { 443 return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg); 444 } 445 OperandMatchResultTy parseVR32(OperandVector &Operands) { 446 return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg); 447 } 448 OperandMatchResultTy parseVR64(OperandVector &Operands) { 449 return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg); 450 } 451 OperandMatchResultTy parseVF128(OperandVector &Operands) { 452 llvm_unreachable("Shouldn't be used as an operand"); 453 } 454 OperandMatchResultTy parseVR128(OperandVector &Operands) { 455 return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg); 456 } 457 OperandMatchResultTy parseBDAddr32(OperandVector &Operands) { 458 return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg); 459 } 460 OperandMatchResultTy parseBDAddr64(OperandVector &Operands) { 461 return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg); 462 } 463 OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) { 464 return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg); 465 } 466 OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) { 467 return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg); 468 } 469 OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) { 470 return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg); 471 } 472 OperandMatchResultTy parseAccessReg(OperandVector &Operands); 473 OperandMatchResultTy parsePCRel16(OperandVector &Operands) { 474 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false); 475 } 476 OperandMatchResultTy parsePCRel32(OperandVector &Operands) { 477 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false); 478 } 479 OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) { 480 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true); 481 } 482 OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) { 483 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true); 484 } 485 }; 486 } // end anonymous namespace 487 488 #define GET_REGISTER_MATCHER 489 #define GET_SUBTARGET_FEATURE_NAME 490 #define GET_MATCHER_IMPLEMENTATION 491 #include "SystemZGenAsmMatcher.inc" 492 493 void SystemZOperand::print(raw_ostream &OS) const { 494 llvm_unreachable("Not implemented"); 495 } 496 497 // Parse one register of the form %<prefix><number>. 498 bool SystemZAsmParser::parseRegister(Register &Reg) { 499 Reg.StartLoc = Parser.getTok().getLoc(); 500 501 // Eat the % prefix. 502 if (Parser.getTok().isNot(AsmToken::Percent)) 503 return Error(Parser.getTok().getLoc(), "register expected"); 504 Parser.Lex(); 505 506 // Expect a register name. 507 if (Parser.getTok().isNot(AsmToken::Identifier)) 508 return Error(Reg.StartLoc, "invalid register"); 509 510 // Check that there's a prefix. 511 StringRef Name = Parser.getTok().getString(); 512 if (Name.size() < 2) 513 return Error(Reg.StartLoc, "invalid register"); 514 char Prefix = Name[0]; 515 516 // Treat the rest of the register name as a register number. 517 if (Name.substr(1).getAsInteger(10, Reg.Num)) 518 return Error(Reg.StartLoc, "invalid register"); 519 520 // Look for valid combinations of prefix and number. 521 if (Prefix == 'r' && Reg.Num < 16) 522 Reg.Group = RegGR; 523 else if (Prefix == 'f' && Reg.Num < 16) 524 Reg.Group = RegFP; 525 else if (Prefix == 'v' && Reg.Num < 32) 526 Reg.Group = RegV; 527 else if (Prefix == 'a' && Reg.Num < 16) 528 Reg.Group = RegAccess; 529 else 530 return Error(Reg.StartLoc, "invalid register"); 531 532 Reg.EndLoc = Parser.getTok().getLoc(); 533 Parser.Lex(); 534 return false; 535 } 536 537 // Parse a register of group Group. If Regs is nonnull, use it to map 538 // the raw register number to LLVM numbering, with zero entries 539 // indicating an invalid register. IsAddress says whether the 540 // register appears in an address context. Allow FP Group if expecting 541 // RegV Group, since the f-prefix yields the FP group even while used 542 // with vector instructions. 543 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group, 544 const unsigned *Regs, bool IsAddress) { 545 if (parseRegister(Reg)) 546 return true; 547 if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV)) 548 return Error(Reg.StartLoc, "invalid operand for instruction"); 549 if (Regs && Regs[Reg.Num] == 0) 550 return Error(Reg.StartLoc, "invalid register pair"); 551 if (Reg.Num == 0 && IsAddress) 552 return Error(Reg.StartLoc, "%r0 used in an address"); 553 if (Regs) 554 Reg.Num = Regs[Reg.Num]; 555 return false; 556 } 557 558 // Parse a register and add it to Operands. The other arguments are as above. 559 SystemZAsmParser::OperandMatchResultTy 560 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group, 561 const unsigned *Regs, RegisterKind Kind) { 562 if (Parser.getTok().isNot(AsmToken::Percent)) 563 return MatchOperand_NoMatch; 564 565 Register Reg; 566 bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg); 567 if (parseRegister(Reg, Group, Regs, IsAddress)) 568 return MatchOperand_ParseFail; 569 570 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num, 571 Reg.StartLoc, Reg.EndLoc)); 572 return MatchOperand_Success; 573 } 574 575 // Parse a memory operand into Base, Disp, Index and Length. 576 // Regs maps asm register numbers to LLVM register numbers and RegKind 577 // says what kind of address register we're using (ADDR32Reg or ADDR64Reg). 578 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp, 579 unsigned &Index, bool &IsVector, 580 const MCExpr *&Length, const unsigned *Regs, 581 RegisterKind RegKind) { 582 // Parse the displacement, which must always be present. 583 if (getParser().parseExpression(Disp)) 584 return true; 585 586 // Parse the optional base and index. 587 Index = 0; 588 Base = 0; 589 IsVector = false; 590 Length = nullptr; 591 if (getLexer().is(AsmToken::LParen)) { 592 Parser.Lex(); 593 594 if (getLexer().is(AsmToken::Percent)) { 595 // Parse the first register and decide whether it's a base or an index. 596 Register Reg; 597 if (parseRegister(Reg)) 598 return true; 599 if (Reg.Group == RegV) { 600 // A vector index register. The base register is optional. 601 IsVector = true; 602 Index = SystemZMC::VR128Regs[Reg.Num]; 603 } else if (Reg.Group == RegGR) { 604 if (Reg.Num == 0) 605 return Error(Reg.StartLoc, "%r0 used in an address"); 606 // If the are two registers, the first one is the index and the 607 // second is the base. 608 if (getLexer().is(AsmToken::Comma)) 609 Index = Regs[Reg.Num]; 610 else 611 Base = Regs[Reg.Num]; 612 } else 613 return Error(Reg.StartLoc, "invalid address register"); 614 } else { 615 // Parse the length. 616 if (getParser().parseExpression(Length)) 617 return true; 618 } 619 620 // Check whether there's a second register. It's the base if so. 621 if (getLexer().is(AsmToken::Comma)) { 622 Parser.Lex(); 623 Register Reg; 624 if (parseRegister(Reg, RegGR, Regs, RegKind)) 625 return true; 626 Base = Reg.Num; 627 } 628 629 // Consume the closing bracket. 630 if (getLexer().isNot(AsmToken::RParen)) 631 return Error(Parser.getTok().getLoc(), "unexpected token in address"); 632 Parser.Lex(); 633 } 634 return false; 635 } 636 637 // Parse a memory operand and add it to Operands. The other arguments 638 // are as above. 639 SystemZAsmParser::OperandMatchResultTy 640 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind, 641 const unsigned *Regs, RegisterKind RegKind) { 642 SMLoc StartLoc = Parser.getTok().getLoc(); 643 unsigned Base, Index; 644 bool IsVector; 645 const MCExpr *Disp; 646 const MCExpr *Length; 647 if (parseAddress(Base, Disp, Index, IsVector, Length, Regs, RegKind)) 648 return MatchOperand_ParseFail; 649 650 if (IsVector && MemKind != BDVMem) { 651 Error(StartLoc, "invalid use of vector addressing"); 652 return MatchOperand_ParseFail; 653 } 654 655 if (!IsVector && MemKind == BDVMem) { 656 Error(StartLoc, "vector index required in address"); 657 return MatchOperand_ParseFail; 658 } 659 660 if (Index && MemKind != BDXMem && MemKind != BDVMem) { 661 Error(StartLoc, "invalid use of indexed addressing"); 662 return MatchOperand_ParseFail; 663 } 664 665 if (Length && MemKind != BDLMem) { 666 Error(StartLoc, "invalid use of length addressing"); 667 return MatchOperand_ParseFail; 668 } 669 670 if (!Length && MemKind == BDLMem) { 671 Error(StartLoc, "missing length in address"); 672 return MatchOperand_ParseFail; 673 } 674 675 SMLoc EndLoc = 676 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 677 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp, 678 Index, Length, StartLoc, 679 EndLoc)); 680 return MatchOperand_Success; 681 } 682 683 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) { 684 return true; 685 } 686 687 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, 688 SMLoc &EndLoc) { 689 Register Reg; 690 if (parseRegister(Reg)) 691 return true; 692 if (Reg.Group == RegGR) 693 RegNo = SystemZMC::GR64Regs[Reg.Num]; 694 else if (Reg.Group == RegFP) 695 RegNo = SystemZMC::FP64Regs[Reg.Num]; 696 else if (Reg.Group == RegV) 697 RegNo = SystemZMC::VR128Regs[Reg.Num]; 698 else 699 // FIXME: Access registers aren't modelled as LLVM registers yet. 700 return Error(Reg.StartLoc, "invalid operand for instruction"); 701 StartLoc = Reg.StartLoc; 702 EndLoc = Reg.EndLoc; 703 return false; 704 } 705 706 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info, 707 StringRef Name, SMLoc NameLoc, 708 OperandVector &Operands) { 709 Operands.push_back(SystemZOperand::createToken(Name, NameLoc)); 710 711 // Read the remaining operands. 712 if (getLexer().isNot(AsmToken::EndOfStatement)) { 713 // Read the first operand. 714 if (parseOperand(Operands, Name)) { 715 Parser.eatToEndOfStatement(); 716 return true; 717 } 718 719 // Read any subsequent operands. 720 while (getLexer().is(AsmToken::Comma)) { 721 Parser.Lex(); 722 if (parseOperand(Operands, Name)) { 723 Parser.eatToEndOfStatement(); 724 return true; 725 } 726 } 727 if (getLexer().isNot(AsmToken::EndOfStatement)) { 728 SMLoc Loc = getLexer().getLoc(); 729 Parser.eatToEndOfStatement(); 730 return Error(Loc, "unexpected token in argument list"); 731 } 732 } 733 734 // Consume the EndOfStatement. 735 Parser.Lex(); 736 return false; 737 } 738 739 bool SystemZAsmParser::parseOperand(OperandVector &Operands, 740 StringRef Mnemonic) { 741 // Check if the current operand has a custom associated parser, if so, try to 742 // custom parse the operand, or fallback to the general approach. 743 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 744 if (ResTy == MatchOperand_Success) 745 return false; 746 747 // If there wasn't a custom match, try the generic matcher below. Otherwise, 748 // there was a match, but an error occurred, in which case, just return that 749 // the operand parsing failed. 750 if (ResTy == MatchOperand_ParseFail) 751 return true; 752 753 // Check for a register. All real register operands should have used 754 // a context-dependent parse routine, which gives the required register 755 // class. The code is here to mop up other cases, like those where 756 // the instruction isn't recognized. 757 if (Parser.getTok().is(AsmToken::Percent)) { 758 Register Reg; 759 if (parseRegister(Reg)) 760 return true; 761 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc)); 762 return false; 763 } 764 765 // The only other type of operand is an immediate or address. As above, 766 // real address operands should have used a context-dependent parse routine, 767 // so we treat any plain expression as an immediate. 768 SMLoc StartLoc = Parser.getTok().getLoc(); 769 unsigned Base, Index; 770 bool IsVector; 771 const MCExpr *Expr, *Length; 772 if (parseAddress(Base, Expr, Index, IsVector, Length, SystemZMC::GR64Regs, 773 ADDR64Reg)) 774 return true; 775 776 SMLoc EndLoc = 777 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 778 if (Base || Index || Length) 779 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc)); 780 else 781 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); 782 return false; 783 } 784 785 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 786 OperandVector &Operands, 787 MCStreamer &Out, 788 uint64_t &ErrorInfo, 789 bool MatchingInlineAsm) { 790 MCInst Inst; 791 unsigned MatchResult; 792 793 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, 794 MatchingInlineAsm); 795 switch (MatchResult) { 796 case Match_Success: 797 Inst.setLoc(IDLoc); 798 Out.EmitInstruction(Inst, getSTI()); 799 return false; 800 801 case Match_MissingFeature: { 802 assert(ErrorInfo && "Unknown missing feature!"); 803 // Special case the error message for the very common case where only 804 // a single subtarget feature is missing 805 std::string Msg = "instruction requires:"; 806 uint64_t Mask = 1; 807 for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) { 808 if (ErrorInfo & Mask) { 809 Msg += " "; 810 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 811 } 812 Mask <<= 1; 813 } 814 return Error(IDLoc, Msg); 815 } 816 817 case Match_InvalidOperand: { 818 SMLoc ErrorLoc = IDLoc; 819 if (ErrorInfo != ~0ULL) { 820 if (ErrorInfo >= Operands.size()) 821 return Error(IDLoc, "too few operands for instruction"); 822 823 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc(); 824 if (ErrorLoc == SMLoc()) 825 ErrorLoc = IDLoc; 826 } 827 return Error(ErrorLoc, "invalid operand for instruction"); 828 } 829 830 case Match_MnemonicFail: 831 return Error(IDLoc, "invalid instruction"); 832 } 833 834 llvm_unreachable("Unexpected match type"); 835 } 836 837 SystemZAsmParser::OperandMatchResultTy 838 SystemZAsmParser::parseAccessReg(OperandVector &Operands) { 839 if (Parser.getTok().isNot(AsmToken::Percent)) 840 return MatchOperand_NoMatch; 841 842 Register Reg; 843 if (parseRegister(Reg, RegAccess, nullptr)) 844 return MatchOperand_ParseFail; 845 846 Operands.push_back(SystemZOperand::createAccessReg(Reg.Num, 847 Reg.StartLoc, 848 Reg.EndLoc)); 849 return MatchOperand_Success; 850 } 851 852 SystemZAsmParser::OperandMatchResultTy 853 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal, 854 int64_t MaxVal, bool AllowTLS) { 855 MCContext &Ctx = getContext(); 856 MCStreamer &Out = getStreamer(); 857 const MCExpr *Expr; 858 SMLoc StartLoc = Parser.getTok().getLoc(); 859 if (getParser().parseExpression(Expr)) 860 return MatchOperand_NoMatch; 861 862 // For consistency with the GNU assembler, treat immediates as offsets 863 // from ".". 864 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) { 865 int64_t Value = CE->getValue(); 866 if ((Value & 1) || Value < MinVal || Value > MaxVal) { 867 Error(StartLoc, "offset out of range"); 868 return MatchOperand_ParseFail; 869 } 870 MCSymbol *Sym = Ctx.createTempSymbol(); 871 Out.EmitLabel(Sym); 872 const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, 873 Ctx); 874 Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx); 875 } 876 877 // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol. 878 const MCExpr *Sym = nullptr; 879 if (AllowTLS && getLexer().is(AsmToken::Colon)) { 880 Parser.Lex(); 881 882 if (Parser.getTok().isNot(AsmToken::Identifier)) { 883 Error(Parser.getTok().getLoc(), "unexpected token"); 884 return MatchOperand_ParseFail; 885 } 886 887 MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None; 888 StringRef Name = Parser.getTok().getString(); 889 if (Name == "tls_gdcall") 890 Kind = MCSymbolRefExpr::VK_TLSGD; 891 else if (Name == "tls_ldcall") 892 Kind = MCSymbolRefExpr::VK_TLSLDM; 893 else { 894 Error(Parser.getTok().getLoc(), "unknown TLS tag"); 895 return MatchOperand_ParseFail; 896 } 897 Parser.Lex(); 898 899 if (Parser.getTok().isNot(AsmToken::Colon)) { 900 Error(Parser.getTok().getLoc(), "unexpected token"); 901 return MatchOperand_ParseFail; 902 } 903 Parser.Lex(); 904 905 if (Parser.getTok().isNot(AsmToken::Identifier)) { 906 Error(Parser.getTok().getLoc(), "unexpected token"); 907 return MatchOperand_ParseFail; 908 } 909 910 StringRef Identifier = Parser.getTok().getString(); 911 Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier), 912 Kind, Ctx); 913 Parser.Lex(); 914 } 915 916 SMLoc EndLoc = 917 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 918 919 if (AllowTLS) 920 Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym, 921 StartLoc, EndLoc)); 922 else 923 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); 924 925 return MatchOperand_Success; 926 } 927 928 // Force static initialization. 929 extern "C" void LLVMInitializeSystemZAsmParser() { 930 RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget); 931 } 932