| /external/mesa3d/src/intel/isl/ |
| isl_gen4.h | 36 enum isl_tiling tiling,
42 enum isl_tiling tiling,
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| isl_gen6.h | 36 enum isl_tiling tiling,
42 enum isl_tiling tiling,
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| isl_gen8.h | 36 enum isl_tiling tiling,
42 enum isl_tiling tiling,
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| isl_gen4.c | 30 enum isl_tiling tiling,
43 enum isl_tiling tiling,
50 assert(!isl_tiling_is_std_y(tiling));
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| isl_gen9.h | 36 enum isl_tiling tiling,
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| isl_gen7.h | 41 enum isl_tiling tiling,
47 enum isl_tiling tiling,
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| isl_gen9.c | 30 * for the standard tiling formats Yf and Ys.
35 enum isl_tiling tiling,
41 assert(isl_tiling_is_std_y(tiling));
44 const uint32_t is_Ys = tiling == ISL_TILING_Ys;
49 * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
59 * Surface Layout and Tiling > 2D Surfaces > 2D/CUBE Alignment
86 * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
102 enum isl_tiling tiling,
124 * Surface Layout and Tiling > 2D Surfaces]:
146 * Tiling" section under Common Surface Formats for the table o
[all...] |
| isl_gen6.c | 30 enum isl_tiling tiling,
59 if (tiling == ISL_TILING_LINEAR)
71 enum isl_tiling tiling,
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| isl.c | 128 enum isl_tiling tiling,
135 if (tiling != ISL_TILING_LINEAR && !isl_is_pow2(format_bpb)) {
139 * This really only works on legacy X and Y tiling formats.
141 assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0);
143 return isl_tiling_get_info(dev, tiling, format_bpb / 3, tile_info);
146 switch (tiling) {
190 bool is_Ys = tiling == ISL_TILING_Ys;
203 * 128bpb format. The tiling has the same physical dimensions as
204 * Y-tiling but actually has two HiZ columns per Y-tiled column
1192 enum isl_tiling tiling; local
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| isl_gen7.c | 30 enum isl_tiling tiling,
86 if (tiling == ISL_TILING_LINEAR)
174 * @brief Filter out tiling flags that are incompatible with the surface.
181 * (ISL_SURF_USAGE_DISPLAY_BIT), then this function filters out all tiling
209 /* Separate stencil requires W tiling, and W tiling requires separate
245 /* FINISHME[SKL]: Y tiling for display surfaces */
262 * As usual, though, stencil is special and requires W-tiling.
272 /* Y tiling is illegal. From the Ivybridge PRM, Vol4 Part1 2.12.2.1,
323 enum isl_tiling tiling)
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| isl_gen8.c | 30 enum isl_tiling tiling,
185 enum isl_tiling tiling,
193 assert(!isl_tiling_is_std_y(tiling));
223 * - Vertical alignment restrictions vary with memory tiling type:
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| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| intel_regions.c | 111 uint32_t tiling, drm_intel_bo *buffer)
125 region->tiling = tiling;
133 uint32_t tiling,
147 &tiling, &aligned_pitch, flags);
152 aligned_pitch, tiling, buffer);
183 uint32_t bit_6_swizzle, tiling; local
188 ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle);
190 fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",
197 width, height, pitch, tiling, buffer)
218 uint32_t bit_6_swizzle, tiling; local
291 uint32_t tiling = region->tiling; local
324 uint32_t tiling = region->tiling; local
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| intel_tiled_memcpy.h | 46 uint32_t tiling,
55 uint32_t tiling,
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| intel_pixel_read.c | 132 (irb->mt->tiling != I915_TILING_X &&
133 irb->mt->tiling != I915_TILING_Y)) {
180 "mesa_format=0x%x tiling=%d "
183 format, type, rb->Format, irb->mt->tiling,
194 irb->mt->tiling,
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| /external/vulkan-validation-layers/loader/ |
| extensions.h | 36 VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags,
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| extensions.c | 35 VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags,
44 unwrapped_phys_dev, format, type, tiling, usage, flags,
51 VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags,
72 phys_dev->phys_dev, format, type, tiling, usage, flags,
77 phys_dev->phys_dev, format, type, tiling, usage, flags,
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| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_screen.h | 50 boolean tiling; member in struct:i915_screen::__anon27691
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| /external/mesa3d/src/gallium/drivers/ilo/core/ |
| ilo_builder_blt.h | 57 enum gen_surface_tiling tiling; member in struct:gen6_blt_xy_bo
174 if (dst->tiling != GEN6_TILING_NONE) {
177 assert(dst->tiling == GEN6_TILING_X || dst->tiling == GEN6_TILING_Y);
178 dst_align = (dst->tiling == GEN6_TILING_Y) ? 128 : 512;
278 if (dst->tiling != GEN6_TILING_NONE) {
281 assert(dst->tiling == GEN6_TILING_X || dst->tiling == GEN6_TILING_Y);
282 dst_align = (dst->tiling == GEN6_TILING_Y) ? 128 : 512;
287 if (src->tiling != GEN6_TILING_NONE)
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| intel_winsys.h | 157 enum intel_tiling_mode *tiling,
161 * Export \p bo as a winsys handle for inter-process sharing. \p tiling and
167 enum intel_tiling_mode tiling,
219 * Set the tiling of \p bo. The info is used by GTT mapping and bo export.
223 enum intel_tiling_mode tiling,
231 * but the caller needs to handle tiling or swizzling manually if the bo is
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| /external/libdrm/tegra/ |
| tegra.h | 61 struct drm_tegra_bo_tiling *tiling);
63 const struct drm_tegra_bo_tiling *tiling);
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| /external/mesa3d/src/gallium/drivers/vc4/ |
| vc4_resource.h | 45 uint8_t tiling; member in struct:vc4_resource_slice
51 uint8_t tiling; member in struct:vc4_surface
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_mipmap_tree.h | 94 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, mesa_format format, unsigned width, unsigned tiling, unsigned target);
101 unsigned tiling);
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| /hardware/intel/img/psb_video/src/ |
| psb_surface.h | 93 #define SET_SURFACE_INFO_tiling(psb_surface, tiling) psb_surface->extra_info[7] = (uint32_t) tiling;
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| /external/skia/src/gpu/vk/ |
| GrVkImage.h | 98 void setNewResource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling);
115 Resource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling)
120 , fImageTiling(tiling) {}
155 BorrowedResource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling)
156 : Resource(image, alloc, tiling) {
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| /external/mesa3d/src/gallium/drivers/ilo/ |
| ilo_resource.c | 220 winsys_to_surface_tiling(enum intel_tiling_mode tiling)
222 switch (tiling) {
230 assert(!"unknown tiling");
236 surface_to_winsys_tiling(enum gen_surface_tiling tiling)
238 switch (tiling) {
246 assert(!"unknown tiling");
300 /* set the tiling for transfer and export */
301 if (bo && (tex->image.tiling == GEN6_TILING_X ||
302 tex->image.tiling == GEN6_TILING_Y)) {
303 const enum intel_tiling_mode tiling local
442 enum intel_tiling_mode tiling; local
579 enum intel_tiling_mode tiling; local
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