| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| x86-64-equ.d | 2 #name: evex equates
|
| avx512f-nondef.s | 12 # vpmovdb %zmm6, 2032(%rdx) # with unset EVEX.B bit
14 # vpmovdb %zmm6, 2032(%rdx) # with set EVEX.B bit - we should get (bad) operand
|
| x86-64-avx512f-nondef.s | 12 # vpmovdb %zmm6, 2032(%rdx) # with unset EVEX.B bit
14 # vpmovdb %zmm6, 2032(%rdx) # with set EVEX.B bit - we should get (bad) operand
|
| i386.exp | 198 run_dump_test "evex-lig256"
199 run_dump_test "evex-lig512"
200 run_dump_test "evex-lig256-intel"
201 run_dump_test "evex-lig512-intel"
202 run_dump_test "evex-wig1"
203 run_dump_test "evex-wig1-intel"
565 run_dump_test "x86-64-evex-lig256"
566 run_dump_test "x86-64-evex-lig512"
567 run_dump_test "x86-64-evex-lig256-intel"
568 run_dump_test "x86-64-evex-lig512-intel
[all...] |
| evex-wig.s | 1 # Check EVEX WIG instructions
|
| x86-64-evex-wig.s | 1 # Check EVEX WIG instructions
|
| evex-wig1-intel.d | 4 #source: evex-wig.s
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.h | 37 #define rFromEVEX2of4(evex) (((~(evex)) & 0x80) >> 7)
38 #define xFromEVEX2of4(evex) (((~(evex)) & 0x40) >> 6)
39 #define bFromEVEX2of4(evex) (((~(evex)) & 0x20) >> 5)
40 #define r2FromEVEX2of4(evex) (((~(evex)) & 0x10) >> 4)
41 #define mmFromEVEX2of4(evex) ((evex) & 0x3
[all...] |
| X86DisassemblerDecoderCommon.h | 130 ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
131 ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
132 ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
133 ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
134 ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \
135 ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \
136 ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \
137 ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \
138 ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \
139 ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")
[all...] |
| X86DisassemblerDecoder.cpp | 457 dbgprintf(insn, "Couldn't read second byte of EVEX prefix");
462 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
479 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
483 dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix");
496 dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrAVX512.td | 581 AVX512AIi8Base, EVEX;
588 addr:$dst)]>, EVEX;
597 []>, EVEX_K, EVEX;
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| i386-opc.h | 480 /* insn has EVEX prefix:
481 1: 512bit EVEX prefix.
482 2: 128bit EVEX prefix.
483 3: 256bit EVEX prefix.
484 4: Length-ignored (LIG) EVEX prefix.
490 EVex,
596 unsigned int evex:3; member in struct:i386_opcode_modifier
|
| ChangeLog-2013 | 290 * i386-dis-evex.h (evex_table): Updated.
420 * i386-dis-evex.h: New.
445 (EVEX enum): New.
595 (struct vex): Add fields evex, r, v, mask_register_specifier,
609 (x86_64_table): Add escape to evex-table.
610 (reg_table): Include reg_table evex-entries from
611 i386-dis-evex.h. Fix prefetchwt1 instruction.
619 (intel_operand_size): Support EVEX, new modes and sizes.
633 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
645 (EVex): New
[all...] |
| ChangeLog | 15 * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
29 * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
354 * i386-dis-evex.h: Updated.
392 * i386-dis-evex.h: Add new instructions (prefixes bellow).
499 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
|
| i386-dis.c | 490 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
493 /* Similar to x_mode, but with different EVEX mem shifts. */
498 in EVEX. */
3109 int evex; member in struct:__anon116484
[all...] |
| /toolchain/binutils/binutils-2.25/gas/doc/ |
| c-i386.texi | 254 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
255 EVEX instructions with 128bit vector length, which is the default.
257 encode LIG EVEX instructions with 256bit and 512bit vector length,
265 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
266 EVEX instructions with evex.w = 0, which is the default.
267 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
268 evex.w = 1.
322 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
323 of EVEX instruction with 00, which is the default
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86BaseInfo.h | 471 // VEX_EVEX - Specifies that this instruction use EVEX form which provides
475 EVEX = 3 << EncodingShift,
519 // - 11 LIG (but, in insn encoding, leave VEX.L and EVEX.L in zeros.
526 // EVEX_Z - Set if this instruction has EVEX.Z field set.
530 // EVEX_L2 - Set if this instruction has EVEX.L' field set.
534 // EVEX_B - Set if this instruction has EVEX.B field set.
|
| X86MCCodeEmitter.cpp | 166 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) &&
167 "Compressed 8-bit displacement is only valid for EVEX inst.");
359 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
506 // Try EVEX compressed 8-bit displacement first; if failed, fall back to
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/ |
| ChangeLog-2013 | 533 * gas/i386/evex-lig.s: New.
534 * gas/i386/evex-lig256-intel.d: New.
535 * gas/i386/evex-lig256.d: New.
536 * gas/i386/evex-lig512-intel.d: New.
537 * gas/i386/evex-lig512.d: New.
538 * gas/i386/evex-wig.s: New.
539 * gas/i386/evex-wig1-intel.d: New.
540 * gas/i386/evex-wig1.d: New.
560 * gas/i386/x86-64-evex-lig.s: New.
561 * gas/i386/x86-64-evex-lig256-intel.d: New
[all...] |
| ChangeLog | 750 * gas/i386/evex-lig256-intel.d: Updated.
751 * gas/i386/evex-lig256.d: Updated.
752 * gas/i386/evex-lig512-intel.d: Updated.
753 * gas/i386/evex-lig512-intel.d: Updated.
754 * gas/i386/x86-64-evex-lig256-intel.d: Updated.
755 * gas/i386/x86-64-evex-lig256.d: Updated.
756 * gas/i386/x86-64-evex-lig512-intel.d: Updated.
757 * gas/i386/x86-64-evex-lig512-intel.d: Updated.
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/share/man/man1/ |
| x86_64-w64-mingw32-as.1 | [all...] |
| /toolchain/binutils/binutils-2.25/gas/ |
| ChangeLog-2013 | 656 (vex_prefix): Size of bytes increased to 4 to support EVEX
680 (process_immext): Adjust to properly handle EVEX.
681 (md_assemble): Add EVEX encoding support.
684 (check_VecOperands): Support EVEX features.
690 (build_modrm_byte): Handle EVEX.
691 (output_insn): Adjust to properly handle EVEX case.
693 (output_disp): Support compressed disp8*N evex feature.
696 (i386_immediate): Handle EVEX features.
699 (i386_att_operand): Handle EVEX features.
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-i386.c | 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
608 /* Encode scalar EVEX LIG instructions with specific vector length. */
616 /* Encode EVEX WIG instructions with specific evex.w. */
623 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
[all...] |
| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.cpp | 127 VEX = 1, XOP = 2, EVEX = 3
288 if (Encoding == X86Local::EVEX) {
375 /// eof EVEX
[all...] |
| /external/llvm/test/MC/Disassembler/X86/ |
| x86-64.txt | 424 # Try all combinations of EVEX.x and REX.b:
|
