1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the Emit routines for the SelectionDAG class, which creates 11 // MachineInstrs based on the decisions of the SelectionDAG instruction 12 // selection. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "InstrEmitter.h" 17 #include "SDNodeDbgValue.h" 18 #include "llvm/ADT/Statistic.h" 19 #include "llvm/CodeGen/MachineConstantPool.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/StackMaps.h" 24 #include "llvm/IR/DataLayout.h" 25 #include "llvm/IR/DebugInfo.h" 26 #include "llvm/Support/Debug.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/MathExtras.h" 29 #include "llvm/Target/TargetInstrInfo.h" 30 #include "llvm/Target/TargetLowering.h" 31 #include "llvm/Target/TargetSubtargetInfo.h" 32 using namespace llvm; 33 34 #define DEBUG_TYPE "instr-emitter" 35 36 /// MinRCSize - Smallest register class we allow when constraining virtual 37 /// registers. If satisfying all register class constraints would require 38 /// using a smaller register class, emit a COPY to a new virtual register 39 /// instead. 40 const unsigned MinRCSize = 4; 41 42 /// CountResults - The results of target nodes have register or immediate 43 /// operands first, then an optional chain, and optional glue operands (which do 44 /// not go into the resulting MachineInstr). 45 unsigned InstrEmitter::CountResults(SDNode *Node) { 46 unsigned N = Node->getNumValues(); 47 while (N && Node->getValueType(N - 1) == MVT::Glue) 48 --N; 49 if (N && Node->getValueType(N - 1) == MVT::Other) 50 --N; // Skip over chain result. 51 return N; 52 } 53 54 /// countOperands - The inputs to target nodes have any actual inputs first, 55 /// followed by an optional chain operand, then an optional glue operand. 56 /// Compute the number of actual operands that will go into the resulting 57 /// MachineInstr. 58 /// 59 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding 60 /// the chain and glue. These operands may be implicit on the machine instr. 61 static unsigned countOperands(SDNode *Node, unsigned NumExpUses, 62 unsigned &NumImpUses) { 63 unsigned N = Node->getNumOperands(); 64 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 65 --N; 66 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 67 --N; // Ignore chain if it exists. 68 69 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses. 70 NumImpUses = N - NumExpUses; 71 for (unsigned I = N; I > NumExpUses; --I) { 72 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1))) 73 continue; 74 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1))) 75 if (TargetRegisterInfo::isPhysicalRegister(RN->getReg())) 76 continue; 77 NumImpUses = N - I; 78 break; 79 } 80 81 return N; 82 } 83 84 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 85 /// implicit physical register output. 86 void InstrEmitter:: 87 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 88 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 89 unsigned VRBase = 0; 90 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 91 // Just use the input register directly! 92 SDValue Op(Node, ResNo); 93 if (IsClone) 94 VRBaseMap.erase(Op); 95 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 96 (void)isNew; // Silence compiler warning. 97 assert(isNew && "Node emitted out of order - early"); 98 return; 99 } 100 101 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 102 // the CopyToReg'd destination register instead of creating a new vreg. 103 bool MatchReg = true; 104 const TargetRegisterClass *UseRC = nullptr; 105 MVT VT = Node->getSimpleValueType(ResNo); 106 107 // Stick to the preferred register classes for legal types. 108 if (TLI->isTypeLegal(VT)) 109 UseRC = TLI->getRegClassFor(VT); 110 111 if (!IsClone && !IsCloned) 112 for (SDNode *User : Node->uses()) { 113 bool Match = true; 114 if (User->getOpcode() == ISD::CopyToReg && 115 User->getOperand(2).getNode() == Node && 116 User->getOperand(2).getResNo() == ResNo) { 117 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 118 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 119 VRBase = DestReg; 120 Match = false; 121 } else if (DestReg != SrcReg) 122 Match = false; 123 } else { 124 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 125 SDValue Op = User->getOperand(i); 126 if (Op.getNode() != Node || Op.getResNo() != ResNo) 127 continue; 128 MVT VT = Node->getSimpleValueType(Op.getResNo()); 129 if (VT == MVT::Other || VT == MVT::Glue) 130 continue; 131 Match = false; 132 if (User->isMachineOpcode()) { 133 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); 134 const TargetRegisterClass *RC = nullptr; 135 if (i+II.getNumDefs() < II.getNumOperands()) { 136 RC = TRI->getAllocatableClass( 137 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 138 } 139 if (!UseRC) 140 UseRC = RC; 141 else if (RC) { 142 const TargetRegisterClass *ComRC = 143 TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy); 144 // If multiple uses expect disjoint register classes, we emit 145 // copies in AddRegisterOperand. 146 if (ComRC) 147 UseRC = ComRC; 148 } 149 } 150 } 151 } 152 MatchReg &= Match; 153 if (VRBase) 154 break; 155 } 156 157 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; 158 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 159 160 // Figure out the register class to create for the destreg. 161 if (VRBase) { 162 DstRC = MRI->getRegClass(VRBase); 163 } else if (UseRC) { 164 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 165 DstRC = UseRC; 166 } else { 167 DstRC = TLI->getRegClassFor(VT); 168 } 169 170 // If all uses are reading from the src physical register and copying the 171 // register is either impossible or very expensive, then don't create a copy. 172 if (MatchReg && SrcRC->getCopyCost() < 0) { 173 VRBase = SrcReg; 174 } else { 175 // Create the reg, emit the copy. 176 VRBase = MRI->createVirtualRegister(DstRC); 177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 178 VRBase).addReg(SrcReg); 179 } 180 181 SDValue Op(Node, ResNo); 182 if (IsClone) 183 VRBaseMap.erase(Op); 184 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 185 (void)isNew; // Silence compiler warning. 186 assert(isNew && "Node emitted out of order - early"); 187 } 188 189 /// getDstOfCopyToRegUse - If the only use of the specified result number of 190 /// node is a CopyToReg, return its destination register. Return 0 otherwise. 191 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 192 unsigned ResNo) const { 193 if (!Node->hasOneUse()) 194 return 0; 195 196 SDNode *User = *Node->use_begin(); 197 if (User->getOpcode() == ISD::CopyToReg && 198 User->getOperand(2).getNode() == Node && 199 User->getOperand(2).getResNo() == ResNo) { 200 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 201 if (TargetRegisterInfo::isVirtualRegister(Reg)) 202 return Reg; 203 } 204 return 0; 205 } 206 207 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, 208 MachineInstrBuilder &MIB, 209 const MCInstrDesc &II, 210 bool IsClone, bool IsCloned, 211 DenseMap<SDValue, unsigned> &VRBaseMap) { 212 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 213 "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 214 215 unsigned NumResults = CountResults(Node); 216 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 217 // If the specific node value is only used by a CopyToReg and the dest reg 218 // is a vreg in the same register class, use the CopyToReg'd destination 219 // register instead of creating a new vreg. 220 unsigned VRBase = 0; 221 const TargetRegisterClass *RC = 222 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 223 // Always let the value type influence the used register class. The 224 // constraints on the instruction may be too lax to represent the value 225 // type correctly. For example, a 64-bit float (X86::FR64) can't live in 226 // the 32-bit float super-class (X86::FR32). 227 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { 228 const TargetRegisterClass *VTRC = 229 TLI->getRegClassFor(Node->getSimpleValueType(i)); 230 if (RC) 231 VTRC = TRI->getCommonSubClass(RC, VTRC); 232 if (VTRC) 233 RC = VTRC; 234 } 235 236 if (II.OpInfo[i].isOptionalDef()) { 237 // Optional def must be a physical register. 238 unsigned NumResults = CountResults(Node); 239 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 240 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 241 MIB.addReg(VRBase, RegState::Define); 242 } 243 244 if (!VRBase && !IsClone && !IsCloned) 245 for (SDNode *User : Node->uses()) { 246 if (User->getOpcode() == ISD::CopyToReg && 247 User->getOperand(2).getNode() == Node && 248 User->getOperand(2).getResNo() == i) { 249 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 250 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 251 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 252 if (RegRC == RC) { 253 VRBase = Reg; 254 MIB.addReg(VRBase, RegState::Define); 255 break; 256 } 257 } 258 } 259 } 260 261 // Create the result registers for this node and add the result regs to 262 // the machine instruction. 263 if (VRBase == 0) { 264 assert(RC && "Isn't a register operand!"); 265 VRBase = MRI->createVirtualRegister(RC); 266 MIB.addReg(VRBase, RegState::Define); 267 } 268 269 // If this def corresponds to a result of the SDNode insert the VRBase into 270 // the lookup map. 271 if (i < NumResults) { 272 SDValue Op(Node, i); 273 if (IsClone) 274 VRBaseMap.erase(Op); 275 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 276 (void)isNew; // Silence compiler warning. 277 assert(isNew && "Node emitted out of order - early"); 278 } 279 } 280 } 281 282 /// getVR - Return the virtual register corresponding to the specified result 283 /// of the specified node. 284 unsigned InstrEmitter::getVR(SDValue Op, 285 DenseMap<SDValue, unsigned> &VRBaseMap) { 286 if (Op.isMachineOpcode() && 287 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 288 // Add an IMPLICIT_DEF instruction before every use. 289 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 290 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc 291 // does not include operand register class info. 292 if (!VReg) { 293 const TargetRegisterClass *RC = 294 TLI->getRegClassFor(Op.getSimpleValueType()); 295 VReg = MRI->createVirtualRegister(RC); 296 } 297 BuildMI(*MBB, InsertPos, Op.getDebugLoc(), 298 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 299 return VReg; 300 } 301 302 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 303 assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 304 return I->second; 305 } 306 307 308 /// AddRegisterOperand - Add the specified register as an operand to the 309 /// specified machine instr. Insert register copies if the register is 310 /// not in the required register class. 311 void 312 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, 313 SDValue Op, 314 unsigned IIOpNum, 315 const MCInstrDesc *II, 316 DenseMap<SDValue, unsigned> &VRBaseMap, 317 bool IsDebug, bool IsClone, bool IsCloned) { 318 assert(Op.getValueType() != MVT::Other && 319 Op.getValueType() != MVT::Glue && 320 "Chain and glue operands should occur at end of operand list!"); 321 // Get/emit the operand. 322 unsigned VReg = getVR(Op, VRBaseMap); 323 324 const MCInstrDesc &MCID = MIB->getDesc(); 325 bool isOptDef = IIOpNum < MCID.getNumOperands() && 326 MCID.OpInfo[IIOpNum].isOptionalDef(); 327 328 // If the instruction requires a register in a different class, create 329 // a new virtual register and copy the value into it, but first attempt to 330 // shrink VReg's register class within reason. For example, if VReg == GR32 331 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. 332 if (II) { 333 const TargetRegisterClass *DstRC = nullptr; 334 if (IIOpNum < II->getNumOperands()) 335 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 336 assert((!DstRC || TargetRegisterInfo::isVirtualRegister(VReg)) && 337 "Expected VReg"); 338 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { 339 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 340 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), 341 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 342 VReg = NewVReg; 343 } 344 } 345 346 // If this value has only one use, that use is a kill. This is a 347 // conservative approximation. InstrEmitter does trivial coalescing 348 // with CopyFromReg nodes, so don't emit kill flags for them. 349 // Avoid kill flags on Schedule cloned nodes, since there will be 350 // multiple uses. 351 // Tied operands are never killed, so we need to check that. And that 352 // means we need to determine the index of the operand. 353 bool isKill = Op.hasOneUse() && 354 Op.getNode()->getOpcode() != ISD::CopyFromReg && 355 !IsDebug && 356 !(IsClone || IsCloned); 357 if (isKill) { 358 unsigned Idx = MIB->getNumOperands(); 359 while (Idx > 0 && 360 MIB->getOperand(Idx-1).isReg() && 361 MIB->getOperand(Idx-1).isImplicit()) 362 --Idx; 363 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; 364 if (isTied) 365 isKill = false; 366 } 367 368 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | 369 getDebugRegState(IsDebug)); 370 } 371 372 /// AddOperand - Add the specified operand to the specified machine instr. II 373 /// specifies the instruction information for the node, and IIOpNum is the 374 /// operand number (in the II) that we are adding. 375 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB, 376 SDValue Op, 377 unsigned IIOpNum, 378 const MCInstrDesc *II, 379 DenseMap<SDValue, unsigned> &VRBaseMap, 380 bool IsDebug, bool IsClone, bool IsCloned) { 381 if (Op.isMachineOpcode()) { 382 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, 383 IsDebug, IsClone, IsCloned); 384 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 385 MIB.addImm(C->getSExtValue()); 386 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 387 MIB.addFPImm(F->getConstantFPValue()); 388 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 389 // Turn additional physreg operands into implicit uses on non-variadic 390 // instructions. This is used by call and return instructions passing 391 // arguments in registers. 392 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic()); 393 MIB.addReg(R->getReg(), getImplRegState(Imp)); 394 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) { 395 MIB.addRegMask(RM->getRegMask()); 396 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 397 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(), 398 TGA->getTargetFlags()); 399 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 400 MIB.addMBB(BBNode->getBasicBlock()); 401 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 402 MIB.addFrameIndex(FI->getIndex()); 403 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 404 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags()); 405 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 406 int Offset = CP->getOffset(); 407 unsigned Align = CP->getAlignment(); 408 Type *Type = CP->getType(); 409 // MachineConstantPool wants an explicit alignment. 410 if (Align == 0) { 411 Align = MF->getDataLayout().getPrefTypeAlignment(Type); 412 if (Align == 0) { 413 // Alignment of vector types. FIXME! 414 Align = MF->getDataLayout().getTypeAllocSize(Type); 415 } 416 } 417 418 unsigned Idx; 419 MachineConstantPool *MCP = MF->getConstantPool(); 420 if (CP->isMachineConstantPoolEntry()) 421 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 422 else 423 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 424 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags()); 425 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 426 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags()); 427 } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) { 428 MIB.addSym(SymNode->getMCSymbol()); 429 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 430 MIB.addBlockAddress(BA->getBlockAddress(), 431 BA->getOffset(), 432 BA->getTargetFlags()); 433 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) { 434 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags()); 435 } else { 436 assert(Op.getValueType() != MVT::Other && 437 Op.getValueType() != MVT::Glue && 438 "Chain and glue operands should occur at end of operand list!"); 439 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, 440 IsDebug, IsClone, IsCloned); 441 } 442 } 443 444 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, 445 MVT VT, const DebugLoc &DL) { 446 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); 447 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); 448 449 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg 450 // within reason. 451 if (RC && RC != VRC) 452 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); 453 454 // VReg has been adjusted. It can be used with SubIdx operands now. 455 if (RC) 456 return VReg; 457 458 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual 459 // register instead. 460 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); 461 assert(RC && "No legal register class for VT supports that SubIdx"); 462 unsigned NewReg = MRI->createVirtualRegister(RC); 463 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) 464 .addReg(VReg); 465 return NewReg; 466 } 467 468 /// EmitSubregNode - Generate machine code for subreg nodes. 469 /// 470 void InstrEmitter::EmitSubregNode(SDNode *Node, 471 DenseMap<SDValue, unsigned> &VRBaseMap, 472 bool IsClone, bool IsCloned) { 473 unsigned VRBase = 0; 474 unsigned Opc = Node->getMachineOpcode(); 475 476 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 477 // the CopyToReg'd destination register instead of creating a new vreg. 478 for (SDNode *User : Node->uses()) { 479 if (User->getOpcode() == ISD::CopyToReg && 480 User->getOperand(2).getNode() == Node) { 481 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 482 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 483 VRBase = DestReg; 484 break; 485 } 486 } 487 } 488 489 if (Opc == TargetOpcode::EXTRACT_SUBREG) { 490 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no 491 // constraints on the %dst register, COPY can target all legal register 492 // classes. 493 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 494 const TargetRegisterClass *TRC = 495 TLI->getRegClassFor(Node->getSimpleValueType(0)); 496 497 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 498 MachineInstr *DefMI = MRI->getVRegDef(VReg); 499 unsigned SrcReg, DstReg, DefSubIdx; 500 if (DefMI && 501 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 502 SubIdx == DefSubIdx && 503 TRC == MRI->getRegClass(SrcReg)) { 504 // Optimize these: 505 // r1025 = s/zext r1024, 4 506 // r1026 = extract_subreg r1025, 4 507 // to a copy 508 // r1026 = copy r1024 509 VRBase = MRI->createVirtualRegister(TRC); 510 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 511 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); 512 MRI->clearKillFlags(SrcReg); 513 } else { 514 // VReg may not support a SubIdx sub-register, and we may need to 515 // constrain its register class or issue a COPY to a compatible register 516 // class. 517 VReg = ConstrainForSubReg(VReg, SubIdx, 518 Node->getOperand(0).getSimpleValueType(), 519 Node->getDebugLoc()); 520 521 // Create the destreg if it is missing. 522 if (VRBase == 0) 523 VRBase = MRI->createVirtualRegister(TRC); 524 525 // Create the extract_subreg machine instruction. 526 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 527 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); 528 } 529 } else if (Opc == TargetOpcode::INSERT_SUBREG || 530 Opc == TargetOpcode::SUBREG_TO_REG) { 531 SDValue N0 = Node->getOperand(0); 532 SDValue N1 = Node->getOperand(1); 533 SDValue N2 = Node->getOperand(2); 534 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 535 536 // Figure out the register class to create for the destreg. It should be 537 // the largest legal register class supporting SubIdx sub-registers. 538 // RegisterCoalescer will constrain it further if it decides to eliminate 539 // the INSERT_SUBREG instruction. 540 // 541 // %dst = INSERT_SUBREG %src, %sub, SubIdx 542 // 543 // is lowered by TwoAddressInstructionPass to: 544 // 545 // %dst = COPY %src 546 // %dst:SubIdx = COPY %sub 547 // 548 // There is no constraint on the %src register class. 549 // 550 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0)); 551 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); 552 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"); 553 554 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) 555 VRBase = MRI->createVirtualRegister(SRC); 556 557 // Create the insert_subreg or subreg_to_reg machine instruction. 558 MachineInstrBuilder MIB = 559 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase); 560 561 // If creating a subreg_to_reg, then the first input operand 562 // is an implicit value immediate, otherwise it's a register 563 if (Opc == TargetOpcode::SUBREG_TO_REG) { 564 const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 565 MIB.addImm(SD->getZExtValue()); 566 } else 567 AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false, 568 IsClone, IsCloned); 569 // Add the subregster being inserted 570 AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false, 571 IsClone, IsCloned); 572 MIB.addImm(SubIdx); 573 MBB->insert(InsertPos, MIB); 574 } else 575 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 576 577 SDValue Op(Node, 0); 578 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 579 (void)isNew; // Silence compiler warning. 580 assert(isNew && "Node emitted out of order - early"); 581 } 582 583 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 584 /// COPY_TO_REGCLASS is just a normal copy, except that the destination 585 /// register is constrained to be in a particular register class. 586 /// 587 void 588 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 589 DenseMap<SDValue, unsigned> &VRBaseMap) { 590 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 591 592 // Create the new VReg in the destination class and emit a copy. 593 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 594 const TargetRegisterClass *DstRC = 595 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); 596 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 597 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 598 NewVReg).addReg(VReg); 599 600 SDValue Op(Node, 0); 601 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 602 (void)isNew; // Silence compiler warning. 603 assert(isNew && "Node emitted out of order - early"); 604 } 605 606 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 607 /// 608 void InstrEmitter::EmitRegSequence(SDNode *Node, 609 DenseMap<SDValue, unsigned> &VRBaseMap, 610 bool IsClone, bool IsCloned) { 611 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue(); 612 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); 613 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC)); 614 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 615 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg); 616 unsigned NumOps = Node->getNumOperands(); 617 assert((NumOps & 1) == 1 && 618 "REG_SEQUENCE must have an odd number of operands!"); 619 for (unsigned i = 1; i != NumOps; ++i) { 620 SDValue Op = Node->getOperand(i); 621 if ((i & 1) == 0) { 622 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1)); 623 // Skip physical registers as they don't have a vreg to get and we'll 624 // insert copies for them in TwoAddressInstructionPass anyway. 625 if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 626 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 627 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 628 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 629 const TargetRegisterClass *SRC = 630 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); 631 if (SRC && SRC != RC) { 632 MRI->setRegClass(NewVReg, SRC); 633 RC = SRC; 634 } 635 } 636 } 637 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, 638 IsClone, IsCloned); 639 } 640 641 MBB->insert(InsertPos, MIB); 642 SDValue Op(Node, 0); 643 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 644 (void)isNew; // Silence compiler warning. 645 assert(isNew && "Node emitted out of order - early"); 646 } 647 648 /// EmitDbgValue - Generate machine instruction for a dbg_value node. 649 /// 650 MachineInstr * 651 InstrEmitter::EmitDbgValue(SDDbgValue *SD, 652 DenseMap<SDValue, unsigned> &VRBaseMap) { 653 uint64_t Offset = SD->getOffset(); 654 MDNode *Var = SD->getVariable(); 655 MDNode *Expr = SD->getExpression(); 656 DebugLoc DL = SD->getDebugLoc(); 657 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) && 658 "Expected inlined-at fields to agree"); 659 660 if (SD->getKind() == SDDbgValue::FRAMEIX) { 661 // Stack address; this needs to be lowered in target-dependent fashion. 662 // EmitTargetCodeForFrameDebugValue is responsible for allocation. 663 return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE)) 664 .addFrameIndex(SD->getFrameIx()) 665 .addImm(Offset) 666 .addMetadata(Var) 667 .addMetadata(Expr); 668 } 669 // Otherwise, we're going to create an instruction here. 670 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 671 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 672 if (SD->getKind() == SDDbgValue::SDNODE) { 673 SDNode *Node = SD->getSDNode(); 674 SDValue Op = SDValue(Node, SD->getResNo()); 675 // It's possible we replaced this SDNode with other(s) and therefore 676 // didn't generate code for it. It's better to catch these cases where 677 // they happen and transfer the debug info, but trying to guarantee that 678 // in all cases would be very fragile; this is a safeguard for any 679 // that were missed. 680 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 681 if (I==VRBaseMap.end()) 682 MIB.addReg(0U); // undef 683 else 684 AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 685 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false); 686 } else if (SD->getKind() == SDDbgValue::CONST) { 687 const Value *V = SD->getConst(); 688 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 689 if (CI->getBitWidth() > 64) 690 MIB.addCImm(CI); 691 else 692 MIB.addImm(CI->getSExtValue()); 693 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 694 MIB.addFPImm(CF); 695 } else { 696 // Could be an Undef. In any case insert an Undef so we can see what we 697 // dropped. 698 MIB.addReg(0U); 699 } 700 } else { 701 // Insert an Undef so we can see what we dropped. 702 MIB.addReg(0U); 703 } 704 705 // Indirect addressing is indicated by an Imm as the second parameter. 706 if (SD->isIndirect()) 707 MIB.addImm(Offset); 708 else { 709 assert(Offset == 0 && "direct value cannot have an offset"); 710 MIB.addReg(0U, RegState::Debug); 711 } 712 713 MIB.addMetadata(Var); 714 MIB.addMetadata(Expr); 715 716 return &*MIB; 717 } 718 719 /// EmitMachineNode - Generate machine code for a target-specific node and 720 /// needed dependencies. 721 /// 722 void InstrEmitter:: 723 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 724 DenseMap<SDValue, unsigned> &VRBaseMap) { 725 unsigned Opc = Node->getMachineOpcode(); 726 727 // Handle subreg insert/extract specially 728 if (Opc == TargetOpcode::EXTRACT_SUBREG || 729 Opc == TargetOpcode::INSERT_SUBREG || 730 Opc == TargetOpcode::SUBREG_TO_REG) { 731 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned); 732 return; 733 } 734 735 // Handle COPY_TO_REGCLASS specially. 736 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 737 EmitCopyToRegClassNode(Node, VRBaseMap); 738 return; 739 } 740 741 // Handle REG_SEQUENCE specially. 742 if (Opc == TargetOpcode::REG_SEQUENCE) { 743 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned); 744 return; 745 } 746 747 if (Opc == TargetOpcode::IMPLICIT_DEF) 748 // We want a unique VR for each IMPLICIT_DEF use. 749 return; 750 751 const MCInstrDesc &II = TII->get(Opc); 752 unsigned NumResults = CountResults(Node); 753 unsigned NumDefs = II.getNumDefs(); 754 const MCPhysReg *ScratchRegs = nullptr; 755 756 // Handle STACKMAP and PATCHPOINT specially and then use the generic code. 757 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) { 758 // Stackmaps do not have arguments and do not preserve their calling 759 // convention. However, to simplify runtime support, they clobber the same 760 // scratch registers as AnyRegCC. 761 unsigned CC = CallingConv::AnyReg; 762 if (Opc == TargetOpcode::PATCHPOINT) { 763 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos); 764 NumDefs = NumResults; 765 } 766 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC); 767 } 768 769 unsigned NumImpUses = 0; 770 unsigned NodeOperands = 771 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses); 772 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr; 773 #ifndef NDEBUG 774 unsigned NumMIOperands = NodeOperands + NumResults; 775 if (II.isVariadic()) 776 assert(NumMIOperands >= II.getNumOperands() && 777 "Too few operands for a variadic node!"); 778 else 779 assert(NumMIOperands >= II.getNumOperands() && 780 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + 781 NumImpUses && 782 "#operands for dag node doesn't match .td file!"); 783 #endif 784 785 // Create the new machine instruction. 786 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II); 787 788 // Add result register values for things that are defined by this 789 // instruction. 790 if (NumResults) 791 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap); 792 793 // Emit all of the actual operands of this instruction, adding them to the 794 // instruction as appropriate. 795 bool HasOptPRefs = NumDefs > NumResults; 796 assert((!HasOptPRefs || !HasPhysRegOuts) && 797 "Unable to cope with optional defs and phys regs defs!"); 798 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0; 799 for (unsigned i = NumSkip; i != NodeOperands; ++i) 800 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II, 801 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned); 802 803 // Add scratch registers as implicit def and early clobber 804 if (ScratchRegs) 805 for (unsigned i = 0; ScratchRegs[i]; ++i) 806 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | 807 RegState::EarlyClobber); 808 809 // Transfer all of the memory reference descriptions of this instruction. 810 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 811 cast<MachineSDNode>(Node)->memoperands_end()); 812 813 // Insert the instruction into position in the block. This needs to 814 // happen before any custom inserter hook is called so that the 815 // hook knows where in the block to insert the replacement code. 816 MBB->insert(InsertPos, MIB); 817 818 // The MachineInstr may also define physregs instead of virtregs. These 819 // physreg values can reach other instructions in different ways: 820 // 821 // 1. When there is a use of a Node value beyond the explicitly defined 822 // virtual registers, we emit a CopyFromReg for one of the implicitly 823 // defined physregs. This only happens when HasPhysRegOuts is true. 824 // 825 // 2. A CopyFromReg reading a physreg may be glued to this instruction. 826 // 827 // 3. A glued instruction may implicitly use a physreg. 828 // 829 // 4. A glued instruction may use a RegisterSDNode operand. 830 // 831 // Collect all the used physreg defs, and make sure that any unused physreg 832 // defs are marked as dead. 833 SmallVector<unsigned, 8> UsedRegs; 834 835 // Additional results must be physical register defs. 836 if (HasPhysRegOuts) { 837 for (unsigned i = NumDefs; i < NumResults; ++i) { 838 unsigned Reg = II.getImplicitDefs()[i - NumDefs]; 839 if (!Node->hasAnyUseOfValue(i)) 840 continue; 841 // This implicitly defined physreg has a use. 842 UsedRegs.push_back(Reg); 843 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 844 } 845 } 846 847 // Scan the glue chain for any used physregs. 848 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) { 849 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) { 850 if (F->getOpcode() == ISD::CopyFromReg) { 851 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); 852 continue; 853 } else if (F->getOpcode() == ISD::CopyToReg) { 854 // Skip CopyToReg nodes that are internal to the glue chain. 855 continue; 856 } 857 // Collect declared implicit uses. 858 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); 859 UsedRegs.append(MCID.getImplicitUses(), 860 MCID.getImplicitUses() + MCID.getNumImplicitUses()); 861 // In addition to declared implicit uses, we must also check for 862 // direct RegisterSDNode operands. 863 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i) 864 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) { 865 unsigned Reg = R->getReg(); 866 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 867 UsedRegs.push_back(Reg); 868 } 869 } 870 } 871 872 // Finally mark unused registers as dead. 873 if (!UsedRegs.empty() || II.getImplicitDefs()) 874 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI); 875 876 // Run post-isel target hook to adjust this instruction if needed. 877 if (II.hasPostISelHook()) 878 TLI->AdjustInstrPostInstrSelection(*MIB, Node); 879 } 880 881 /// EmitSpecialNode - Generate machine code for a target-independent node and 882 /// needed dependencies. 883 void InstrEmitter:: 884 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 885 DenseMap<SDValue, unsigned> &VRBaseMap) { 886 switch (Node->getOpcode()) { 887 default: 888 #ifndef NDEBUG 889 Node->dump(); 890 #endif 891 llvm_unreachable("This target-independent node should have been selected!"); 892 case ISD::EntryToken: 893 llvm_unreachable("EntryToken should have been excluded from the schedule!"); 894 case ISD::MERGE_VALUES: 895 case ISD::TokenFactor: // fall thru 896 break; 897 case ISD::CopyToReg: { 898 unsigned SrcReg; 899 SDValue SrcVal = Node->getOperand(2); 900 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 901 SrcReg = R->getReg(); 902 else 903 SrcReg = getVR(SrcVal, VRBaseMap); 904 905 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 906 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 907 break; 908 909 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 910 DestReg).addReg(SrcReg); 911 break; 912 } 913 case ISD::CopyFromReg: { 914 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 915 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 916 break; 917 } 918 case ISD::EH_LABEL: { 919 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 920 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 921 TII->get(TargetOpcode::EH_LABEL)).addSym(S); 922 break; 923 } 924 925 case ISD::LIFETIME_START: 926 case ISD::LIFETIME_END: { 927 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ? 928 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END; 929 930 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1)); 931 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp)) 932 .addFrameIndex(FI->getIndex()); 933 break; 934 } 935 936 case ISD::INLINEASM: { 937 unsigned NumOps = Node->getNumOperands(); 938 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 939 --NumOps; // Ignore the glue operand. 940 941 // Create the inline asm machine instruction. 942 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), 943 TII->get(TargetOpcode::INLINEASM)); 944 945 // Add the asm string as an external symbol operand. 946 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 947 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 948 MIB.addExternalSymbol(AsmStr); 949 950 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore 951 // bits. 952 int64_t ExtraInfo = 953 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))-> 954 getZExtValue(); 955 MIB.addImm(ExtraInfo); 956 957 // Remember to operand index of the group flags. 958 SmallVector<unsigned, 8> GroupIdx; 959 960 // Remember registers that are part of early-clobber defs. 961 SmallVector<unsigned, 8> ECRegs; 962 963 // Add all of the operand registers to the instruction. 964 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 965 unsigned Flags = 966 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 967 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 968 969 GroupIdx.push_back(MIB->getNumOperands()); 970 MIB.addImm(Flags); 971 ++i; // Skip the ID value. 972 973 switch (InlineAsm::getKind(Flags)) { 974 default: llvm_unreachable("Bad flags!"); 975 case InlineAsm::Kind_RegDef: 976 for (unsigned j = 0; j != NumVals; ++j, ++i) { 977 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 978 // FIXME: Add dead flags for physical and virtual registers defined. 979 // For now, mark physical register defs as implicit to help fast 980 // regalloc. This makes inline asm look a lot like calls. 981 MIB.addReg(Reg, RegState::Define | 982 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg))); 983 } 984 break; 985 case InlineAsm::Kind_RegDefEarlyClobber: 986 case InlineAsm::Kind_Clobber: 987 for (unsigned j = 0; j != NumVals; ++j, ++i) { 988 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 989 MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber | 990 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg))); 991 ECRegs.push_back(Reg); 992 } 993 break; 994 case InlineAsm::Kind_RegUse: // Use of register. 995 case InlineAsm::Kind_Imm: // Immediate. 996 case InlineAsm::Kind_Mem: // Addressing mode. 997 // The addressing mode has been selected, just add all of the 998 // operands to the machine instruction. 999 for (unsigned j = 0; j != NumVals; ++j, ++i) 1000 AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap, 1001 /*IsDebug=*/false, IsClone, IsCloned); 1002 1003 // Manually set isTied bits. 1004 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) { 1005 unsigned DefGroup = 0; 1006 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) { 1007 unsigned DefIdx = GroupIdx[DefGroup] + 1; 1008 unsigned UseIdx = GroupIdx.back() + 1; 1009 for (unsigned j = 0; j != NumVals; ++j) 1010 MIB->tieOperands(DefIdx + j, UseIdx + j); 1011 } 1012 } 1013 break; 1014 } 1015 } 1016 1017 // GCC inline assembly allows input operands to also be early-clobber 1018 // output operands (so long as the operand is written only after it's 1019 // used), but this does not match the semantics of our early-clobber flag. 1020 // If an early-clobber operand register is also an input operand register, 1021 // then remove the early-clobber flag. 1022 for (unsigned Reg : ECRegs) { 1023 if (MIB->readsRegister(Reg, TRI)) { 1024 MachineOperand *MO = MIB->findRegisterDefOperand(Reg, false, TRI); 1025 assert(MO && "No def operand for clobbered register?"); 1026 MO->setIsEarlyClobber(false); 1027 } 1028 } 1029 1030 // Get the mdnode from the asm if it exists and add it to the instruction. 1031 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 1032 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 1033 if (MD) 1034 MIB.addMetadata(MD); 1035 1036 MBB->insert(InsertPos, MIB); 1037 break; 1038 } 1039 } 1040 } 1041 1042 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting 1043 /// at the given position in the given block. 1044 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 1045 MachineBasicBlock::iterator insertpos) 1046 : MF(mbb->getParent()), MRI(&MF->getRegInfo()), 1047 TII(MF->getSubtarget().getInstrInfo()), 1048 TRI(MF->getSubtarget().getRegisterInfo()), 1049 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb), 1050 InsertPos(insertpos) {} 1051