| /external/llvm/lib/Target/Hexagon/ |
| HexagonBitTracker.h | 50 struct ExtType {
54 ExtType() : Type(0), Width(0) {}
55 ExtType(char t, uint16_t w) : Type(t), Width(w) {}
58 typedef DenseMap<unsigned, ExtType> RegExtMap;
|
| HexagonISelDAGToDAG.cpp | 250 ISD::LoadExtType ExtType = LD->getExtensionType();
251 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
304 auto getExt64 = [this,ExtType] (MachineSDNode *N, const SDLoc &dl)
306 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) {
311 if (ExtType == ISD::SEXTLOAD)
322 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) {
[all...] |
| /external/capstone/arch/AArch64/ |
| AArch64InstPrinter.c | 809 AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val);
815 if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) {
819 ExtType == AArch64_AM_UXTX) ||
821 ExtType == AArch64_AM_UXTW) ) {
835 SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType));
838 switch(ExtType) {
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| evntcons.h | 65 USHORT ExtType;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 204 ISD::LoadExtType ExtType = LD->getExtensionType();
205 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
513 ISD::LoadExtType ExtType = LD->getExtensionType();
602 switch (ExtType) {
[all...] |
| LegalizeIntegerTypes.cpp | 478 ISD::LoadExtType ExtType =
481 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
[all...] |
| LegalizeVectorTypes.cpp | [all...] |
| TargetLowering.cpp | [all...] |
| SelectionDAG.cpp | 233 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) {
234 switch (ExtType) {
[all...] |
| DAGCombiner.cpp | 217 ISD::NodeType ExtType);
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 414 ISD::LoadExtType ExtType =
417 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
[all...] |
| LegalizeVectorTypes.cpp | 708 ISD::LoadExtType ExtType = LD->getExtensionType();
720 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
727 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
[all...] |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | 143 ISD::NodeType ExtType);
688 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
693 return DAG.getExtLoad(ExtType, dl, PVT,
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | [all...] |
| AArch64InstrInfo.cpp | [all...] |
| AArch64FastISel.cpp | 54 AArch64_AM::ShiftExtendType ExtType;
65 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend),
69 void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; }
70 AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; }
174 AArch64_AM::ShiftExtendType ExtType,
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | [all...] |
| SIISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 555 ISD::LoadExtType ExtType = LN->getExtensionType();
726 if (ExtType == ISD::SEXTLOAD) {
728 } else if (ExtType == ISD::ZEXTLOAD) {
730 } else if (ExtType == ISD::EXTLOAD) {
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | [all...] |
