1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares codegen opcodes and related utilities. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_ISDOPCODES_H 15 #define LLVM_CODEGEN_ISDOPCODES_H 16 17 namespace llvm { 18 19 /// ISD namespace - This namespace contains an enum which represents all of the 20 /// SelectionDAG node types and value types. 21 /// 22 namespace ISD { 23 24 //===--------------------------------------------------------------------===// 25 /// ISD::NodeType enum - This enum defines the target-independent operators 26 /// for a SelectionDAG. 27 /// 28 /// Targets may also define target-dependent operator codes for SDNodes. For 29 /// example, on x86, these are the enum values in the X86ISD namespace. 30 /// Targets should aim to use target-independent operators to model their 31 /// instruction sets as much as possible, and only use target-dependent 32 /// operators when they have special requirements. 33 /// 34 /// Finally, during and after selection proper, SNodes may use special 35 /// operator codes that correspond directly with MachineInstr opcodes. These 36 /// are used to represent selected instructions. See the isMachineOpcode() 37 /// and getMachineOpcode() member functions of SDNode. 38 /// 39 enum NodeType { 40 // DELETED_NODE - This is an illegal value that is used to catch 41 // errors. This opcode is not a legal opcode for any node. 42 DELETED_NODE, 43 44 // EntryToken - This is the marker used to indicate the start of the region. 45 EntryToken, 46 47 // TokenFactor - This node takes multiple tokens as input and produces a 48 // single token result. This is used to represent the fact that the operand 49 // operators are independent of each other. 50 TokenFactor, 51 52 // AssertSext, AssertZext - These nodes record if a register contains a 53 // value that has already been zero or sign extended from a narrower type. 54 // These nodes take two operands. The first is the node that has already 55 // been extended, and the second is a value type node indicating the width 56 // of the extension 57 AssertSext, AssertZext, 58 59 // Various leaf nodes. 60 BasicBlock, VALUETYPE, CONDCODE, Register, 61 Constant, ConstantFP, 62 GlobalAddress, GlobalTLSAddress, FrameIndex, 63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress, 64 65 // The address of the GOT 66 GLOBAL_OFFSET_TABLE, 67 68 // FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and 69 // llvm.returnaddress on the DAG. These nodes take one operand, the index 70 // of the frame or return address to return. An index of zero corresponds 71 // to the current function's frame or return address, an index of one to the 72 // parent's frame or return address, and so on. 73 FRAMEADDR, RETURNADDR, 74 75 // FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to 76 // first (possible) on-stack argument. This is needed for correct stack 77 // adjustment during unwind. 78 FRAME_TO_ARGS_OFFSET, 79 80 // RESULT, OUTCHAIN = EXCEPTIONADDR(INCHAIN) - This node represents the 81 // address of the exception block on entry to an landing pad block. 82 EXCEPTIONADDR, 83 84 // RESULT, OUTCHAIN = LSDAADDR(INCHAIN) - This node represents the 85 // address of the Language Specific Data Area for the enclosing function. 86 LSDAADDR, 87 88 // RESULT, OUTCHAIN = EHSELECTION(INCHAIN, EXCEPTION) - This node represents 89 // the selection index of the exception thrown. 90 EHSELECTION, 91 92 // OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 93 // 'eh_return' gcc dwarf builtin, which is used to return from 94 // exception. The general meaning is: adjust stack by OFFSET and pass 95 // execution to HANDLER. Many platform-related details also :) 96 EH_RETURN, 97 98 // RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) 99 // This corresponds to the eh.sjlj.setjmp intrinsic. 100 // It takes an input chain and a pointer to the jump buffer as inputs 101 // and returns an outchain. 102 EH_SJLJ_SETJMP, 103 104 // OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) 105 // This corresponds to the eh.sjlj.longjmp intrinsic. 106 // It takes an input chain and a pointer to the jump buffer as inputs 107 // and returns an outchain. 108 EH_SJLJ_LONGJMP, 109 110 // OUTCHAIN = EH_SJLJ_DISPATCHSETUP(INCHAIN, setjmpval) 111 // This corresponds to the eh.sjlj.dispatchsetup intrinsic. It takes an 112 // input chain and the value returning from setjmp as inputs and returns an 113 // outchain. By default, this does nothing. Targets can lower this to unwind 114 // setup code if needed. 115 EH_SJLJ_DISPATCHSETUP, 116 117 // TargetConstant* - Like Constant*, but the DAG does not do any folding, 118 // simplification, or lowering of the constant. They are used for constants 119 // which are known to fit in the immediate fields of their users, or for 120 // carrying magic numbers which are not values which need to be materialized 121 // in registers. 122 TargetConstant, 123 TargetConstantFP, 124 125 // TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or 126 // anything else with this node, and this is valid in the target-specific 127 // dag, turning into a GlobalAddress operand. 128 TargetGlobalAddress, 129 TargetGlobalTLSAddress, 130 TargetFrameIndex, 131 TargetJumpTable, 132 TargetConstantPool, 133 TargetExternalSymbol, 134 TargetBlockAddress, 135 136 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) 137 /// This node represents a target intrinsic function with no side effects. 138 /// The first operand is the ID number of the intrinsic from the 139 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The 140 /// node returns the result of the intrinsic. 141 INTRINSIC_WO_CHAIN, 142 143 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) 144 /// This node represents a target intrinsic function with side effects that 145 /// returns a result. The first operand is a chain pointer. The second is 146 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The 147 /// operands to the intrinsic follow. The node has two results, the result 148 /// of the intrinsic and an output chain. 149 INTRINSIC_W_CHAIN, 150 151 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) 152 /// This node represents a target intrinsic function with side effects that 153 /// does not return a result. The first operand is a chain pointer. The 154 /// second is the ID number of the intrinsic from the llvm::Intrinsic 155 /// namespace. The operands to the intrinsic follow. 156 INTRINSIC_VOID, 157 158 // CopyToReg - This node has three operands: a chain, a register number to 159 // set to this value, and a value. 160 CopyToReg, 161 162 // CopyFromReg - This node indicates that the input value is a virtual or 163 // physical register that is defined outside of the scope of this 164 // SelectionDAG. The register is available from the RegisterSDNode object. 165 CopyFromReg, 166 167 // UNDEF - An undefined node 168 UNDEF, 169 170 // EXTRACT_ELEMENT - This is used to get the lower or upper (determined by 171 // a Constant, which is required to be operand #1) half of the integer or 172 // float value specified as operand #0. This is only for use before 173 // legalization, for values that will be broken into multiple registers. 174 EXTRACT_ELEMENT, 175 176 // BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. Given 177 // two values of the same integer value type, this produces a value twice as 178 // big. Like EXTRACT_ELEMENT, this can only be used before legalization. 179 BUILD_PAIR, 180 181 // MERGE_VALUES - This node takes multiple discrete operands and returns 182 // them all as its individual results. This nodes has exactly the same 183 // number of inputs and outputs. This node is useful for some pieces of the 184 // code generator that want to think about a single node with multiple 185 // results, not multiple nodes. 186 MERGE_VALUES, 187 188 // Simple integer binary arithmetic operators. 189 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, 190 191 // SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing 192 // a signed/unsigned value of type i[2*N], and return the full value as 193 // two results, each of type iN. 194 SMUL_LOHI, UMUL_LOHI, 195 196 // SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 197 // remainder result. 198 SDIVREM, UDIVREM, 199 200 // CARRY_FALSE - This node is used when folding other nodes, 201 // like ADDC/SUBC, which indicate the carry result is always false. 202 CARRY_FALSE, 203 204 // Carry-setting nodes for multiple precision addition and subtraction. 205 // These nodes take two operands of the same value type, and produce two 206 // results. The first result is the normal add or sub result, the second 207 // result is the carry flag result. 208 ADDC, SUBC, 209 210 // Carry-using nodes for multiple precision addition and subtraction. These 211 // nodes take three operands: The first two are the normal lhs and rhs to 212 // the add or sub, and the third is the input carry flag. These nodes 213 // produce two results; the normal result of the add or sub, and the output 214 // carry flag. These nodes both read and write a carry flag to allow them 215 // to them to be chained together for add and sub of arbitrarily large 216 // values. 217 ADDE, SUBE, 218 219 // RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. 220 // These nodes take two operands: the normal LHS and RHS to the add. They 221 // produce two results: the normal result of the add, and a boolean that 222 // indicates if an overflow occurred (*not* a flag, because it may be stored 223 // to memory, etc.). If the type of the boolean is not i1 then the high 224 // bits conform to getBooleanContents. 225 // These nodes are generated from the llvm.[su]add.with.overflow intrinsics. 226 SADDO, UADDO, 227 228 // Same for subtraction 229 SSUBO, USUBO, 230 231 // Same for multiplication 232 SMULO, UMULO, 233 234 // Simple binary floating point operators. 235 FADD, FSUB, FMUL, FMA, FDIV, FREM, 236 237 // FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This 238 // DAG node does not require that X and Y have the same type, just that they 239 // are both floating point. X and the result must have the same type. 240 // FCOPYSIGN(f32, f64) is allowed. 241 FCOPYSIGN, 242 243 // INT = FGETSIGN(FP) - Return the sign bit of the specified floating point 244 // value as an integer 0/1 value. 245 FGETSIGN, 246 247 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the 248 /// specified, possibly variable, elements. The number of elements is 249 /// required to be a power of two. The types of the operands must all be 250 /// the same and must match the vector element type, except that integer 251 /// types are allowed to be larger than the element type, in which case 252 /// the operands are implicitly truncated. 253 BUILD_VECTOR, 254 255 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 256 /// at IDX replaced with VAL. If the type of VAL is larger than the vector 257 /// element type then VAL is truncated before replacement. 258 INSERT_VECTOR_ELT, 259 260 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 261 /// identified by the (potentially variable) element number IDX. If the 262 /// return type is an integer type larger than the element type of the 263 /// vector, the result is extended to the width of the return type. 264 EXTRACT_VECTOR_ELT, 265 266 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 267 /// vector type with the same length and element type, this produces a 268 /// concatenated vector result value, with length equal to the sum of the 269 /// lengths of the input vectors. 270 CONCAT_VECTORS, 271 272 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector 273 /// with VECTOR2 inserted into VECTOR1 at the (potentially 274 /// variable) element number IDX, which must be a multiple of the 275 /// VECTOR2 vector length. The elements of VECTOR1 starting at 276 /// IDX are overwritten with VECTOR2. Elements IDX through 277 /// vector_length(VECTOR2) must be valid VECTOR1 indices. 278 INSERT_SUBVECTOR, 279 280 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an 281 /// vector value) starting with the element number IDX, which must be a 282 /// constant multiple of the result vector length. 283 EXTRACT_SUBVECTOR, 284 285 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 286 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 287 /// values that indicate which value (or undef) each result element will 288 /// get. These constant ints are accessible through the 289 /// ShuffleVectorSDNode class. This is quite similar to the Altivec 290 /// 'vperm' instruction, except that the indices must be constants and are 291 /// in terms of the element size of VEC1/VEC2, not in terms of bytes. 292 VECTOR_SHUFFLE, 293 294 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a 295 /// scalar value into element 0 of the resultant vector type. The top 296 /// elements 1 to N-1 of the N-element vector are undefined. The type 297 /// of the operand must match the vector element type, except when they 298 /// are integer types. In this case the operand is allowed to be wider 299 /// than the vector element type, and is implicitly truncated to it. 300 SCALAR_TO_VECTOR, 301 302 // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing 303 // an unsigned/signed value of type i[2*N], then return the top part. 304 MULHU, MULHS, 305 306 /// Bitwise operators - logical and, logical or, logical xor. 307 AND, OR, XOR, 308 309 /// Shift and rotation operations. After legalization, the type of the 310 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization 311 /// the shift amount can be any type, but care must be taken to ensure it is 312 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before 313 /// legalization, types like i1024 can occur and i8 doesn't have enough bits 314 /// to represent the shift amount. By convention, DAGCombine and 315 /// SelectionDAGBuilder forces these shift amounts to i32 for simplicity. 316 /// 317 SHL, SRA, SRL, ROTL, ROTR, 318 319 /// Byte Swap and Counting operators. 320 BSWAP, CTTZ, CTLZ, CTPOP, 321 322 // Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not 323 // i1 then the high bits must conform to getBooleanContents. 324 SELECT, 325 326 // Select with a vector condition (op #0) and two vector operands (ops #1 327 // and #2), returning a vector result. All vectors have the same length. 328 // Much like the scalar select and setcc, each bit in the condition selects 329 // whether the corresponding result element is taken from op #1 or op #2. 330 VSELECT, 331 332 // Select with condition operator - This selects between a true value and 333 // a false value (ops #2 and #3) based on the boolean result of comparing 334 // the lhs and rhs (ops #0 and #1) of a conditional expression with the 335 // condition code in op #4, a CondCodeSDNode. 336 SELECT_CC, 337 338 // SetCC operator - This evaluates to a true value iff the condition is 339 // true. If the result value type is not i1 then the high bits conform 340 // to getBooleanContents. The operands to this are the left and right 341 // operands to compare (ops #0, and #1) and the condition code to compare 342 // them with (op #2) as a CondCodeSDNode. If the operands are vector types 343 // then the result type must also be a vector type. 344 SETCC, 345 346 // SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded 347 // integer shift operations, just like ADD/SUB_PARTS. The operation 348 // ordering is: 349 // [Lo,Hi] = op [LoLHS,HiLHS], Amt 350 SHL_PARTS, SRA_PARTS, SRL_PARTS, 351 352 // Conversion operators. These are all single input single output 353 // operations. For all of these, the result type must be strictly 354 // wider or narrower (depending on the operation) than the source 355 // type. 356 357 // SIGN_EXTEND - Used for integer types, replicating the sign bit 358 // into new bits. 359 SIGN_EXTEND, 360 361 // ZERO_EXTEND - Used for integer types, zeroing the new bits. 362 ZERO_EXTEND, 363 364 // ANY_EXTEND - Used for integer types. The high bits are undefined. 365 ANY_EXTEND, 366 367 // TRUNCATE - Completely drop the high bits. 368 TRUNCATE, 369 370 // [SU]INT_TO_FP - These operators convert integers (whose interpreted sign 371 // depends on the first letter) to floating point. 372 SINT_TO_FP, 373 UINT_TO_FP, 374 375 // SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 376 // sign extend a small value in a large integer register (e.g. sign 377 // extending the low 8 bits of a 32-bit register to fill the top 24 bits 378 // with the 7th bit). The size of the smaller type is indicated by the 1th 379 // operand, a ValueType node. 380 SIGN_EXTEND_INREG, 381 382 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned 383 /// integer. 384 FP_TO_SINT, 385 FP_TO_UINT, 386 387 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 388 /// down to the precision of the destination VT. TRUNC is a flag, which is 389 /// always an integer that is zero or one. If TRUNC is 0, this is a 390 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 391 /// value of Y. 392 /// 393 /// The TRUNC = 1 case is used in cases where we know that the value will 394 /// not be modified by the node, because Y is not using any of the extra 395 /// precision of source type. This allows certain transformations like 396 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 397 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 398 FP_ROUND, 399 400 // FLT_ROUNDS_ - Returns current rounding mode: 401 // -1 Undefined 402 // 0 Round to 0 403 // 1 Round to nearest 404 // 2 Round to +inf 405 // 3 Round to -inf 406 FLT_ROUNDS_, 407 408 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and 409 /// rounds it to a floating point value. It then promotes it and returns it 410 /// in a register of the same size. This operation effectively just 411 /// discards excess precision. The type to round down to is specified by 412 /// the VT operand, a VTSDNode. 413 FP_ROUND_INREG, 414 415 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. 416 FP_EXTEND, 417 418 // BITCAST - This operator converts between integer, vector and FP 419 // values, as if the value was stored to memory with one type and loaded 420 // from the same address with the other type (or equivalently for vector 421 // format conversions, etc). The source and result are required to have 422 // the same bit size (e.g. f32 <-> i32). This can also be used for 423 // int-to-int or fp-to-fp conversions, but that is a noop, deleted by 424 // getNode(). 425 BITCAST, 426 427 // CONVERT_RNDSAT - This operator is used to support various conversions 428 // between various types (float, signed, unsigned and vectors of those 429 // types) with rounding and saturation. NOTE: Avoid using this operator as 430 // most target don't support it and the operator might be removed in the 431 // future. It takes the following arguments: 432 // 0) value 433 // 1) dest type (type to convert to) 434 // 2) src type (type to convert from) 435 // 3) rounding imm 436 // 4) saturation imm 437 // 5) ISD::CvtCode indicating the type of conversion to do 438 CONVERT_RNDSAT, 439 440 // FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform 441 // promotions and truncation for half-precision (16 bit) floating 442 // numbers. We need special nodes since FP16 is a storage-only type with 443 // special semantics of operations. 444 FP16_TO_FP32, FP32_TO_FP16, 445 446 // FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 447 // FLOG, FLOG2, FLOG10, FEXP, FEXP2, 448 // FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary floating 449 // point operations. These are inspired by libm. 450 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 451 FLOG, FLOG2, FLOG10, FEXP, FEXP2, 452 FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR, 453 454 // LOAD and STORE have token chains as their first operand, then the same 455 // operands as an LLVM load/store instruction, then an offset node that 456 // is added / subtracted from the base pointer to form the address (for 457 // indexed memory ops). 458 LOAD, STORE, 459 460 // DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned 461 // to a specified boundary. This node always has two return values: a new 462 // stack pointer value and a chain. The first operand is the token chain, 463 // the second is the number of bytes to allocate, and the third is the 464 // alignment boundary. The size is guaranteed to be a multiple of the stack 465 // alignment, and the alignment is guaranteed to be bigger than the stack 466 // alignment (if required) or 0 to get standard stack alignment. 467 DYNAMIC_STACKALLOC, 468 469 // Control flow instructions. These all have token chains. 470 471 // BR - Unconditional branch. The first operand is the chain 472 // operand, the second is the MBB to branch to. 473 BR, 474 475 // BRIND - Indirect branch. The first operand is the chain, the second 476 // is the value to branch to, which must be of the same type as the target's 477 // pointer type. 478 BRIND, 479 480 // BR_JT - Jumptable branch. The first operand is the chain, the second 481 // is the jumptable index, the last one is the jumptable entry index. 482 BR_JT, 483 484 // BRCOND - Conditional branch. The first operand is the chain, the 485 // second is the condition, the third is the block to branch to if the 486 // condition is true. If the type of the condition is not i1, then the 487 // high bits must conform to getBooleanContents. 488 BRCOND, 489 490 // BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 491 // that the condition is represented as condition code, and two nodes to 492 // compare, rather than as a combined SetCC node. The operands in order are 493 // chain, cc, lhs, rhs, block to branch to if condition is true. 494 BR_CC, 495 496 // INLINEASM - Represents an inline asm block. This node always has two 497 // return values: a chain and a flag result. The inputs are as follows: 498 // Operand #0 : Input chain. 499 // Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. 500 // Operand #2 : a MDNodeSDNode with the !srcloc metadata. 501 // Operand #3 : HasSideEffect, IsAlignStack bits. 502 // After this, it is followed by a list of operands with this format: 503 // ConstantSDNode: Flags that encode whether it is a mem or not, the 504 // of operands that follow, etc. See InlineAsm.h. 505 // ... however many operands ... 506 // Operand #last: Optional, an incoming flag. 507 // 508 // The variable width operands are required to represent target addressing 509 // modes as a single "operand", even though they may have multiple 510 // SDOperands. 511 INLINEASM, 512 513 // EH_LABEL - Represents a label in mid basic block used to track 514 // locations needed for debug and exception handling tables. These nodes 515 // take a chain as input and return a chain. 516 EH_LABEL, 517 518 // STACKSAVE - STACKSAVE has one operand, an input chain. It produces a 519 // value, the same type as the pointer type for the system, and an output 520 // chain. 521 STACKSAVE, 522 523 // STACKRESTORE has two operands, an input chain and a pointer to restore to 524 // it returns an output chain. 525 STACKRESTORE, 526 527 // CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of 528 // a call sequence, and carry arbitrary information that target might want 529 // to know. The first operand is a chain, the rest are specified by the 530 // target and not touched by the DAG optimizers. 531 // CALLSEQ_START..CALLSEQ_END pairs may not be nested. 532 CALLSEQ_START, // Beginning of a call sequence 533 CALLSEQ_END, // End of a call sequence 534 535 // VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, 536 // and the alignment. It returns a pair of values: the vaarg value and a 537 // new chain. 538 VAARG, 539 540 // VACOPY - VACOPY has five operands: an input chain, a destination pointer, 541 // a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the 542 // source. 543 VACOPY, 544 545 // VAEND, VASTART - VAEND and VASTART have three operands: an input chain, a 546 // pointer, and a SRCVALUE. 547 VAEND, VASTART, 548 549 // SRCVALUE - This is a node type that holds a Value* that is used to 550 // make reference to a value in the LLVM IR. 551 SRCVALUE, 552 553 // MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to 554 // reference metadata in the IR. 555 MDNODE_SDNODE, 556 557 // PCMARKER - This corresponds to the pcmarker intrinsic. 558 PCMARKER, 559 560 // READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. 561 // The only operand is a chain and a value and a chain are produced. The 562 // value is the contents of the architecture specific cycle counter like 563 // register (or other high accuracy low latency clock source) 564 READCYCLECOUNTER, 565 566 // HANDLENODE node - Used as a handle for various purposes. 567 HANDLENODE, 568 569 // INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It 570 // takes as input a token chain, the pointer to the trampoline, the pointer 571 // to the nested function, the pointer to pass for the 'nest' parameter, a 572 // SRCVALUE for the trampoline and another for the nested function (allowing 573 // targets to access the original Function*). It produces a token chain as 574 // output. 575 INIT_TRAMPOLINE, 576 577 // ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. 578 // It takes a pointer to the trampoline and produces a (possibly) new 579 // pointer to the same trampoline with platform-specific adjustments 580 // applied. The pointer it returns points to an executable block of code. 581 ADJUST_TRAMPOLINE, 582 583 // TRAP - Trapping instruction 584 TRAP, 585 586 // PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are 587 // their first operand. The other operands are the address to prefetch, 588 // read / write specifier, locality specifier and instruction / data cache 589 // specifier. 590 PREFETCH, 591 592 // OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load, 593 // store-store, device) 594 // This corresponds to the memory.barrier intrinsic. 595 // it takes an input chain, 4 operands to specify the type of barrier, an 596 // operand specifying if the barrier applies to device and uncached memory 597 // and produces an output chain. 598 MEMBARRIER, 599 600 // OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) 601 // This corresponds to the fence instruction. It takes an input chain, and 602 // two integer constants: an AtomicOrdering and a SynchronizationScope. 603 ATOMIC_FENCE, 604 605 // Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) 606 // This corresponds to "load atomic" instruction. 607 ATOMIC_LOAD, 608 609 // OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr, val) 610 // This corresponds to "store atomic" instruction. 611 ATOMIC_STORE, 612 613 // Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 614 // This corresponds to the cmpxchg instruction. 615 ATOMIC_CMP_SWAP, 616 617 // Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) 618 // Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) 619 // These correspond to the atomicrmw instruction. 620 ATOMIC_SWAP, 621 ATOMIC_LOAD_ADD, 622 ATOMIC_LOAD_SUB, 623 ATOMIC_LOAD_AND, 624 ATOMIC_LOAD_OR, 625 ATOMIC_LOAD_XOR, 626 ATOMIC_LOAD_NAND, 627 ATOMIC_LOAD_MIN, 628 ATOMIC_LOAD_MAX, 629 ATOMIC_LOAD_UMIN, 630 ATOMIC_LOAD_UMAX, 631 632 /// BUILTIN_OP_END - This must be the last enum value in this list. 633 /// The target-specific pre-isel opcode values start here. 634 BUILTIN_OP_END 635 }; 636 637 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations 638 /// which do not reference a specific memory location should be less than 639 /// this value. Those that do must not be less than this value, and can 640 /// be used with SelectionDAG::getMemIntrinsicNode. 641 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+150; 642 643 //===--------------------------------------------------------------------===// 644 /// MemIndexedMode enum - This enum defines the load / store indexed 645 /// addressing modes. 646 /// 647 /// UNINDEXED "Normal" load / store. The effective address is already 648 /// computed and is available in the base pointer. The offset 649 /// operand is always undefined. In addition to producing a 650 /// chain, an unindexed load produces one value (result of the 651 /// load); an unindexed store does not produce a value. 652 /// 653 /// PRE_INC Similar to the unindexed mode where the effective address is 654 /// PRE_DEC the value of the base pointer add / subtract the offset. 655 /// It considers the computation as being folded into the load / 656 /// store operation (i.e. the load / store does the address 657 /// computation as well as performing the memory transaction). 658 /// The base operand is always undefined. In addition to 659 /// producing a chain, pre-indexed load produces two values 660 /// (result of the load and the result of the address 661 /// computation); a pre-indexed store produces one value (result 662 /// of the address computation). 663 /// 664 /// POST_INC The effective address is the value of the base pointer. The 665 /// POST_DEC value of the offset operand is then added to / subtracted 666 /// from the base after memory transaction. In addition to 667 /// producing a chain, post-indexed load produces two values 668 /// (the result of the load and the result of the base +/- offset 669 /// computation); a post-indexed store produces one value (the 670 /// the result of the base +/- offset computation). 671 enum MemIndexedMode { 672 UNINDEXED = 0, 673 PRE_INC, 674 PRE_DEC, 675 POST_INC, 676 POST_DEC, 677 LAST_INDEXED_MODE 678 }; 679 680 //===--------------------------------------------------------------------===// 681 /// LoadExtType enum - This enum defines the three variants of LOADEXT 682 /// (load with extension). 683 /// 684 /// SEXTLOAD loads the integer operand and sign extends it to a larger 685 /// integer result type. 686 /// ZEXTLOAD loads the integer operand and zero extends it to a larger 687 /// integer result type. 688 /// EXTLOAD is used for two things: floating point extending loads and 689 /// integer extending loads [the top bits are undefined]. 690 enum LoadExtType { 691 NON_EXTLOAD = 0, 692 EXTLOAD, 693 SEXTLOAD, 694 ZEXTLOAD, 695 LAST_LOADEXT_TYPE 696 }; 697 698 //===--------------------------------------------------------------------===// 699 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 700 /// below work out, when considering SETFALSE (something that never exists 701 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered 702 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal 703 /// to. If the "N" column is 1, the result of the comparison is undefined if 704 /// the input is a NAN. 705 /// 706 /// All of these (except for the 'always folded ops') should be handled for 707 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 708 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 709 /// 710 /// Note that these are laid out in a specific order to allow bit-twiddling 711 /// to transform conditions. 712 enum CondCode { 713 // Opcode N U L G E Intuitive operation 714 SETFALSE, // 0 0 0 0 Always false (always folded) 715 SETOEQ, // 0 0 0 1 True if ordered and equal 716 SETOGT, // 0 0 1 0 True if ordered and greater than 717 SETOGE, // 0 0 1 1 True if ordered and greater than or equal 718 SETOLT, // 0 1 0 0 True if ordered and less than 719 SETOLE, // 0 1 0 1 True if ordered and less than or equal 720 SETONE, // 0 1 1 0 True if ordered and operands are unequal 721 SETO, // 0 1 1 1 True if ordered (no nans) 722 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) 723 SETUEQ, // 1 0 0 1 True if unordered or equal 724 SETUGT, // 1 0 1 0 True if unordered or greater than 725 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal 726 SETULT, // 1 1 0 0 True if unordered or less than 727 SETULE, // 1 1 0 1 True if unordered, less than, or equal 728 SETUNE, // 1 1 1 0 True if unordered or not equal 729 SETTRUE, // 1 1 1 1 Always true (always folded) 730 // Don't care operations: undefined if the input is a nan. 731 SETFALSE2, // 1 X 0 0 0 Always false (always folded) 732 SETEQ, // 1 X 0 0 1 True if equal 733 SETGT, // 1 X 0 1 0 True if greater than 734 SETGE, // 1 X 0 1 1 True if greater than or equal 735 SETLT, // 1 X 1 0 0 True if less than 736 SETLE, // 1 X 1 0 1 True if less than or equal 737 SETNE, // 1 X 1 1 0 True if not equal 738 SETTRUE2, // 1 X 1 1 1 Always true (always folded) 739 740 SETCC_INVALID // Marker value. 741 }; 742 743 /// isSignedIntSetCC - Return true if this is a setcc instruction that 744 /// performs a signed comparison when used with integer operands. 745 inline bool isSignedIntSetCC(CondCode Code) { 746 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; 747 } 748 749 /// isUnsignedIntSetCC - Return true if this is a setcc instruction that 750 /// performs an unsigned comparison when used with integer operands. 751 inline bool isUnsignedIntSetCC(CondCode Code) { 752 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; 753 } 754 755 /// isTrueWhenEqual - Return true if the specified condition returns true if 756 /// the two operands to the condition are equal. Note that if one of the two 757 /// operands is a NaN, this value is meaningless. 758 inline bool isTrueWhenEqual(CondCode Cond) { 759 return ((int)Cond & 1) != 0; 760 } 761 762 /// getUnorderedFlavor - This function returns 0 if the condition is always 763 /// false if an operand is a NaN, 1 if the condition is always true if the 764 /// operand is a NaN, and 2 if the condition is undefined if the operand is a 765 /// NaN. 766 inline unsigned getUnorderedFlavor(CondCode Cond) { 767 return ((int)Cond >> 3) & 3; 768 } 769 770 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where 771 /// 'op' is a valid SetCC operation. 772 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 773 774 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 775 /// when given the operation for (X op Y). 776 CondCode getSetCCSwappedOperands(CondCode Operation); 777 778 /// getSetCCOrOperation - Return the result of a logical OR between different 779 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This 780 /// function returns SETCC_INVALID if it is not possible to represent the 781 /// resultant comparison. 782 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 783 784 /// getSetCCAndOperation - Return the result of a logical AND between 785 /// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 786 /// function returns SETCC_INVALID if it is not possible to represent the 787 /// resultant comparison. 788 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger); 789 790 //===--------------------------------------------------------------------===// 791 /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT 792 /// supports. 793 enum CvtCode { 794 CVT_FF, // Float from Float 795 CVT_FS, // Float from Signed 796 CVT_FU, // Float from Unsigned 797 CVT_SF, // Signed from Float 798 CVT_UF, // Unsigned from Float 799 CVT_SS, // Signed from Signed 800 CVT_SU, // Signed from Unsigned 801 CVT_US, // Unsigned from Signed 802 CVT_UU, // Unsigned from Unsigned 803 CVT_INVALID // Marker - Invalid opcode 804 }; 805 806 } // end llvm::ISD namespace 807 808 } // end llvm namespace 809 810 #endif 811
