| /external/vogar/src/vogar/commands/ |
| Rm.java | 23 * A rm command.
25 public final class Rm {
28 public Rm(Log log) {
33 new Command(log, "rm", "-rf", file.getPath()).execute();
|
| /cts/libs/vogar-expect/src/vogar/commands/ |
| Rm.java | 22 * A rm command.
24 public final class Rm {
27 new Command("rm", "-f", file.getPath()).execute();
31 new Command("rm", "-rf", directory.getPath()).execute();
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
| ArmDisassembler.c | 169 UINT32 Rn, Rd, Rm;
184 Rm = (OpCode & 0xf);
199 // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
234 // A5.2.3 [<Rn>, +/-<Rm>]
235 // A5.2.6 [<Rn>, +/-<Rm>]!
238 // A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
239 // A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
252 AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
258 AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W));
265 // A5.2.9 [<Rn>], +/-<Rm>
[all...] |
| ThumbDisassembler.c | 114 { "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 }, // ADC <Rndn>, <Rm>
150 { "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
154 { "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
157 { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
165 { "LSRS", 0x0800, 0xf800, DATA_FORMAT4 }, // LSRS <Rd>, <Rm>, #<imm5>
188 { "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
191 { "STRB" , 0x5400, 0xfe00, LOAD_STORE_FORMAT2 }, // STRB <Rt>, [<Rn>, <Rm>]
193 { "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 }, // STRH <Rt>, [<Rn>, <Rm>]
218 { "CMN", 0xeb100f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
221 { "TEQ", 0xea900f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | [all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | [all...] |
| /external/capstone/arch/AArch64/ |
| AArch64Disassembler.c | 845 unsigned Rm = fieldFromInstruction(insn, 16, 5);
874 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
895 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 687 // [Rn, Rm]
688 // {5-3} = Rm
693 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
694 return (Rm << 3) | Rn;
[all...] |
| /external/v8/src/arm/ |
| disasm-arm.cc | 91 void FormatNeonMemory(int Rn, int align, int Rm);
196 int rm = instr->RmValue(); local
198 PrintRegister(rm);
201 // Special case for using rm only.
317 } else if (format[1] == 'm') { // 'rm: Rm register
418 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) {
425 if (Rm == 15) {
427 } else if (Rm == 13) {
431 "], r%d", Rm);
[all...] |
| simulator-arm.cc | 2101 int rm = instr->RmValue(); local
2246 int rm = instr->RmValue(); local
2376 int rm = instr->RmValue(); local
2389 int rm = instr->RmValue(); local
2410 int rm = instr->RmValue(); local
3023 int rm = instr->RmValue(); local
3046 int rm = instr->RmValue(); local
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Assembler.cpp | 375 uint32_t Rm;
381 Rm = mAddrMode.reg_imm_Rm;
387 Rm = Op2;
397 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break;
398 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break;
399 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break;
400 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break;
401 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break;
471 int Rm = mAddrMode.reg_imm_Rm;
473 *mPC++ = A64_ADD_X_Wm_SXTW(Rd, Rn, Rm, amount)
[all...] |
| /system/core/libpixelflinger/tests/arch-arm64/assembler/ |
| arm64_assembler_test.cpp | 414 uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3)
439 op2 = Rm;
440 regs[Rm] = test.RmValue;
444 op2 = a64asm->reg_imm(Rm, test.shiftMode, test.shiftAmount);
445 regs[Rm] = test.RmValue;
455 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break;
456 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
460 case INSTR_SMULBB:a64asm->SMULBB(test.cond, Rd,Rm,Rs); break;
461 case INSTR_SMULBT:a64asm->SMULBT(test.cond, Rd,Rm,Rs); break;
462 case INSTR_SMULTB:a64asm->SMULTB(test.cond, Rd,Rm,Rs); break
[all...] |
| /external/capstone/arch/ARM/ |
| ARMDisassembler.c | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | 672 void lslv(const Register& rd, const Register& rn, const Register& rm);
675 void lsrv(const Register& rd, const Register& rn, const Register& rm);
678 void asrv(const Register& rd, const Register& rn, const Register& rm);
681 void rorv(const Register& rd, const Register& rn, const Register& rm);
814 const Register& rm,
817 // Conditional select: rd = cond ? rn : rm.
820 const Register& rm,
823 // Conditional select increment: rd = cond ? rn : rm + 1.
826 const Register& rm,
829 // Conditional select inversion: rd = cond ? rn : ~rm
[all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| arm-dis.c | 3932 const char *rm = arm_regnames [given & 0xf]; local
4161 int rm = ((given >> 0) & 0xf); local
4191 int rm = ((given >> 0) & 0xf); local
4266 int rm = ((given >> 0) & 0xf); local
[all...] |
| i386-dis.c | 284 #define Rm { OP_R, m_mode }
3169 int rm; member in struct:__anon5076
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /toolchain/binutils/binutils-2.27/gas/config/ |
| tc-arm.c | 15534 int rm; local
[all...] |
| /external/conscrypt/benchmark-android/ |
| vogar.jar | |
