1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Christian Knig <christian.koenig (at) amd.com> 25 */ 26 27 #ifndef SI_STATE_H 28 #define SI_STATE_H 29 30 #include "si_pm4.h" 31 #include "radeon/r600_pipe_common.h" 32 33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1) 34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1) 35 36 #define SI_MAX_ATTRIBS 16 37 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS 38 #define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */ 39 #define SI_NUM_CONST_BUFFERS 16 40 #define SI_NUM_IMAGES 16 41 #define SI_NUM_SHADER_BUFFERS 16 42 43 struct si_screen; 44 struct si_shader; 45 46 struct si_state_blend { 47 struct si_pm4_state pm4; 48 uint32_t cb_target_mask; 49 bool alpha_to_coverage; 50 bool alpha_to_one; 51 bool dual_src_blend; 52 /* Set 0xf or 0x0 (4 bits) per render target if the following is 53 * true. ANDed with spi_shader_col_format. 54 */ 55 unsigned blend_enable_4bit; 56 unsigned need_src_alpha_4bit; 57 }; 58 59 struct si_state_rasterizer { 60 struct si_pm4_state pm4; 61 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */ 62 struct si_pm4_state pm4_poly_offset[3]; 63 bool flatshade; 64 bool two_side; 65 bool multisample_enable; 66 bool force_persample_interp; 67 bool line_stipple_enable; 68 unsigned sprite_coord_enable; 69 unsigned pa_sc_line_stipple; 70 unsigned pa_cl_clip_cntl; 71 unsigned clip_plane_enable; 72 bool poly_stipple_enable; 73 bool line_smooth; 74 bool poly_smooth; 75 bool uses_poly_offset; 76 bool clamp_fragment_color; 77 bool rasterizer_discard; 78 bool scissor_enable; 79 bool clip_halfz; 80 }; 81 82 struct si_dsa_stencil_ref_part { 83 uint8_t valuemask[2]; 84 uint8_t writemask[2]; 85 }; 86 87 struct si_state_dsa { 88 struct si_pm4_state pm4; 89 unsigned alpha_func; 90 struct si_dsa_stencil_ref_part stencil_ref; 91 }; 92 93 struct si_stencil_ref { 94 struct r600_atom atom; 95 struct pipe_stencil_ref state; 96 struct si_dsa_stencil_ref_part dsa_part; 97 }; 98 99 struct si_vertex_element 100 { 101 unsigned count; 102 unsigned first_vb_use_mask; 103 104 /* Two bits per attribute indicating the size of each vector component 105 * in bytes if the size 3-workaround must be applied. 106 */ 107 uint32_t fix_size3; 108 uint64_t fix_fetch; 109 110 uint32_t rsrc_word3[SI_MAX_ATTRIBS]; 111 uint32_t format_size[SI_MAX_ATTRIBS]; 112 struct pipe_vertex_element elements[SI_MAX_ATTRIBS]; 113 }; 114 115 union si_state { 116 struct { 117 struct si_state_blend *blend; 118 struct si_state_rasterizer *rasterizer; 119 struct si_state_dsa *dsa; 120 struct si_pm4_state *poly_offset; 121 struct si_pm4_state *ls; 122 struct si_pm4_state *hs; 123 struct si_pm4_state *es; 124 struct si_pm4_state *gs; 125 struct si_pm4_state *vgt_shader_config; 126 struct si_pm4_state *vs; 127 struct si_pm4_state *ps; 128 } named; 129 struct si_pm4_state *array[0]; 130 }; 131 132 union si_state_atoms { 133 struct { 134 /* The order matters. */ 135 struct r600_atom *render_cond; 136 struct r600_atom *streamout_begin; 137 struct r600_atom *streamout_enable; /* must be after streamout_begin */ 138 struct r600_atom *framebuffer; 139 struct r600_atom *msaa_sample_locs; 140 struct r600_atom *db_render_state; 141 struct r600_atom *msaa_config; 142 struct r600_atom *sample_mask; 143 struct r600_atom *cb_render_state; 144 struct r600_atom *blend_color; 145 struct r600_atom *clip_regs; 146 struct r600_atom *clip_state; 147 struct r600_atom *shader_userdata; 148 struct r600_atom *scissors; 149 struct r600_atom *viewports; 150 struct r600_atom *stencil_ref; 151 struct r600_atom *spi_map; 152 } s; 153 struct r600_atom *array[0]; 154 }; 155 156 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*)) 157 158 struct si_shader_data { 159 struct r600_atom atom; 160 uint32_t sh_base[SI_NUM_SHADERS]; 161 }; 162 163 /* Private read-write buffer slots. */ 164 enum { 165 SI_HS_RING_TESS_FACTOR, 166 SI_HS_RING_TESS_OFFCHIP, 167 168 SI_ES_RING_ESGS, 169 SI_GS_RING_ESGS, 170 171 SI_RING_GSVS, 172 173 SI_VS_STREAMOUT_BUF0, 174 SI_VS_STREAMOUT_BUF1, 175 SI_VS_STREAMOUT_BUF2, 176 SI_VS_STREAMOUT_BUF3, 177 178 SI_HS_CONST_DEFAULT_TESS_LEVELS, 179 SI_VS_CONST_CLIP_PLANES, 180 SI_PS_CONST_POLY_STIPPLE, 181 SI_PS_CONST_SAMPLE_POSITIONS, 182 183 SI_NUM_RW_BUFFERS, 184 }; 185 186 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines 187 * are contiguous: 188 * 189 * 0 - rw buffers 190 * 1 - vertex const buffers 191 * 2 - vertex shader buffers 192 * ... 193 * 5 - fragment const buffers 194 * ... 195 * 21 - compute const buffers 196 * ... 197 */ 198 #define SI_SHADER_DESCS_CONST_BUFFERS 0 199 #define SI_SHADER_DESCS_SHADER_BUFFERS 1 200 #define SI_SHADER_DESCS_SAMPLERS 2 201 #define SI_SHADER_DESCS_IMAGES 3 202 #define SI_NUM_SHADER_DESCS 4 203 204 #define SI_DESCS_RW_BUFFERS 0 205 #define SI_DESCS_FIRST_SHADER 1 206 #define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + \ 207 PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS) 208 #define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + \ 209 SI_NUM_SHADERS * SI_NUM_SHADER_DESCS) 210 211 /* This represents descriptors in memory, such as buffer resources, 212 * image resources, and sampler states. 213 */ 214 struct si_descriptors { 215 /* The list of descriptors in malloc'd memory. */ 216 uint32_t *list; 217 /* The list in mapped GPU memory. */ 218 uint32_t *gpu_list; 219 /* The size of one descriptor. */ 220 unsigned element_dw_size; 221 /* The maximum number of descriptors. */ 222 unsigned num_elements; 223 224 /* The buffer where the descriptors have been uploaded. */ 225 struct r600_resource *buffer; 226 unsigned buffer_offset; 227 228 /* Offset in CE RAM */ 229 unsigned ce_offset; 230 231 /* elements of the list that are changed and need to be uploaded */ 232 unsigned dirty_mask; 233 234 /* Whether the CE ram is dirty and needs to be reinitialized entirely 235 * before we can do partial updates. */ 236 bool ce_ram_dirty; 237 238 /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor 239 * array will be stored. */ 240 unsigned shader_userdata_offset; 241 }; 242 243 struct si_sampler_views { 244 struct pipe_sampler_view *views[SI_NUM_SAMPLERS]; 245 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS]; 246 247 /* The i-th bit is set if that element is enabled (non-NULL resource). */ 248 unsigned enabled_mask; 249 }; 250 251 struct si_buffer_resources { 252 enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */ 253 enum radeon_bo_priority priority; 254 struct pipe_resource **buffers; /* this has num_buffers elements */ 255 256 /* The i-th bit is set if that element is enabled (non-NULL resource). */ 257 unsigned enabled_mask; 258 }; 259 260 #define si_pm4_block_idx(member) \ 261 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *)) 262 263 #define si_pm4_state_changed(sctx, member) \ 264 ((sctx)->queued.named.member != (sctx)->emitted.named.member) 265 266 #define si_pm4_bind_state(sctx, member, value) \ 267 do { \ 268 (sctx)->queued.named.member = (value); \ 269 } while(0) 270 271 #define si_pm4_delete_state(sctx, member, value) \ 272 do { \ 273 if ((sctx)->queued.named.member == (value)) { \ 274 (sctx)->queued.named.member = NULL; \ 275 } \ 276 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \ 277 si_pm4_block_idx(member)); \ 278 } while(0) 279 280 /* si_descriptors.c */ 281 void si_ce_reinitialize_all_descriptors(struct si_context *sctx); 282 void si_ce_enable_loads(struct radeon_winsys_cs *ib); 283 void si_set_mutable_tex_desc_fields(struct r600_texture *tex, 284 const struct radeon_surf_level *base_level_info, 285 unsigned base_level, unsigned first_level, 286 unsigned block_width, bool is_stencil, 287 uint32_t *state); 288 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader, 289 uint slot, struct pipe_constant_buffer *cbuf); 290 void si_get_shader_buffers(struct si_context *sctx, uint shader, 291 uint start_slot, uint count, 292 struct pipe_shader_buffer *sbuf); 293 void si_set_ring_buffer(struct pipe_context *ctx, uint slot, 294 struct pipe_resource *buffer, 295 unsigned stride, unsigned num_records, 296 bool add_tid, bool swizzle, 297 unsigned element_size, unsigned index_stride, uint64_t offset); 298 void si_init_all_descriptors(struct si_context *sctx); 299 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx); 300 bool si_upload_graphics_shader_descriptors(struct si_context *sctx); 301 bool si_upload_compute_shader_descriptors(struct si_context *sctx); 302 void si_release_all_descriptors(struct si_context *sctx); 303 void si_all_descriptors_begin_new_cs(struct si_context *sctx); 304 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer, 305 const uint8_t *ptr, unsigned size, uint32_t *const_offset); 306 void si_update_all_texture_descriptors(struct si_context *sctx); 307 void si_shader_change_notify(struct si_context *sctx); 308 void si_update_compressed_colortex_masks(struct si_context *sctx); 309 void si_emit_graphics_shader_userdata(struct si_context *sctx, 310 struct r600_atom *atom); 311 void si_emit_compute_shader_userdata(struct si_context *sctx); 312 void si_set_rw_buffer(struct si_context *sctx, 313 uint slot, const struct pipe_constant_buffer *input); 314 /* si_state.c */ 315 struct si_shader_selector; 316 317 void si_init_atom(struct si_context *sctx, struct r600_atom *atom, 318 struct r600_atom **list_elem, 319 void (*emit_func)(struct si_context *ctx, struct r600_atom *state)); 320 void si_init_state_functions(struct si_context *sctx); 321 void si_init_screen_state_functions(struct si_screen *sscreen); 322 void 323 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf, 324 enum pipe_format format, 325 unsigned offset, unsigned size, 326 uint32_t *state); 327 void 328 si_make_texture_descriptor(struct si_screen *screen, 329 struct r600_texture *tex, 330 bool sampler, 331 enum pipe_texture_target target, 332 enum pipe_format pipe_format, 333 const unsigned char state_swizzle[4], 334 unsigned first_level, unsigned last_level, 335 unsigned first_layer, unsigned last_layer, 336 unsigned width, unsigned height, unsigned depth, 337 uint32_t *state, 338 uint32_t *fmask_state); 339 struct pipe_sampler_view * 340 si_create_sampler_view_custom(struct pipe_context *ctx, 341 struct pipe_resource *texture, 342 const struct pipe_sampler_view *state, 343 unsigned width0, unsigned height0, 344 unsigned force_level); 345 346 /* si_state_shader.c */ 347 bool si_update_shaders(struct si_context *sctx); 348 void si_init_shader_functions(struct si_context *sctx); 349 bool si_init_shader_cache(struct si_screen *sscreen); 350 void si_destroy_shader_cache(struct si_screen *sscreen); 351 void si_init_shader_selector_async(void *job, int thread_index); 352 353 /* si_state_draw.c */ 354 void si_emit_cache_flush(struct si_context *sctx); 355 void si_ce_pre_draw_synchronization(struct si_context *sctx); 356 void si_ce_post_draw_synchronization(struct si_context *sctx); 357 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo); 358 void si_trace_emit(struct si_context *sctx); 359 360 361 static inline unsigned 362 si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil) 363 { 364 if (stencil) 365 return rtex->surface.stencil_tiling_index[level]; 366 else 367 return rtex->surface.tiling_index[level]; 368 } 369 370 #endif 371
