| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| DeadMachineInstructionElim.cpp | 146 MachineInstr *UseMI = Use.getParent();
147 if (UseMI==MI)
150 UseMI->getOperand(0).setReg(0U);
|
| LiveRangeEdit.cpp | 167 MachineInstr *DefMI = 0, *UseMI = 0;
181 if (UseMI && UseMI != MI)
186 UseMI = MI;
189 if (!DefMI || !UseMI)
193 << " into single use: " << *UseMI);
196 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
199 MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI);
203 LIS.ReplaceMachineInstrInMaps(UseMI, FoldMI);
204 UseMI->eraseFromParent()
[all...] |
| OptimizePHIs.cpp | 145 MachineInstr *UseMI = &*I;
146 if (!UseMI->isPHI() || !IsDeadPHICycle(UseMI, PHIsInCycle))
|
| RegisterScavenging.cpp | 261 /// longest after StargMII. UseMI is set to the instruction where the search
269 MachineBasicBlock::iterator &UseMI) {
326 UseMI = RestorePointMI;
355 MachineBasicBlock::iterator UseMI;
356 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
372 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
381 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
382 II = prior(UseMI);
386 ScavengeRestore = prior(UseMI);
|
| MachineSSAUpdater.cpp | 223 MachineInstr *UseMI = U.getParent();
225 if (UseMI->isPHI()) {
226 MachineBasicBlock *SourceBB = findCorrespondingPred(UseMI, &U);
229 NewVR = GetValueInMiddleOfBlock(UseMI->getParent());
|
| PeepholeOptimizer.cpp | 166 MachineInstr *UseMI = &*UI;
167 if (UseMI == MI)
170 if (UseMI->isPHI()) {
192 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
195 MachineBasicBlock *UseMBB = UseMI->getParent();
198 if (!LocalMIs.count(UseMI))
238 MachineInstr *UseMI = UseMO->getParent();
239 MachineBasicBlock *UseMBB = UseMI->getParent();
244 BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc()
[all...] |
| ScheduleDAGInstrs.cpp | 313 MachineInstr *UseMI = UseSU->getInstr();
314 const MCInstrDesc &UseMCID = UseMI->getDesc();
315 int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg);
316 assert(RegUseIndex >= 0 && "UseMI doesn's use register!");
355 const MachineInstr *UseMI = UseMO->getParent();
356 unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
357 const MCInstrDesc &UseMCID = UseMI->getDesc();
365 if (UseMI->getParent() != MI->getParent()) {
613 MachineInstr *UseMI = Use->getInstr();
616 if (UseMI) {
[all...] |
| MachineLICM.cpp | 855 MachineInstr *UseMI = &*UI;
856 if (UseMI->isPHI())
859 if (UseMI->isCopy()) {
860 unsigned Def = UseMI->getOperand(0).getReg();
[all...] |
| RegAllocFast.cpp | 553 const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
555 if (UseMI.isCopyLike())
556 Hint = UseMI.getOperand(0).getReg();
[all...] |
| TailDuplication.cpp | 246 MachineInstr *UseMI = &*UI;
248 if (UseMI->isDebugValue()) {
253 UseMI->eraseFromParent();
256 if (UseMI->getParent() == DefBB && !UseMI->isPHI())
323 MachineInstr *UseMI = &*UI;
324 if (UseMI->isDebugValue())
326 if (UseMI->getParent() != BB)
[all...] |
| TwoAddressInstructionPass.cpp | 290 static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
291 const MCInstrDesc &MCID = UseMI->getDesc();
293 MachineOperand &MO = UseMI->getOperand(i);
295 (MO.isDef() || UseMI->isRegTiedToDefOperand(i)))
314 MachineInstr *UseMI = UseMO.getParent();
315 MachineBasicBlock *UseMBB = UseMI->getParent();
317 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
323 if (isTwoAddrUse(UseMI, Reg))
481 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg);
482 if (UseMI.getParent() != MBB
[all...] |
| /external/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 166 MachineInstr *DefMI = nullptr, *UseMI = nullptr;
178 if (UseMI && UseMI != MI)
183 UseMI = MI;
186 if (!DefMI || !UseMI)
192 LIS.getInstructionIndex(*UseMI)))
196 // Assume there are stores between DefMI and UseMI.
202 << " into single use: " << *UseMI);
205 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
208 MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS)
[all...] |
| MachineRegisterInfo.cpp | 469 MachineInstr *UseMI = &*I;
470 if (UseMI->isDebugValue())
471 UseMI->getOperand(0).setReg(0U);
|
| MachineSSAUpdater.cpp | 222 MachineInstr *UseMI = U.getParent();
224 if (UseMI->isPHI()) {
225 MachineBasicBlock *SourceBB = findCorrespondingPred(UseMI, &U);
228 NewVR = GetValueInMiddleOfBlock(UseMI->getParent());
|
| RegisterScavenging.cpp | 279 MachineBasicBlock::iterator &UseMI) {
336 UseMI = RestorePointMI;
372 MachineBasicBlock::iterator UseMI;
373 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
424 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
441 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,
443 II = std::prev(UseMI);
449 Scavenged[SI].Restore = &*std::prev(UseMI);
|
| DetectDeadLanes.cpp | 426 const MachineInstr &UseMI = *MO.getParent();
427 if (UseMI.isKill())
431 if (lowersToCopies(UseMI)) {
432 assert(UseMI.getDesc().getNumDefs() == 1);
433 const MachineOperand &Def = *UseMI.defs().begin();
440 if (lowersToCopies(UseMI)) {
442 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
444 DEBUG(dbgs() << "Copy accross incompatible classes: " << UseMI);
|
| RegAllocFast.cpp | 611 const MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(VirtReg);
613 if (UseMI.isCopyLike())
614 Hint = UseMI.getOperand(0).getReg();
[all...] |
| TailDuplicator.cpp | 180 MachineInstr *UseMI = UseMO.getParent();
182 if (UseMI->isDebugValue()) {
187 UseMI->eraseFromParent();
190 if (UseMI->getParent() == DefBB && !UseMI->isPHI())
255 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
256 if (UseMI.isDebugValue())
258 if (UseMI.getParent() != BB)
[all...] |
| LiveIntervalAnalysis.cpp | 428 MachineInstr *UseMI = &*(I++);
429 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
431 SlotIndex Idx = getInstructionIndex(*UseMI).getRegSlot();
438 DEBUG(dbgs() << Idx << '\t' << *UseMI
518 MachineInstr *UseMI = MO.getParent();
519 if (UseMI->isDebugValue())
529 SlotIndex Idx = getInstructionIndex(*UseMI).getRegSlot();
[all...] |
| PeepholeOptimizer.cpp | 455 MachineInstr *UseMI = UseMO.getParent();
456 if (UseMI == MI)
459 if (UseMI->isPHI()) {
485 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
488 MachineBasicBlock *UseMBB = UseMI->getParent();
491 if (!LocalMIs.count(UseMI))
528 MachineInstr *UseMI = UseMO->getParent();
529 MachineBasicBlock *UseMBB = UseMI->getParent();
540 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc()
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIFoldOperands.cpp | 50 MachineInstr *UseMI;
56 UseMI(MI), UseOpNo(OpNo) {
101 MachineInstr *MI = Fold.UseMI;
125 if (Candidate.UseMI == MI)
191 static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI,
197 const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx);
236 if (UseMI->getOpcode() == AMDGPU::COPY) {
237 unsigned DestReg = UseMI->getOperand(0).getReg();
247 UseMI->setDesc(TII->get(MovOp));
248 CopiesToReplace.push_back(UseMI);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 124 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg);
125 if (UseMI->getParent() != MBB)
128 while (UseMI->isCopy() || UseMI->isInsertSubreg()) {
129 Reg = UseMI->getOperand(0).getReg();
133 UseMI = &*MRI->use_instr_nodbg_begin(Reg);
134 if (UseMI->getParent() != MBB)
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXFMAMutate.cpp | 285 MachineInstr *UseMI = UseMO.getParent();
289 if (UseMI == AddendMI)
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 121 MachineInstr *UseMI = &*MRI->use_nodbg_begin(Reg);
122 if (UseMI->getParent() != MBB)
125 while (UseMI->isCopy() || UseMI->isInsertSubreg()) {
126 Reg = UseMI->getOperand(0).getReg();
130 UseMI = &*MRI->use_nodbg_begin(Reg);
131 if (UseMI->getParent() != MBB)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonOptAddrMode.cpp | 78 bool xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
165 MachineInstr *UseMI = NodeAddr<StmtNode *>(IA).Addr->getCode();
169 MI->getParent() != UseMI->getParent())
172 const MCInstrDesc &UseMID = UseMI->getDesc();
174 HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset ||
175 getBaseWithLongOffset(UseMI) < 0)
179 if (UseMID.mayStore() && UseMI->getOperand(2).isReg() &&
180 UseMI->getOperand(2).getReg() == MI->getOperand(0).getReg())
183 for (auto &Mo : UseMI->operands())
441 MachineInstr *UseMI = UseIA.Addr->getCode()
[all...] |
