1 /* 2 * Advanced Micro Devices Inc. AMD8111E Linux Network Driver 3 * Copyright (C) 2003 Advanced Micro Devices 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 18 * USA 19 20 Module Name: 21 22 amd8111e.h 23 24 Abstract: 25 26 AMD8111 based 10/100 Ethernet Controller driver definitions. 27 28 Environment: 29 30 Kernel Mode 31 32 Revision History: 33 3.0.0 34 Initial Revision. 35 3.0.1 36 */ 37 38 FILE_LICENCE ( GPL2_OR_LATER ); 39 40 #ifndef _AMD811E_H 41 #define _AMD811E_H 42 43 /* Command style register access 44 45 Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register. 46 47 eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered. 48 49 */ 50 51 /* Offset for Memory Mapped Registers. */ 52 /* 32 bit registers */ 53 54 #define ASF_STAT 0x00 /* ASF status register */ 55 #define CHIPID 0x04 /* Chip ID regsiter */ 56 #define MIB_DATA 0x10 /* MIB data register */ 57 #define MIB_ADDR 0x14 /* MIB address register */ 58 #define STAT0 0x30 /* Status0 register */ 59 #define INT0 0x38 /* Interrupt0 register */ 60 #define INTEN0 0x40 /* Interrupt0 enable register*/ 61 #define CMD0 0x48 /* Command0 register */ 62 #define CMD2 0x50 /* Command2 register */ 63 #define CMD3 0x54 /* Command3 resiter */ 64 #define CMD7 0x64 /* Command7 register */ 65 66 #define CTRL1 0x6C /* Control1 register */ 67 #define CTRL2 0x70 /* Control2 register */ 68 69 #define XMT_RING_LIMIT 0x7C /* Transmit ring limit register */ 70 71 #define AUTOPOLL0 0x88 /* Auto-poll0 register */ 72 #define AUTOPOLL1 0x8A /* Auto-poll1 register */ 73 #define AUTOPOLL2 0x8C /* Auto-poll2 register */ 74 #define AUTOPOLL3 0x8E /* Auto-poll3 register */ 75 #define AUTOPOLL4 0x90 /* Auto-poll4 register */ 76 #define AUTOPOLL5 0x92 /* Auto-poll5 register */ 77 78 #define AP_VALUE 0x98 /* Auto-poll value register */ 79 #define DLY_INT_A 0xA8 /* Group A delayed interrupt register */ 80 #define DLY_INT_B 0xAC /* Group B delayed interrupt register */ 81 82 #define FLOW_CONTROL 0xC8 /* Flow control register */ 83 #define PHY_ACCESS 0xD0 /* PHY access register */ 84 85 #define STVAL 0xD8 /* Software timer value register */ 86 87 #define XMT_RING_BASE_ADDR0 0x100 /* Transmit ring0 base addr register */ 88 #define XMT_RING_BASE_ADDR1 0x108 /* Transmit ring1 base addr register */ 89 #define XMT_RING_BASE_ADDR2 0x110 /* Transmit ring2 base addr register */ 90 #define XMT_RING_BASE_ADDR3 0x118 /* Transmit ring2 base addr register */ 91 92 #define RCV_RING_BASE_ADDR0 0x120 /* Transmit ring0 base addr register */ 93 94 #define PMAT0 0x190 /* OnNow pattern register0 */ 95 #define PMAT1 0x194 /* OnNow pattern register1 */ 96 97 /* 16bit registers */ 98 99 #define XMT_RING_LEN0 0x140 /* Transmit Ring0 length register */ 100 #define XMT_RING_LEN1 0x144 /* Transmit Ring1 length register */ 101 #define XMT_RING_LEN2 0x148 /* Transmit Ring2 length register */ 102 #define XMT_RING_LEN3 0x14C /* Transmit Ring3 length register */ 103 104 #define RCV_RING_LEN0 0x150 /* Receive Ring0 length register */ 105 106 #define SRAM_SIZE 0x178 /* SRAM size register */ 107 #define SRAM_BOUNDARY 0x17A /* SRAM boundary register */ 108 109 /* 48bit register */ 110 111 #define PADR 0x160 /* Physical address register */ 112 113 #define IFS1 0x18C /* Inter-frame spacing Part1 register */ 114 #define IFS 0x18D /* Inter-frame spacing register */ 115 #define IPG 0x18E /* Inter-frame gap register */ 116 /* 64bit register */ 117 118 #define LADRF 0x168 /* Logical address filter register */ 119 120 121 /* Register Bit Definitions */ 122 typedef enum { 123 124 ASF_INIT_DONE = (1 << 1), 125 ASF_INIT_PRESENT = (1 << 0), 126 127 }STAT_ASF_BITS; 128 129 typedef enum { 130 131 MIB_CMD_ACTIVE = (1 << 15 ), 132 MIB_RD_CMD = (1 << 13 ), 133 MIB_CLEAR = (1 << 12 ), 134 MIB_ADDRESS = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)| 135 (1 << 4) | (1 << 5), 136 }MIB_ADDR_BITS; 137 138 139 typedef enum { 140 141 PMAT_DET = (1 << 12), 142 MP_DET = (1 << 11), 143 LC_DET = (1 << 10), 144 SPEED_MASK = (1 << 9)|(1 << 8)|(1 << 7), 145 FULL_DPLX = (1 << 6), 146 LINK_STATS = (1 << 5), 147 AUTONEG_COMPLETE = (1 << 4), 148 MIIPD = (1 << 3), 149 RX_SUSPENDED = (1 << 2), 150 TX_SUSPENDED = (1 << 1), 151 RUNNING = (1 << 0), 152 153 }STAT0_BITS; 154 155 #define PHY_SPEED_10 0x2 156 #define PHY_SPEED_100 0x3 157 158 /* INT0 0x38, 32bit register */ 159 typedef enum { 160 161 INTR = (1 << 31), 162 PCSINT = (1 << 28), 163 LCINT = (1 << 27), 164 APINT5 = (1 << 26), 165 APINT4 = (1 << 25), 166 APINT3 = (1 << 24), 167 TINT_SUM = (1 << 23), 168 APINT2 = (1 << 22), 169 APINT1 = (1 << 21), 170 APINT0 = (1 << 20), 171 MIIPDTINT = (1 << 19), 172 MCCINT = (1 << 17), 173 MREINT = (1 << 16), 174 RINT_SUM = (1 << 15), 175 SPNDINT = (1 << 14), 176 MPINT = (1 << 13), 177 SINT = (1 << 12), 178 TINT3 = (1 << 11), 179 TINT2 = (1 << 10), 180 TINT1 = (1 << 9), 181 TINT0 = (1 << 8), 182 UINT = (1 << 7), 183 STINT = (1 << 4), 184 RINT0 = (1 << 0), 185 186 }INT0_BITS; 187 188 typedef enum { 189 190 VAL3 = (1 << 31), /* VAL bit for byte 3 */ 191 VAL2 = (1 << 23), /* VAL bit for byte 2 */ 192 VAL1 = (1 << 15), /* VAL bit for byte 1 */ 193 VAL0 = (1 << 7), /* VAL bit for byte 0 */ 194 195 }VAL_BITS; 196 197 typedef enum { 198 199 /* VAL3 */ 200 LCINTEN = (1 << 27), 201 APINT5EN = (1 << 26), 202 APINT4EN = (1 << 25), 203 APINT3EN = (1 << 24), 204 /* VAL2 */ 205 APINT2EN = (1 << 22), 206 APINT1EN = (1 << 21), 207 APINT0EN = (1 << 20), 208 MIIPDTINTEN = (1 << 19), 209 MCCIINTEN = (1 << 18), 210 MCCINTEN = (1 << 17), 211 MREINTEN = (1 << 16), 212 /* VAL1 */ 213 SPNDINTEN = (1 << 14), 214 MPINTEN = (1 << 13), 215 TINTEN3 = (1 << 11), 216 SINTEN = (1 << 12), 217 TINTEN2 = (1 << 10), 218 TINTEN1 = (1 << 9), 219 TINTEN0 = (1 << 8), 220 /* VAL0 */ 221 STINTEN = (1 << 4), 222 RINTEN0 = (1 << 0), 223 224 INTEN0_CLEAR = 0x1F7F7F1F, /* Command style register */ 225 226 }INTEN0_BITS; 227 228 typedef enum { 229 /* VAL2 */ 230 RDMD0 = (1 << 16), 231 /* VAL1 */ 232 TDMD3 = (1 << 11), 233 TDMD2 = (1 << 10), 234 TDMD1 = (1 << 9), 235 TDMD0 = (1 << 8), 236 /* VAL0 */ 237 UINTCMD = (1 << 6), 238 RX_FAST_SPND = (1 << 5), 239 TX_FAST_SPND = (1 << 4), 240 RX_SPND = (1 << 3), 241 TX_SPND = (1 << 2), 242 INTREN = (1 << 1), 243 RUN = (1 << 0), 244 245 CMD0_CLEAR = 0x000F0F7F, /* Command style register */ 246 247 }CMD0_BITS; 248 249 typedef enum { 250 251 /* VAL3 */ 252 CONDUIT_MODE = (1 << 29), 253 /* VAL2 */ 254 RPA = (1 << 19), 255 DRCVPA = (1 << 18), 256 DRCVBC = (1 << 17), 257 PROM = (1 << 16), 258 /* VAL1 */ 259 ASTRP_RCV = (1 << 13), 260 RCV_DROP0 = (1 << 12), 261 EMBA = (1 << 11), 262 DXMT2PD = (1 << 10), 263 LTINTEN = (1 << 9), 264 DXMTFCS = (1 << 8), 265 /* VAL0 */ 266 APAD_XMT = (1 << 6), 267 DRTY = (1 << 5), 268 INLOOP = (1 << 4), 269 EXLOOP = (1 << 3), 270 REX_RTRY = (1 << 2), 271 REX_UFLO = (1 << 1), 272 REX_LCOL = (1 << 0), 273 274 CMD2_CLEAR = 0x3F7F3F7F, /* Command style register */ 275 276 }CMD2_BITS; 277 278 typedef enum { 279 280 /* VAL3 */ 281 ASF_INIT_DONE_ALIAS = (1 << 29), 282 /* VAL2 */ 283 JUMBO = (1 << 21), 284 VSIZE = (1 << 20), 285 VLONLY = (1 << 19), 286 VL_TAG_DEL = (1 << 18), 287 /* VAL1 */ 288 EN_PMGR = (1 << 14), 289 INTLEVEL = (1 << 13), 290 FORCE_FULL_DUPLEX = (1 << 12), 291 FORCE_LINK_STATUS = (1 << 11), 292 APEP = (1 << 10), 293 MPPLBA = (1 << 9), 294 /* VAL0 */ 295 RESET_PHY_PULSE = (1 << 2), 296 RESET_PHY = (1 << 1), 297 PHY_RST_POL = (1 << 0), 298 299 }CMD3_BITS; 300 301 302 typedef enum { 303 304 /* VAL0 */ 305 PMAT_SAVE_MATCH = (1 << 4), 306 PMAT_MODE = (1 << 3), 307 MPEN_SW = (1 << 1), 308 LCMODE_SW = (1 << 0), 309 310 CMD7_CLEAR = 0x0000001B /* Command style register */ 311 312 }CMD7_BITS; 313 314 315 typedef enum { 316 317 RESET_PHY_WIDTH = (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */ 318 XMTSP_MASK = (1 << 9) | (1 << 8), /* 9:8 */ 319 XMTSP_128 = (1 << 9), /* 9 */ 320 XMTSP_64 = (1 << 8), 321 CACHE_ALIGN = (1 << 4), 322 BURST_LIMIT_MASK = (0xF << 0 ), 323 CTRL1_DEFAULT = 0x00010111, 324 325 }CTRL1_BITS; 326 327 typedef enum { 328 329 FMDC_MASK = (1 << 9)|(1 << 8), /* 9:8 */ 330 XPHYRST = (1 << 7), 331 XPHYANE = (1 << 6), 332 XPHYFD = (1 << 5), 333 XPHYSP = (1 << 4) | (1 << 3), /* 4:3 */ 334 APDW_MASK = (1 << 2) | (1 << 1) | (1 << 0), /* 2:0 */ 335 336 }CTRL2_BITS; 337 338 /* XMT_RING_LIMIT 0x7C, 32bit register */ 339 typedef enum { 340 341 XMT_RING2_LIMIT = (0xFF << 16), /* 23:16 */ 342 XMT_RING1_LIMIT = (0xFF << 8), /* 15:8 */ 343 XMT_RING0_LIMIT = (0xFF << 0), /* 7:0 */ 344 345 }XMT_RING_LIMIT_BITS; 346 347 typedef enum { 348 349 AP_REG0_EN = (1 << 15), 350 AP_REG0_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */ 351 AP_PHY0_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */ 352 353 }AUTOPOLL0_BITS; 354 355 /* AUTOPOLL1 0x8A, 16bit register */ 356 typedef enum { 357 358 AP_REG1_EN = (1 << 15), 359 AP_REG1_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */ 360 AP_PRE_SUP1 = (1 << 6), 361 AP_PHY1_DFLT = (1 << 5), 362 AP_PHY1_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */ 363 364 }AUTOPOLL1_BITS; 365 366 367 typedef enum { 368 369 AP_REG2_EN = (1 << 15), 370 AP_REG2_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */ 371 AP_PRE_SUP2 = (1 << 6), 372 AP_PHY2_DFLT = (1 << 5), 373 AP_PHY2_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */ 374 375 }AUTOPOLL2_BITS; 376 377 typedef enum { 378 379 AP_REG3_EN = (1 << 15), 380 AP_REG3_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */ 381 AP_PRE_SUP3 = (1 << 6), 382 AP_PHY3_DFLT = (1 << 5), 383 AP_PHY3_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */ 384 385 }AUTOPOLL3_BITS; 386 387 388 typedef enum { 389 390 AP_REG4_EN = (1 << 15), 391 AP_REG4_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */ 392 AP_PRE_SUP4 = (1 << 6), 393 AP_PHY4_DFLT = (1 << 5), 394 AP_PHY4_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */ 395 396 }AUTOPOLL4_BITS; 397 398 399 typedef enum { 400 401 AP_REG5_EN = (1 << 15), 402 AP_REG5_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */ 403 AP_PRE_SUP5 = (1 << 6), 404 AP_PHY5_DFLT = (1 << 5), 405 AP_PHY5_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */ 406 407 }AUTOPOLL5_BITS; 408 409 410 411 412 /* AP_VALUE 0x98, 32bit ragister */ 413 typedef enum { 414 415 AP_VAL_ACTIVE = (1 << 31), 416 AP_VAL_RD_CMD = ( 1 << 29), 417 AP_ADDR = (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */ 418 AP_VAL = (0xF << 0) | (0xF << 4) |( 0xF << 8) | 419 (0xF << 12), /* 15:0 */ 420 421 }AP_VALUE_BITS; 422 423 typedef enum { 424 425 DLY_INT_A_R3 = (1 << 31), 426 DLY_INT_A_R2 = (1 << 30), 427 DLY_INT_A_R1 = (1 << 29), 428 DLY_INT_A_R0 = (1 << 28), 429 DLY_INT_A_T3 = (1 << 27), 430 DLY_INT_A_T2 = (1 << 26), 431 DLY_INT_A_T1 = (1 << 25), 432 DLY_INT_A_T0 = ( 1 << 24), 433 EVENT_COUNT_A = (0xF << 16) | (0x1 << 20),/* 20:16 */ 434 MAX_DELAY_TIME_A = (0xF << 0) | (0xF << 4) | (1 << 8)| 435 (1 << 9) | (1 << 10), /* 10:0 */ 436 437 }DLY_INT_A_BITS; 438 439 typedef enum { 440 441 DLY_INT_B_R3 = (1 << 31), 442 DLY_INT_B_R2 = (1 << 30), 443 DLY_INT_B_R1 = (1 << 29), 444 DLY_INT_B_R0 = (1 << 28), 445 DLY_INT_B_T3 = (1 << 27), 446 DLY_INT_B_T2 = (1 << 26), 447 DLY_INT_B_T1 = (1 << 25), 448 DLY_INT_B_T0 = ( 1 << 24), 449 EVENT_COUNT_B = (0xF << 16) | (0x1 << 20),/* 20:16 */ 450 MAX_DELAY_TIME_B = (0xF << 0) | (0xF << 4) | (1 << 8)| 451 (1 << 9) | (1 << 10), /* 10:0 */ 452 }DLY_INT_B_BITS; 453 454 455 /* FLOW_CONTROL 0xC8, 32bit register */ 456 typedef enum { 457 458 PAUSE_LEN_CHG = (1 << 30), 459 FTPE = (1 << 22), 460 FRPE = (1 << 21), 461 NAPA = (1 << 20), 462 NPA = (1 << 19), 463 FIXP = ( 1 << 18), 464 FCCMD = ( 1 << 16), 465 PAUSE_LEN = (0xF << 0) | (0xF << 4) |( 0xF << 8) | (0xF << 12), /* 15:0 */ 466 467 }FLOW_CONTROL_BITS; 468 469 /* PHY_ ACCESS 0xD0, 32bit register */ 470 typedef enum { 471 472 PHY_CMD_ACTIVE = (1 << 31), 473 PHY_WR_CMD = (1 << 30), 474 PHY_RD_CMD = (1 << 29), 475 PHY_RD_ERR = (1 << 28), 476 PHY_PRE_SUP = (1 << 27), 477 PHY_ADDR = (1 << 21) | (1 << 22) | (1 << 23)| 478 (1 << 24) |(1 << 25),/* 25:21 */ 479 PHY_REG_ADDR = (1 << 16) | (1 << 17) | (1 << 18)| (1 << 19) | (1 << 20),/* 20:16 */ 480 PHY_DATA = (0xF << 0)|(0xF << 4) |(0xF << 8)| 481 (0xF << 12),/* 15:0 */ 482 483 }PHY_ACCESS_BITS; 484 485 486 /* PMAT0 0x190, 32bit register */ 487 typedef enum { 488 PMR_ACTIVE = (1 << 31), 489 PMR_WR_CMD = (1 << 30), 490 PMR_RD_CMD = (1 << 29), 491 PMR_BANK = (1 <<28), 492 PMR_ADDR = (0xF << 16)|(1 << 20)|(1 << 21)| 493 (1 << 22),/* 22:16 */ 494 PMR_B4 = (0xF << 0) | (0xF << 4),/* 15:0 */ 495 }PMAT0_BITS; 496 497 498 /* PMAT1 0x194, 32bit register */ 499 typedef enum { 500 PMR_B3 = (0xF << 24) | (0xF <<28),/* 31:24 */ 501 PMR_B2 = (0xF << 16) |(0xF << 20),/* 23:16 */ 502 PMR_B1 = (0xF << 8) | (0xF <<12), /* 15:8 */ 503 PMR_B0 = (0xF << 0)|(0xF << 4),/* 7:0 */ 504 }PMAT1_BITS; 505 506 /************************************************************************/ 507 /* */ 508 /* MIB counter definitions */ 509 /* */ 510 /************************************************************************/ 511 512 #define rcv_miss_pkts 0x00 513 #define rcv_octets 0x01 514 #define rcv_broadcast_pkts 0x02 515 #define rcv_multicast_pkts 0x03 516 #define rcv_undersize_pkts 0x04 517 #define rcv_oversize_pkts 0x05 518 #define rcv_fragments 0x06 519 #define rcv_jabbers 0x07 520 #define rcv_unicast_pkts 0x08 521 #define rcv_alignment_errors 0x09 522 #define rcv_fcs_errors 0x0A 523 #define rcv_good_octets 0x0B 524 #define rcv_mac_ctrl 0x0C 525 #define rcv_flow_ctrl 0x0D 526 #define rcv_pkts_64_octets 0x0E 527 #define rcv_pkts_65to127_octets 0x0F 528 #define rcv_pkts_128to255_octets 0x10 529 #define rcv_pkts_256to511_octets 0x11 530 #define rcv_pkts_512to1023_octets 0x12 531 #define rcv_pkts_1024to1518_octets 0x13 532 #define rcv_unsupported_opcode 0x14 533 #define rcv_symbol_errors 0x15 534 #define rcv_drop_pkts_ring1 0x16 535 #define rcv_drop_pkts_ring2 0x17 536 #define rcv_drop_pkts_ring3 0x18 537 #define rcv_drop_pkts_ring4 0x19 538 #define rcv_jumbo_pkts 0x1A 539 540 #define xmt_underrun_pkts 0x20 541 #define xmt_octets 0x21 542 #define xmt_packets 0x22 543 #define xmt_broadcast_pkts 0x23 544 #define xmt_multicast_pkts 0x24 545 #define xmt_collisions 0x25 546 #define xmt_unicast_pkts 0x26 547 #define xmt_one_collision 0x27 548 #define xmt_multiple_collision 0x28 549 #define xmt_deferred_transmit 0x29 550 #define xmt_late_collision 0x2A 551 #define xmt_excessive_defer 0x2B 552 #define xmt_loss_carrier 0x2C 553 #define xmt_excessive_collision 0x2D 554 #define xmt_back_pressure 0x2E 555 #define xmt_flow_ctrl 0x2F 556 #define xmt_pkts_64_octets 0x30 557 #define xmt_pkts_65to127_octets 0x31 558 #define xmt_pkts_128to255_octets 0x32 559 #define xmt_pkts_256to511_octets 0x33 560 #define xmt_pkts_512to1023_octets 0x34 561 #define xmt_pkts_1024to1518_octet 0x35 562 #define xmt_oversize_pkts 0x36 563 #define xmt_jumbo_pkts 0x37 564 565 /* ipg parameters */ 566 #define DEFAULT_IPG 0x60 567 #define IFS1_DELTA 36 568 #define IPG_CONVERGE_JIFFIES (HZ/2) 569 #define IPG_STABLE_TIME 5 570 #define MIN_IPG 96 571 #define MAX_IPG 255 572 #define IPG_STEP 16 573 #define CSTATE 1 574 #define SSTATE 2 575 576 /* amd8111e decriptor flag definitions */ 577 typedef enum { 578 579 OWN_BIT = (1 << 15), 580 ADD_FCS_BIT = (1 << 13), 581 LTINT_BIT = (1 << 12), 582 STP_BIT = (1 << 9), 583 ENP_BIT = (1 << 8), 584 KILL_BIT = (1 << 6), 585 TCC_VLAN_INSERT = (1 << 1), 586 TCC_VLAN_REPLACE = (1 << 1) |( 1<< 0), 587 588 }TX_FLAG_BITS; 589 590 typedef enum { 591 ERR_BIT = (1 << 14), 592 FRAM_BIT = (1 << 13), 593 OFLO_BIT = (1 << 12), 594 CRC_BIT = (1 << 11), 595 PAM_BIT = (1 << 6), 596 LAFM_BIT = (1 << 5), 597 BAM_BIT = (1 << 4), 598 TT_VLAN_TAGGED = (1 << 3) |(1 << 2),/* 0x000 */ 599 TT_PRTY_TAGGED = (1 << 3),/* 0x0008 */ 600 601 }RX_FLAG_BITS; 602 603 #define RESET_RX_FLAGS 0x0000 604 #define TT_MASK 0x000c 605 #define TCC_MASK 0x0003 606 607 /* driver ioctl parameters */ 608 #define AMD8111E_REG_DUMP_LEN 13*sizeof(u32) 609 610 /* crc generator constants */ 611 #define CRC32 0xedb88320 612 #define INITCRC 0xFFFFFFFF 613 614 /* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register. 615 BUG? */ 616 #define amd8111e_writeq(_UlData,_memMap) \ 617 writel(*(u32*)(&_UlData), _memMap); \ 618 writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4) 619 620 /* maps the external speed options to internal value */ 621 typedef enum { 622 SPEED_AUTONEG, 623 SPEED10_HALF, 624 SPEED10_FULL, 625 SPEED100_HALF, 626 SPEED100_FULL, 627 }EXT_PHY_OPTION; 628 629 630 #endif /* _AMD8111E_H */ 631 632
