1 /* 2 * Copyright 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "main/context.h" 25 #include "main/teximage.h" 26 #include "main/blend.h" 27 #include "main/fbobject.h" 28 #include "main/renderbuffer.h" 29 #include "main/glformats.h" 30 31 #include "brw_blorp.h" 32 #include "brw_context.h" 33 #include "brw_defines.h" 34 #include "brw_meta_util.h" 35 #include "brw_state.h" 36 #include "intel_fbo.h" 37 #include "intel_debug.h" 38 39 #define FILE_DEBUG_FLAG DEBUG_BLORP 40 41 static bool 42 brw_blorp_lookup_shader(struct blorp_context *blorp, 43 const void *key, uint32_t key_size, 44 uint32_t *kernel_out, void *prog_data_out) 45 { 46 struct brw_context *brw = blorp->driver_ctx; 47 return brw_search_cache(&brw->cache, BRW_CACHE_BLORP_PROG, 48 key, key_size, kernel_out, prog_data_out); 49 } 50 51 static void 52 brw_blorp_upload_shader(struct blorp_context *blorp, 53 const void *key, uint32_t key_size, 54 const void *kernel, uint32_t kernel_size, 55 const struct brw_stage_prog_data *prog_data, 56 uint32_t prog_data_size, 57 uint32_t *kernel_out, void *prog_data_out) 58 { 59 struct brw_context *brw = blorp->driver_ctx; 60 brw_upload_cache(&brw->cache, BRW_CACHE_BLORP_PROG, key, key_size, 61 kernel, kernel_size, prog_data, prog_data_size, 62 kernel_out, prog_data_out); 63 } 64 65 void 66 brw_blorp_init(struct brw_context *brw) 67 { 68 blorp_init(&brw->blorp, brw, &brw->isl_dev); 69 70 brw->blorp.compiler = brw->screen->compiler; 71 72 switch (brw->gen) { 73 case 6: 74 brw->blorp.mocs.tex = 0; 75 brw->blorp.mocs.rb = 0; 76 brw->blorp.mocs.vb = 0; 77 brw->blorp.exec = gen6_blorp_exec; 78 break; 79 case 7: 80 brw->blorp.mocs.tex = GEN7_MOCS_L3; 81 brw->blorp.mocs.rb = GEN7_MOCS_L3; 82 brw->blorp.mocs.vb = GEN7_MOCS_L3; 83 if (brw->is_haswell) { 84 brw->blorp.exec = gen75_blorp_exec; 85 } else { 86 brw->blorp.exec = gen7_blorp_exec; 87 } 88 break; 89 case 8: 90 brw->blorp.mocs.tex = BDW_MOCS_WB; 91 brw->blorp.mocs.rb = BDW_MOCS_PTE; 92 brw->blorp.mocs.vb = BDW_MOCS_WB; 93 brw->blorp.exec = gen8_blorp_exec; 94 break; 95 case 9: 96 brw->blorp.mocs.tex = SKL_MOCS_WB; 97 brw->blorp.mocs.rb = SKL_MOCS_PTE; 98 brw->blorp.mocs.vb = SKL_MOCS_WB; 99 brw->blorp.exec = gen9_blorp_exec; 100 break; 101 default: 102 unreachable("Invalid gen"); 103 } 104 105 brw->blorp.lookup_shader = brw_blorp_lookup_shader; 106 brw->blorp.upload_shader = brw_blorp_upload_shader; 107 } 108 109 static void 110 apply_gen6_stencil_hiz_offset(struct isl_surf *surf, 111 struct intel_mipmap_tree *mt, 112 uint32_t lod, 113 uint32_t *offset) 114 { 115 assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD); 116 117 if (mt->format == MESA_FORMAT_S_UINT8) { 118 /* Note: we can't compute the stencil offset using 119 * intel_miptree_get_aligned_offset(), because the miptree 120 * claims that the region is untiled even though it's W tiled. 121 */ 122 *offset = mt->level[lod].level_y * mt->pitch + 123 mt->level[lod].level_x * 64; 124 } else { 125 *offset = intel_miptree_get_aligned_offset(mt, 126 mt->level[lod].level_x, 127 mt->level[lod].level_y); 128 } 129 130 surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod); 131 surf->logical_level0_px.height = minify(surf->logical_level0_px.height, lod); 132 surf->phys_level0_sa.width = minify(surf->phys_level0_sa.width, lod); 133 surf->phys_level0_sa.height = minify(surf->phys_level0_sa.height, lod); 134 surf->levels = 1; 135 surf->array_pitch_el_rows = 136 ALIGN(surf->phys_level0_sa.height, surf->image_alignment_el.height); 137 } 138 139 static void 140 blorp_surf_for_miptree(struct brw_context *brw, 141 struct blorp_surf *surf, 142 struct intel_mipmap_tree *mt, 143 bool is_render_target, 144 uint32_t safe_aux_usage, 145 unsigned *level, 146 unsigned start_layer, unsigned num_layers, 147 struct isl_surf tmp_surfs[2]) 148 { 149 if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS || 150 mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) { 151 const unsigned num_samples = MAX2(1, mt->num_samples); 152 for (unsigned i = 0; i < num_layers; i++) { 153 for (unsigned s = 0; s < num_samples; s++) { 154 const unsigned phys_layer = (start_layer + i) * num_samples + s; 155 intel_miptree_check_level_layer(mt, *level, phys_layer); 156 } 157 } 158 } else { 159 for (unsigned i = 0; i < num_layers; i++) 160 intel_miptree_check_level_layer(mt, *level, start_layer + i); 161 } 162 163 intel_miptree_get_isl_surf(brw, mt, &tmp_surfs[0]); 164 surf->surf = &tmp_surfs[0]; 165 surf->addr = (struct blorp_address) { 166 .buffer = mt->bo, 167 .offset = mt->offset, 168 .read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER : 169 I915_GEM_DOMAIN_SAMPLER, 170 .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0, 171 }; 172 173 if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 && 174 mt->array_layout == ALL_SLICES_AT_EACH_LOD) { 175 /* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD hack in 176 * order to allow for layered rendering. The hack makes each LOD of the 177 * stencil or HiZ buffer a single tightly packed array surface at some 178 * offset into the surface. Since ISL doesn't know how to deal with the 179 * crazy ALL_SLICES_AT_EACH_LOD layout and since we have to do a manual 180 * offset of it anyway, we might as well do the offset here and keep the 181 * hacks inside the i965 driver. 182 * 183 * See also gen6_depth_stencil_state.c 184 */ 185 uint32_t offset; 186 apply_gen6_stencil_hiz_offset(&tmp_surfs[0], mt, *level, &offset); 187 surf->addr.offset += offset; 188 *level = 0; 189 } 190 191 struct isl_surf *aux_surf = &tmp_surfs[1]; 192 intel_miptree_get_aux_isl_surf(brw, mt, aux_surf, &surf->aux_usage); 193 194 if (surf->aux_usage != ISL_AUX_USAGE_NONE) { 195 if (surf->aux_usage == ISL_AUX_USAGE_HIZ) { 196 /* If we're not going to use it as a depth buffer, resolve HiZ */ 197 if (!(safe_aux_usage & (1 << ISL_AUX_USAGE_HIZ))) { 198 for (unsigned i = 0; i < num_layers; i++) { 199 intel_miptree_slice_resolve_depth(brw, mt, *level, 200 start_layer + i); 201 202 /* If we're rendering to it then we'll need a HiZ resolve once 203 * we're done before we can use it with HiZ again. 204 */ 205 if (is_render_target) 206 intel_miptree_slice_set_needs_hiz_resolve(mt, *level, 207 start_layer + i); 208 } 209 surf->aux_usage = ISL_AUX_USAGE_NONE; 210 } 211 } else if (!(safe_aux_usage & (1 << surf->aux_usage))) { 212 uint32_t flags = 0; 213 if (safe_aux_usage & (1 << ISL_AUX_USAGE_CCS_E)) 214 flags |= INTEL_MIPTREE_IGNORE_CCS_E; 215 216 intel_miptree_resolve_color(brw, mt, 217 *level, start_layer, num_layers, flags); 218 219 assert(!intel_miptree_has_color_unresolved(mt, *level, 1, 220 start_layer, num_layers)); 221 surf->aux_usage = ISL_AUX_USAGE_NONE; 222 } 223 } 224 225 if (is_render_target) 226 intel_miptree_used_for_rendering(brw, mt, *level, 227 start_layer, num_layers); 228 229 if (surf->aux_usage != ISL_AUX_USAGE_NONE) { 230 /* We only really need a clear color if we also have an auxiliary 231 * surface. Without one, it does nothing. 232 */ 233 surf->clear_color = intel_miptree_get_isl_clear_color(brw, mt); 234 235 surf->aux_surf = aux_surf; 236 surf->aux_addr = (struct blorp_address) { 237 .read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER : 238 I915_GEM_DOMAIN_SAMPLER, 239 .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0, 240 }; 241 242 if (mt->mcs_buf) { 243 surf->aux_addr.buffer = mt->mcs_buf->bo; 244 surf->aux_addr.offset = mt->mcs_buf->offset; 245 } else { 246 assert(surf->aux_usage == ISL_AUX_USAGE_HIZ); 247 struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt; 248 if (hiz_mt) { 249 surf->aux_addr.buffer = hiz_mt->bo; 250 if (brw->gen == 6 && 251 hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) { 252 /* gen6 requires the HiZ buffer to be manually offset to the 253 * right location. We could fixup the surf but it doesn't 254 * matter since most of those fields don't matter. 255 */ 256 apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level, 257 &surf->aux_addr.offset); 258 } else { 259 surf->aux_addr.offset = 0; 260 } 261 assert(hiz_mt->pitch == aux_surf->row_pitch); 262 } else { 263 surf->aux_addr.buffer = mt->hiz_buf->aux_base.bo; 264 surf->aux_addr.offset = mt->hiz_buf->aux_base.offset; 265 } 266 } 267 } else { 268 surf->aux_addr = (struct blorp_address) { 269 .buffer = NULL, 270 }; 271 memset(&surf->clear_color, 0, sizeof(surf->clear_color)); 272 } 273 assert((surf->aux_usage == ISL_AUX_USAGE_NONE) == 274 (surf->aux_addr.buffer == NULL)); 275 } 276 277 static enum isl_format 278 brw_blorp_to_isl_format(struct brw_context *brw, mesa_format format, 279 bool is_render_target) 280 { 281 switch (format) { 282 case MESA_FORMAT_NONE: 283 return ISL_FORMAT_UNSUPPORTED; 284 case MESA_FORMAT_S_UINT8: 285 return ISL_FORMAT_R8_UINT; 286 case MESA_FORMAT_Z24_UNORM_X8_UINT: 287 case MESA_FORMAT_Z24_UNORM_S8_UINT: 288 return ISL_FORMAT_R24_UNORM_X8_TYPELESS; 289 case MESA_FORMAT_Z_FLOAT32: 290 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: 291 return ISL_FORMAT_R32_FLOAT; 292 case MESA_FORMAT_Z_UNORM16: 293 return ISL_FORMAT_R16_UNORM; 294 default: { 295 if (is_render_target) { 296 assert(brw->format_supported_as_render_target[format]); 297 return brw->render_target_format[format]; 298 } else { 299 return brw_format_for_mesa_format(format); 300 } 301 break; 302 } 303 } 304 } 305 306 /** 307 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+ 308 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are 309 * 310 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE 311 * 0 1 2 3 4 5 312 * 4 5 6 7 0 1 313 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE 314 * 315 * which is simply adding 4 then modding by 8 (or anding with 7). 316 * 317 * We then may need to apply workarounds for textureGather hardware bugs. 318 */ 319 static enum isl_channel_select 320 swizzle_to_scs(GLenum swizzle) 321 { 322 return (enum isl_channel_select)((swizzle + 4) & 7); 323 } 324 325 static unsigned 326 physical_to_logical_layer(struct intel_mipmap_tree *mt, 327 unsigned physical_layer) 328 { 329 if (mt->num_samples > 1 && 330 (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS || 331 mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS)) { 332 assert(physical_layer % mt->num_samples == 0); 333 return physical_layer / mt->num_samples; 334 } else { 335 return physical_layer; 336 } 337 } 338 339 /** 340 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using 341 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is 342 * the physical layer holding sample 0. So, for example, if 343 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer == 344 * 4*n. 345 */ 346 void 347 brw_blorp_blit_miptrees(struct brw_context *brw, 348 struct intel_mipmap_tree *src_mt, 349 unsigned src_level, unsigned src_layer, 350 mesa_format src_format, int src_swizzle, 351 struct intel_mipmap_tree *dst_mt, 352 unsigned dst_level, unsigned dst_layer, 353 mesa_format dst_format, 354 float src_x0, float src_y0, 355 float src_x1, float src_y1, 356 float dst_x0, float dst_y0, 357 float dst_x1, float dst_y1, 358 GLenum filter, bool mirror_x, bool mirror_y, 359 bool decode_srgb, bool encode_srgb) 360 { 361 /* Blorp operates in logical layers */ 362 src_layer = physical_to_logical_layer(src_mt, src_layer); 363 dst_layer = physical_to_logical_layer(dst_mt, dst_layer); 364 365 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)" 366 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n", 367 __func__, 368 src_mt->num_samples, _mesa_get_format_name(src_mt->format), src_mt, 369 src_level, src_layer, src_x0, src_y0, src_x1, src_y1, 370 dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt, 371 dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1, 372 mirror_x, mirror_y); 373 374 if (!decode_srgb && _mesa_get_format_color_encoding(src_format) == GL_SRGB) 375 src_format = _mesa_get_srgb_format_linear(src_format); 376 377 if (!encode_srgb && _mesa_get_format_color_encoding(dst_format) == GL_SRGB) 378 dst_format = _mesa_get_srgb_format_linear(dst_format); 379 380 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F 381 * texture, the above code configures the source format for L32_FLOAT or 382 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge, 383 * the SAMPLE message appears to handle multisampled L32_FLOAT and 384 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work 385 * around the problem by using a source format of R32_FLOAT. This 386 * shouldn't affect rendering correctness, since the destination format is 387 * R32_FLOAT, so only the contents of the red channel matters. 388 */ 389 if (brw->gen == 6 && 390 src_mt->num_samples > 1 && dst_mt->num_samples <= 1 && 391 src_mt->format == dst_mt->format && 392 (dst_format == MESA_FORMAT_L_FLOAT32 || 393 dst_format == MESA_FORMAT_I_FLOAT32)) { 394 src_format = dst_format = MESA_FORMAT_R_FLOAT32; 395 } 396 397 uint32_t src_usage_flags = (1 << ISL_AUX_USAGE_MCS); 398 if (src_format == src_mt->format) 399 src_usage_flags |= (1 << ISL_AUX_USAGE_CCS_E); 400 401 uint32_t dst_usage_flags = (1 << ISL_AUX_USAGE_MCS); 402 if (dst_format == dst_mt->format) { 403 dst_usage_flags |= (1 << ISL_AUX_USAGE_CCS_E) | 404 (1 << ISL_AUX_USAGE_CCS_D); 405 } 406 407 struct isl_surf tmp_surfs[4]; 408 struct blorp_surf src_surf, dst_surf; 409 blorp_surf_for_miptree(brw, &src_surf, src_mt, false, src_usage_flags, 410 &src_level, src_layer, 1, &tmp_surfs[0]); 411 blorp_surf_for_miptree(brw, &dst_surf, dst_mt, true, dst_usage_flags, 412 &dst_level, dst_layer, 1, &tmp_surfs[2]); 413 414 struct isl_swizzle src_isl_swizzle = { 415 .r = swizzle_to_scs(GET_SWZ(src_swizzle, 0)), 416 .g = swizzle_to_scs(GET_SWZ(src_swizzle, 1)), 417 .b = swizzle_to_scs(GET_SWZ(src_swizzle, 2)), 418 .a = swizzle_to_scs(GET_SWZ(src_swizzle, 3)), 419 }; 420 421 struct blorp_batch batch; 422 blorp_batch_init(&brw->blorp, &batch, brw, 0); 423 blorp_blit(&batch, &src_surf, src_level, src_layer, 424 brw_blorp_to_isl_format(brw, src_format, false), src_isl_swizzle, 425 &dst_surf, dst_level, dst_layer, 426 brw_blorp_to_isl_format(brw, dst_format, true), 427 ISL_SWIZZLE_IDENTITY, 428 src_x0, src_y0, src_x1, src_y1, 429 dst_x0, dst_y0, dst_x1, dst_y1, 430 filter, mirror_x, mirror_y); 431 blorp_batch_finish(&batch); 432 } 433 434 void 435 brw_blorp_copy_miptrees(struct brw_context *brw, 436 struct intel_mipmap_tree *src_mt, 437 unsigned src_level, unsigned src_layer, 438 struct intel_mipmap_tree *dst_mt, 439 unsigned dst_level, unsigned dst_layer, 440 unsigned src_x, unsigned src_y, 441 unsigned dst_x, unsigned dst_y, 442 unsigned src_width, unsigned src_height) 443 { 444 DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d" 445 "to %dx %s mt %p %d %d (%d,%d)\n", 446 __func__, 447 src_mt->num_samples, _mesa_get_format_name(src_mt->format), src_mt, 448 src_level, src_layer, src_x, src_y, src_width, src_height, 449 dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt, 450 dst_level, dst_layer, dst_x, dst_y); 451 452 struct isl_surf tmp_surfs[4]; 453 struct blorp_surf src_surf, dst_surf; 454 blorp_surf_for_miptree(brw, &src_surf, src_mt, false, 455 (1 << ISL_AUX_USAGE_MCS) | 456 (1 << ISL_AUX_USAGE_CCS_E), 457 &src_level, src_layer, 1, &tmp_surfs[0]); 458 blorp_surf_for_miptree(brw, &dst_surf, dst_mt, true, 459 (1 << ISL_AUX_USAGE_MCS) | 460 (1 << ISL_AUX_USAGE_CCS_E), 461 &dst_level, dst_layer, 1, &tmp_surfs[2]); 462 463 struct blorp_batch batch; 464 blorp_batch_init(&brw->blorp, &batch, brw, 0); 465 blorp_copy(&batch, &src_surf, src_level, src_layer, 466 &dst_surf, dst_level, dst_layer, 467 src_x, src_y, dst_x, dst_y, src_width, src_height); 468 blorp_batch_finish(&batch); 469 } 470 471 static struct intel_mipmap_tree * 472 find_miptree(GLbitfield buffer_bit, struct intel_renderbuffer *irb) 473 { 474 struct intel_mipmap_tree *mt = irb->mt; 475 if (buffer_bit == GL_STENCIL_BUFFER_BIT && mt->stencil_mt) 476 mt = mt->stencil_mt; 477 return mt; 478 } 479 480 static int 481 blorp_get_texture_swizzle(const struct intel_renderbuffer *irb) 482 { 483 return irb->Base.Base._BaseFormat == GL_RGB ? 484 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE) : 485 SWIZZLE_XYZW; 486 } 487 488 static void 489 do_blorp_blit(struct brw_context *brw, GLbitfield buffer_bit, 490 struct intel_renderbuffer *src_irb, mesa_format src_format, 491 struct intel_renderbuffer *dst_irb, mesa_format dst_format, 492 GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1, 493 GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1, 494 GLenum filter, bool mirror_x, bool mirror_y) 495 { 496 const struct gl_context *ctx = &brw->ctx; 497 498 /* Find source/dst miptrees */ 499 struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb); 500 struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb); 501 502 const bool do_srgb = ctx->Color.sRGBEnabled; 503 504 /* Do the blit */ 505 brw_blorp_blit_miptrees(brw, 506 src_mt, src_irb->mt_level, src_irb->mt_layer, 507 src_format, blorp_get_texture_swizzle(src_irb), 508 dst_mt, dst_irb->mt_level, dst_irb->mt_layer, 509 dst_format, 510 srcX0, srcY0, srcX1, srcY1, 511 dstX0, dstY0, dstX1, dstY1, 512 filter, mirror_x, mirror_y, 513 do_srgb, do_srgb); 514 515 dst_irb->need_downsample = true; 516 } 517 518 static bool 519 try_blorp_blit(struct brw_context *brw, 520 const struct gl_framebuffer *read_fb, 521 const struct gl_framebuffer *draw_fb, 522 GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1, 523 GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1, 524 GLenum filter, GLbitfield buffer_bit) 525 { 526 struct gl_context *ctx = &brw->ctx; 527 528 /* Sync up the state of window system buffers. We need to do this before 529 * we go looking for the buffers. 530 */ 531 intel_prepare_render(brw); 532 533 bool mirror_x, mirror_y; 534 if (brw_meta_mirror_clip_and_scissor(ctx, read_fb, draw_fb, 535 &srcX0, &srcY0, &srcX1, &srcY1, 536 &dstX0, &dstY0, &dstX1, &dstY1, 537 &mirror_x, &mirror_y)) 538 return true; 539 540 /* Find buffers */ 541 struct intel_renderbuffer *src_irb; 542 struct intel_renderbuffer *dst_irb; 543 struct intel_mipmap_tree *src_mt; 544 struct intel_mipmap_tree *dst_mt; 545 switch (buffer_bit) { 546 case GL_COLOR_BUFFER_BIT: 547 src_irb = intel_renderbuffer(read_fb->_ColorReadBuffer); 548 for (unsigned i = 0; i < draw_fb->_NumColorDrawBuffers; ++i) { 549 dst_irb = intel_renderbuffer(draw_fb->_ColorDrawBuffers[i]); 550 if (dst_irb) 551 do_blorp_blit(brw, buffer_bit, 552 src_irb, src_irb->Base.Base.Format, 553 dst_irb, dst_irb->Base.Base.Format, 554 srcX0, srcY0, srcX1, srcY1, 555 dstX0, dstY0, dstX1, dstY1, 556 filter, mirror_x, mirror_y); 557 } 558 break; 559 case GL_DEPTH_BUFFER_BIT: 560 src_irb = 561 intel_renderbuffer(read_fb->Attachment[BUFFER_DEPTH].Renderbuffer); 562 dst_irb = 563 intel_renderbuffer(draw_fb->Attachment[BUFFER_DEPTH].Renderbuffer); 564 src_mt = find_miptree(buffer_bit, src_irb); 565 dst_mt = find_miptree(buffer_bit, dst_irb); 566 567 /* We can't handle format conversions between Z24 and other formats 568 * since we have to lie about the surface format. See the comments in 569 * brw_blorp_surface_info::set(). 570 */ 571 if ((src_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT) != 572 (dst_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT)) 573 return false; 574 575 do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE, 576 dst_irb, MESA_FORMAT_NONE, srcX0, srcY0, 577 srcX1, srcY1, dstX0, dstY0, dstX1, dstY1, 578 filter, mirror_x, mirror_y); 579 break; 580 case GL_STENCIL_BUFFER_BIT: 581 src_irb = 582 intel_renderbuffer(read_fb->Attachment[BUFFER_STENCIL].Renderbuffer); 583 dst_irb = 584 intel_renderbuffer(draw_fb->Attachment[BUFFER_STENCIL].Renderbuffer); 585 do_blorp_blit(brw, buffer_bit, src_irb, MESA_FORMAT_NONE, 586 dst_irb, MESA_FORMAT_NONE, srcX0, srcY0, 587 srcX1, srcY1, dstX0, dstY0, dstX1, dstY1, 588 filter, mirror_x, mirror_y); 589 break; 590 default: 591 unreachable("not reached"); 592 } 593 594 return true; 595 } 596 597 bool 598 brw_blorp_copytexsubimage(struct brw_context *brw, 599 struct gl_renderbuffer *src_rb, 600 struct gl_texture_image *dst_image, 601 int slice, 602 int srcX0, int srcY0, 603 int dstX0, int dstY0, 604 int width, int height) 605 { 606 struct gl_context *ctx = &brw->ctx; 607 struct intel_renderbuffer *src_irb = intel_renderbuffer(src_rb); 608 struct intel_texture_image *intel_image = intel_texture_image(dst_image); 609 610 /* No pixel transfer operations (zoom, bias, mapping), just a blit */ 611 if (brw->ctx._ImageTransferState) 612 return false; 613 614 /* Sync up the state of window system buffers. We need to do this before 615 * we go looking at the src renderbuffer's miptree. 616 */ 617 intel_prepare_render(brw); 618 619 struct intel_mipmap_tree *src_mt = src_irb->mt; 620 struct intel_mipmap_tree *dst_mt = intel_image->mt; 621 622 /* There is support for only up to eight samples. */ 623 if (src_mt->num_samples > 8 || dst_mt->num_samples > 8) 624 return false; 625 626 /* BLORP is only supported from Gen6 onwards. */ 627 if (brw->gen < 6) 628 return false; 629 630 if (_mesa_get_format_base_format(src_rb->Format) != 631 _mesa_get_format_base_format(dst_image->TexFormat)) { 632 return false; 633 } 634 635 /* We can't handle format conversions between Z24 and other formats since 636 * we have to lie about the surface format. See the comments in 637 * brw_blorp_surface_info::set(). 638 */ 639 if ((src_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT) != 640 (dst_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT)) { 641 return false; 642 } 643 644 if (!brw->format_supported_as_render_target[dst_image->TexFormat]) 645 return false; 646 647 /* Source clipping shouldn't be necessary, since copytexsubimage (in 648 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which 649 * takes care of it. 650 * 651 * Destination clipping shouldn't be necessary since the restrictions on 652 * glCopyTexSubImage prevent the user from specifying a destination rectangle 653 * that falls outside the bounds of the destination texture. 654 * See error_check_subtexture_dimensions(). 655 */ 656 657 int srcY1 = srcY0 + height; 658 int srcX1 = srcX0 + width; 659 int dstX1 = dstX0 + width; 660 int dstY1 = dstY0 + height; 661 662 /* Account for the fact that in the system framebuffer, the origin is at 663 * the lower left. 664 */ 665 bool mirror_y = false; 666 if (_mesa_is_winsys_fbo(ctx->ReadBuffer)) { 667 GLint tmp = src_rb->Height - srcY0; 668 srcY0 = src_rb->Height - srcY1; 669 srcY1 = tmp; 670 mirror_y = true; 671 } 672 673 /* Account for face selection and texture view MinLayer */ 674 int dst_slice = slice + dst_image->TexObject->MinLayer + dst_image->Face; 675 int dst_level = dst_image->Level + dst_image->TexObject->MinLevel; 676 677 brw_blorp_blit_miptrees(brw, 678 src_mt, src_irb->mt_level, src_irb->mt_layer, 679 src_rb->Format, blorp_get_texture_swizzle(src_irb), 680 dst_mt, dst_level, dst_slice, 681 dst_image->TexFormat, 682 srcX0, srcY0, srcX1, srcY1, 683 dstX0, dstY0, dstX1, dstY1, 684 GL_NEAREST, false, mirror_y, 685 false, false); 686 687 /* If we're copying to a packed depth stencil texture and the source 688 * framebuffer has separate stencil, we need to also copy the stencil data 689 * over. 690 */ 691 src_rb = ctx->ReadBuffer->Attachment[BUFFER_STENCIL].Renderbuffer; 692 if (_mesa_get_format_bits(dst_image->TexFormat, GL_STENCIL_BITS) > 0 && 693 src_rb != NULL) { 694 src_irb = intel_renderbuffer(src_rb); 695 src_mt = src_irb->mt; 696 697 if (src_mt->stencil_mt) 698 src_mt = src_mt->stencil_mt; 699 if (dst_mt->stencil_mt) 700 dst_mt = dst_mt->stencil_mt; 701 702 if (src_mt != dst_mt) { 703 brw_blorp_blit_miptrees(brw, 704 src_mt, src_irb->mt_level, src_irb->mt_layer, 705 src_mt->format, 706 blorp_get_texture_swizzle(src_irb), 707 dst_mt, dst_level, dst_slice, 708 dst_mt->format, 709 srcX0, srcY0, srcX1, srcY1, 710 dstX0, dstY0, dstX1, dstY1, 711 GL_NEAREST, false, mirror_y, 712 false, false); 713 } 714 } 715 716 return true; 717 } 718 719 720 GLbitfield 721 brw_blorp_framebuffer(struct brw_context *brw, 722 struct gl_framebuffer *readFb, 723 struct gl_framebuffer *drawFb, 724 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1, 725 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, 726 GLbitfield mask, GLenum filter) 727 { 728 /* BLORP is not supported before Gen6. */ 729 if (brw->gen < 6) 730 return mask; 731 732 static GLbitfield buffer_bits[] = { 733 GL_COLOR_BUFFER_BIT, 734 GL_DEPTH_BUFFER_BIT, 735 GL_STENCIL_BUFFER_BIT, 736 }; 737 738 for (unsigned int i = 0; i < ARRAY_SIZE(buffer_bits); ++i) { 739 if ((mask & buffer_bits[i]) && 740 try_blorp_blit(brw, readFb, drawFb, 741 srcX0, srcY0, srcX1, srcY1, 742 dstX0, dstY0, dstX1, dstY1, 743 filter, buffer_bits[i])) { 744 mask &= ~buffer_bits[i]; 745 } 746 } 747 748 return mask; 749 } 750 751 static bool 752 set_write_disables(const struct intel_renderbuffer *irb, 753 const GLubyte *color_mask, bool *color_write_disable) 754 { 755 /* Format information in the renderbuffer represents the requirements 756 * given by the client. There are cases where the backing miptree uses, 757 * for example, RGBA to represent RGBX. Since the client is only expecting 758 * RGB we can treat alpha as not used and write whatever we like into it. 759 */ 760 const GLenum base_format = irb->Base.Base._BaseFormat; 761 const int components = _mesa_base_format_component_count(base_format); 762 bool disables = false; 763 764 assert(components > 0); 765 766 for (int i = 0; i < components; i++) { 767 color_write_disable[i] = !color_mask[i]; 768 disables = disables || !color_mask[i]; 769 } 770 771 return disables; 772 } 773 774 static unsigned 775 irb_logical_mt_layer(struct intel_renderbuffer *irb) 776 { 777 return physical_to_logical_layer(irb->mt, irb->mt_layer); 778 } 779 780 static bool 781 do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, 782 struct gl_renderbuffer *rb, unsigned buf, 783 bool partial_clear, bool encode_srgb) 784 { 785 struct gl_context *ctx = &brw->ctx; 786 struct intel_renderbuffer *irb = intel_renderbuffer(rb); 787 mesa_format format = irb->mt->format; 788 uint32_t x0, x1, y0, y1; 789 790 if (!encode_srgb && _mesa_get_format_color_encoding(format) == GL_SRGB) 791 format = _mesa_get_srgb_format_linear(format); 792 793 x0 = fb->_Xmin; 794 x1 = fb->_Xmax; 795 if (rb->Name != 0) { 796 y0 = fb->_Ymin; 797 y1 = fb->_Ymax; 798 } else { 799 y0 = rb->Height - fb->_Ymax; 800 y1 = rb->Height - fb->_Ymin; 801 } 802 803 /* If the clear region is empty, just return. */ 804 if (x0 == x1 || y0 == y1) 805 return true; 806 807 bool can_fast_clear = !partial_clear; 808 809 bool color_write_disable[4] = { false, false, false, false }; 810 if (set_write_disables(irb, ctx->Color.ColorMask[buf], color_write_disable)) 811 can_fast_clear = false; 812 813 if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS || 814 !brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->Color.ClearColor)) 815 can_fast_clear = false; 816 817 const unsigned logical_layer = irb_logical_mt_layer(irb); 818 const enum intel_fast_clear_state fast_clear_state = 819 intel_miptree_get_fast_clear_state(irb->mt, irb->mt_level, 820 logical_layer); 821 822 /* Surface state can only record one fast clear color value. Therefore 823 * unless different levels/layers agree on the color it can be used to 824 * represent only single level/layer. Here it will be reserved for the 825 * first slice (level 0, layer 0). 826 */ 827 if (irb->layer_count > 1 || irb->mt_level || irb->mt_layer) 828 can_fast_clear = false; 829 830 if (can_fast_clear) { 831 union gl_color_union override_color = 832 brw_meta_convert_fast_clear_color(brw, irb->mt, 833 &ctx->Color.ClearColor); 834 835 /* Record the clear color in the miptree so that it will be 836 * programmed in SURFACE_STATE by later rendering and resolve 837 * operations. 838 */ 839 const bool color_updated = brw_meta_set_fast_clear_color( 840 brw, &irb->mt->gen9_fast_clear_color, 841 &override_color); 842 843 /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear 844 * is redundant and can be skipped. 845 */ 846 if (!color_updated && fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR) 847 return true; 848 849 /* If the MCS buffer hasn't been allocated yet, we need to allocate 850 * it now. 851 */ 852 if (!irb->mt->mcs_buf) { 853 assert(!intel_miptree_is_lossless_compressed(brw, irb->mt)); 854 if (!intel_miptree_alloc_non_msrt_mcs(brw, irb->mt, false)) { 855 /* MCS allocation failed--probably this will only happen in 856 * out-of-memory conditions. But in any case, try to recover 857 * by falling back to a non-blorp clear technique. 858 */ 859 return false; 860 } 861 } 862 } 863 864 const unsigned num_layers = fb->MaxNumLayers ? irb->layer_count : 1; 865 866 /* We can't setup the blorp_surf until we've allocated the MCS above */ 867 struct isl_surf isl_tmp[2]; 868 struct blorp_surf surf; 869 unsigned level = irb->mt_level; 870 blorp_surf_for_miptree(brw, &surf, irb->mt, true, 871 (1 << ISL_AUX_USAGE_MCS) | 872 (1 << ISL_AUX_USAGE_CCS_E) | 873 (1 << ISL_AUX_USAGE_CCS_D), 874 &level, logical_layer, num_layers, isl_tmp); 875 876 if (can_fast_clear) { 877 DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__, 878 irb->mt, irb->mt_level, irb->mt_layer, num_layers); 879 880 struct blorp_batch batch; 881 blorp_batch_init(&brw->blorp, &batch, brw, 0); 882 blorp_fast_clear(&batch, &surf, 883 (enum isl_format)brw->render_target_format[format], 884 level, logical_layer, num_layers, 885 x0, y0, x1, y1); 886 blorp_batch_finish(&batch); 887 888 /* Now that the fast clear has occurred, put the buffer in 889 * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing 890 * redundant clears. 891 */ 892 intel_miptree_set_fast_clear_state(brw, irb->mt, irb->mt_level, 893 logical_layer, num_layers, 894 INTEL_FAST_CLEAR_STATE_CLEAR); 895 } else { 896 DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__, 897 irb->mt, irb->mt_level, irb->mt_layer, num_layers); 898 899 union isl_color_value clear_color; 900 memcpy(clear_color.f32, ctx->Color.ClearColor.f, sizeof(float) * 4); 901 902 struct blorp_batch batch; 903 blorp_batch_init(&brw->blorp, &batch, brw, 0); 904 blorp_clear(&batch, &surf, 905 (enum isl_format)brw->render_target_format[format], 906 ISL_SWIZZLE_IDENTITY, 907 level, irb_logical_mt_layer(irb), num_layers, 908 x0, y0, x1, y1, 909 clear_color, color_write_disable); 910 blorp_batch_finish(&batch); 911 } 912 913 /* 914 * Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)": 915 * 916 * Any transition from any value in {Clear, Render, Resolve} to a 917 * different value in {Clear, Render, Resolve} requires end of pipe 918 * synchronization. 919 */ 920 brw_emit_pipe_control_flush(brw, 921 PIPE_CONTROL_RENDER_TARGET_FLUSH | 922 PIPE_CONTROL_CS_STALL); 923 924 return true; 925 } 926 927 bool 928 brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb, 929 GLbitfield mask, bool partial_clear, bool encode_srgb) 930 { 931 for (unsigned buf = 0; buf < fb->_NumColorDrawBuffers; buf++) { 932 struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[buf]; 933 struct intel_renderbuffer *irb = intel_renderbuffer(rb); 934 935 /* Only clear the buffers present in the provided mask */ 936 if (((1 << fb->_ColorDrawBufferIndexes[buf]) & mask) == 0) 937 continue; 938 939 /* If this is an ES2 context or GL_ARB_ES2_compatibility is supported, 940 * the framebuffer can be complete with some attachments missing. In 941 * this case the _ColorDrawBuffers pointer will be NULL. 942 */ 943 if (rb == NULL) 944 continue; 945 946 if (!do_single_blorp_clear(brw, fb, rb, buf, partial_clear, 947 encode_srgb)) { 948 return false; 949 } 950 951 irb->need_downsample = true; 952 } 953 954 return true; 955 } 956 957 void 958 brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt, 959 unsigned level, unsigned layer) 960 { 961 DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer); 962 963 const mesa_format format = _mesa_get_srgb_format_linear(mt->format); 964 965 struct isl_surf isl_tmp[2]; 966 struct blorp_surf surf; 967 blorp_surf_for_miptree(brw, &surf, mt, true, 968 (1 << ISL_AUX_USAGE_CCS_E) | 969 (1 << ISL_AUX_USAGE_CCS_D), 970 &level, layer, 1 /* num_layers */, 971 isl_tmp); 972 973 enum blorp_fast_clear_op resolve_op; 974 if (brw->gen >= 9) { 975 if (surf.aux_usage == ISL_AUX_USAGE_CCS_E) 976 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL; 977 else 978 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL; 979 } else { 980 assert(surf.aux_usage == ISL_AUX_USAGE_CCS_D); 981 /* Broadwell and earlier do not have a partial resolve */ 982 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL; 983 } 984 985 struct blorp_batch batch; 986 blorp_batch_init(&brw->blorp, &batch, brw, 0); 987 blorp_ccs_resolve(&batch, &surf, level, layer, 988 brw_blorp_to_isl_format(brw, format, true), 989 resolve_op); 990 blorp_batch_finish(&batch); 991 992 /* 993 * Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)": 994 * 995 * Any transition from any value in {Clear, Render, Resolve} to a 996 * different value in {Clear, Render, Resolve} requires end of pipe 997 * synchronization. 998 */ 999 brw_emit_pipe_control_flush(brw, 1000 PIPE_CONTROL_RENDER_TARGET_FLUSH | 1001 PIPE_CONTROL_CS_STALL); 1002 } 1003 1004 static void 1005 gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, 1006 unsigned int level, unsigned int layer, enum blorp_hiz_op op) 1007 { 1008 assert(intel_miptree_level_has_hiz(mt, level)); 1009 1010 struct isl_surf isl_tmp[2]; 1011 struct blorp_surf surf; 1012 blorp_surf_for_miptree(brw, &surf, mt, true, (1 << ISL_AUX_USAGE_HIZ), 1013 &level, layer, 1, isl_tmp); 1014 1015 struct blorp_batch batch; 1016 blorp_batch_init(&brw->blorp, &batch, brw, 0); 1017 blorp_gen6_hiz_op(&batch, &surf, level, layer, op); 1018 blorp_batch_finish(&batch); 1019 } 1020 1021 /** 1022 * Perform a HiZ or depth resolve operation. 1023 * 1024 * For an overview of HiZ ops, see the following sections of the Sandy Bridge 1025 * PRM, Volume 1, Part 2: 1026 * - 7.5.3.1 Depth Buffer Clear 1027 * - 7.5.3.2 Depth Buffer Resolve 1028 * - 7.5.3.3 Hierarchical Depth Buffer Resolve 1029 */ 1030 void 1031 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, 1032 unsigned int level, unsigned int layer, enum blorp_hiz_op op) 1033 { 1034 const char *opname = NULL; 1035 1036 switch (op) { 1037 case BLORP_HIZ_OP_DEPTH_RESOLVE: 1038 opname = "depth resolve"; 1039 break; 1040 case BLORP_HIZ_OP_HIZ_RESOLVE: 1041 opname = "hiz ambiguate"; 1042 break; 1043 case BLORP_HIZ_OP_DEPTH_CLEAR: 1044 opname = "depth clear"; 1045 break; 1046 case BLORP_HIZ_OP_NONE: 1047 opname = "noop?"; 1048 break; 1049 } 1050 1051 DBG("%s %s to mt %p level %d layer %d\n", 1052 __func__, opname, mt, level, layer); 1053 1054 if (brw->gen >= 8) { 1055 gen8_hiz_exec(brw, mt, level, layer, op); 1056 } else { 1057 gen6_blorp_hiz_exec(brw, mt, level, layer, op); 1058 } 1059 } 1060
