1 /* 2 * Copyright 2014-2015 Broadcom 3 * Copyright (C) 2014 Rob Clark <robclark (at) freedesktop.org> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22 * IN THE SOFTWARE. 23 */ 24 25 #include "util/ralloc.h" 26 #include "compiler/nir/nir.h" 27 #include "compiler/nir/nir_control_flow.h" 28 #include "compiler/nir/nir_builder.h" 29 #include "compiler/glsl/list.h" 30 #include "compiler/shader_enums.h" 31 32 #include "tgsi_to_nir.h" 33 #include "tgsi/tgsi_parse.h" 34 #include "tgsi/tgsi_dump.h" 35 #include "tgsi/tgsi_info.h" 36 #include "tgsi/tgsi_scan.h" 37 38 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \ 39 TGSI_SWIZZLE_##X, \ 40 TGSI_SWIZZLE_##Y, \ 41 TGSI_SWIZZLE_##Z, \ 42 TGSI_SWIZZLE_##W, \ 43 } 44 45 struct ttn_reg_info { 46 /** nir register containing this TGSI index. */ 47 nir_register *reg; 48 nir_variable *var; 49 /** Offset (in vec4s) from the start of var for this TGSI index. */ 50 int offset; 51 }; 52 53 struct ttn_compile { 54 union tgsi_full_token *token; 55 nir_builder build; 56 struct tgsi_shader_info *scan; 57 58 struct ttn_reg_info *output_regs; 59 struct ttn_reg_info *temp_regs; 60 nir_ssa_def **imm_defs; 61 62 unsigned num_samp_types; 63 nir_alu_type *samp_types; 64 65 nir_register *addr_reg; 66 67 /** 68 * Stack of nir_cursors where instructions should be pushed as we pop 69 * back out of the control flow stack. 70 * 71 * For each IF/ELSE/ENDIF block, if_stack[if_stack_pos] has where the else 72 * instructions should be placed, and if_stack[if_stack_pos - 1] has where 73 * the next instructions outside of the if/then/else block go. 74 */ 75 nir_cursor *if_stack; 76 unsigned if_stack_pos; 77 78 /** 79 * Stack of nir_cursors where instructions should be pushed as we pop 80 * back out of the control flow stack. 81 * 82 * loop_stack[loop_stack_pos - 1] contains the cf_node_list for the outside 83 * of the loop. 84 */ 85 nir_cursor *loop_stack; 86 unsigned loop_stack_pos; 87 88 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */ 89 unsigned next_imm; 90 }; 91 92 #define ttn_swizzle(b, src, x, y, z, w) \ 93 nir_swizzle(b, src, SWIZ(x, y, z, w), 4, false) 94 #define ttn_channel(b, src, swiz) \ 95 nir_swizzle(b, src, SWIZ(swiz, swiz, swiz, swiz), 1, false) 96 97 static gl_varying_slot 98 tgsi_varying_semantic_to_slot(unsigned semantic, unsigned index) 99 { 100 switch (semantic) { 101 case TGSI_SEMANTIC_POSITION: 102 return VARYING_SLOT_POS; 103 case TGSI_SEMANTIC_COLOR: 104 if (index == 0) 105 return VARYING_SLOT_COL0; 106 else 107 return VARYING_SLOT_COL1; 108 case TGSI_SEMANTIC_BCOLOR: 109 if (index == 0) 110 return VARYING_SLOT_BFC0; 111 else 112 return VARYING_SLOT_BFC1; 113 case TGSI_SEMANTIC_FOG: 114 return VARYING_SLOT_FOGC; 115 case TGSI_SEMANTIC_PSIZE: 116 return VARYING_SLOT_PSIZ; 117 case TGSI_SEMANTIC_GENERIC: 118 return VARYING_SLOT_VAR0 + index; 119 case TGSI_SEMANTIC_FACE: 120 return VARYING_SLOT_FACE; 121 case TGSI_SEMANTIC_EDGEFLAG: 122 return VARYING_SLOT_EDGE; 123 case TGSI_SEMANTIC_PRIMID: 124 return VARYING_SLOT_PRIMITIVE_ID; 125 case TGSI_SEMANTIC_CLIPDIST: 126 if (index == 0) 127 return VARYING_SLOT_CLIP_DIST0; 128 else 129 return VARYING_SLOT_CLIP_DIST1; 130 case TGSI_SEMANTIC_CLIPVERTEX: 131 return VARYING_SLOT_CLIP_VERTEX; 132 case TGSI_SEMANTIC_TEXCOORD: 133 return VARYING_SLOT_TEX0 + index; 134 case TGSI_SEMANTIC_PCOORD: 135 return VARYING_SLOT_PNTC; 136 case TGSI_SEMANTIC_VIEWPORT_INDEX: 137 return VARYING_SLOT_VIEWPORT; 138 case TGSI_SEMANTIC_LAYER: 139 return VARYING_SLOT_LAYER; 140 default: 141 fprintf(stderr, "Bad TGSI semantic: %d/%d\n", semantic, index); 142 abort(); 143 } 144 } 145 146 /* Temporary helper to remap back to TGSI style semantic name/index 147 * values, for use in drivers that haven't been converted to using 148 * VARYING_SLOT_ 149 */ 150 void 151 varying_slot_to_tgsi_semantic(gl_varying_slot slot, 152 unsigned *semantic_name, unsigned *semantic_index) 153 { 154 static const unsigned map[][2] = { 155 [VARYING_SLOT_POS] = { TGSI_SEMANTIC_POSITION, 0 }, 156 [VARYING_SLOT_COL0] = { TGSI_SEMANTIC_COLOR, 0 }, 157 [VARYING_SLOT_COL1] = { TGSI_SEMANTIC_COLOR, 1 }, 158 [VARYING_SLOT_BFC0] = { TGSI_SEMANTIC_BCOLOR, 0 }, 159 [VARYING_SLOT_BFC1] = { TGSI_SEMANTIC_BCOLOR, 1 }, 160 [VARYING_SLOT_FOGC] = { TGSI_SEMANTIC_FOG, 0 }, 161 [VARYING_SLOT_PSIZ] = { TGSI_SEMANTIC_PSIZE, 0 }, 162 [VARYING_SLOT_FACE] = { TGSI_SEMANTIC_FACE, 0 }, 163 [VARYING_SLOT_EDGE] = { TGSI_SEMANTIC_EDGEFLAG, 0 }, 164 [VARYING_SLOT_PRIMITIVE_ID] = { TGSI_SEMANTIC_PRIMID, 0 }, 165 [VARYING_SLOT_CLIP_DIST0] = { TGSI_SEMANTIC_CLIPDIST, 0 }, 166 [VARYING_SLOT_CLIP_DIST1] = { TGSI_SEMANTIC_CLIPDIST, 1 }, 167 [VARYING_SLOT_CLIP_VERTEX] = { TGSI_SEMANTIC_CLIPVERTEX, 0 }, 168 [VARYING_SLOT_PNTC] = { TGSI_SEMANTIC_PCOORD, 0 }, 169 [VARYING_SLOT_VIEWPORT] = { TGSI_SEMANTIC_VIEWPORT_INDEX, 0 }, 170 [VARYING_SLOT_LAYER] = { TGSI_SEMANTIC_LAYER, 0 }, 171 }; 172 173 if (slot >= VARYING_SLOT_VAR0) { 174 *semantic_name = TGSI_SEMANTIC_GENERIC; 175 *semantic_index = slot - VARYING_SLOT_VAR0; 176 return; 177 } 178 179 if (slot >= VARYING_SLOT_TEX0 && slot <= VARYING_SLOT_TEX7) { 180 *semantic_name = TGSI_SEMANTIC_TEXCOORD; 181 *semantic_index = slot - VARYING_SLOT_TEX0; 182 return; 183 } 184 185 if (slot >= ARRAY_SIZE(map)) { 186 fprintf(stderr, "Unknown varying slot %d\n", slot); 187 abort(); 188 } 189 190 *semantic_name = map[slot][0]; 191 *semantic_index = map[slot][1]; 192 } 193 194 /* Temporary helper to remap back to TGSI style semantic name/index 195 * values, for use in drivers that haven't been converted to using 196 * FRAG_RESULT_ 197 */ 198 void 199 frag_result_to_tgsi_semantic(gl_frag_result slot, 200 unsigned *semantic_name, unsigned *semantic_index) 201 { 202 static const unsigned map[][2] = { 203 [FRAG_RESULT_DEPTH] = { TGSI_SEMANTIC_POSITION, 0 }, 204 [FRAG_RESULT_COLOR] = { TGSI_SEMANTIC_COLOR, -1 }, 205 [FRAG_RESULT_DATA0 + 0] = { TGSI_SEMANTIC_COLOR, 0 }, 206 [FRAG_RESULT_DATA0 + 1] = { TGSI_SEMANTIC_COLOR, 1 }, 207 [FRAG_RESULT_DATA0 + 2] = { TGSI_SEMANTIC_COLOR, 2 }, 208 [FRAG_RESULT_DATA0 + 3] = { TGSI_SEMANTIC_COLOR, 3 }, 209 [FRAG_RESULT_DATA0 + 4] = { TGSI_SEMANTIC_COLOR, 4 }, 210 [FRAG_RESULT_DATA0 + 5] = { TGSI_SEMANTIC_COLOR, 5 }, 211 [FRAG_RESULT_DATA0 + 6] = { TGSI_SEMANTIC_COLOR, 6 }, 212 [FRAG_RESULT_DATA0 + 7] = { TGSI_SEMANTIC_COLOR, 7 }, 213 }; 214 215 *semantic_name = map[slot][0]; 216 *semantic_index = map[slot][1]; 217 } 218 219 static nir_ssa_def * 220 ttn_src_for_dest(nir_builder *b, nir_alu_dest *dest) 221 { 222 nir_alu_src src; 223 memset(&src, 0, sizeof(src)); 224 225 if (dest->dest.is_ssa) 226 src.src = nir_src_for_ssa(&dest->dest.ssa); 227 else { 228 assert(!dest->dest.reg.indirect); 229 src.src = nir_src_for_reg(dest->dest.reg.reg); 230 src.src.reg.base_offset = dest->dest.reg.base_offset; 231 } 232 233 for (int i = 0; i < 4; i++) 234 src.swizzle[i] = i; 235 236 return nir_fmov_alu(b, src, 4); 237 } 238 239 static void 240 ttn_emit_declaration(struct ttn_compile *c) 241 { 242 nir_builder *b = &c->build; 243 struct tgsi_full_declaration *decl = &c->token->FullDeclaration; 244 unsigned array_size = decl->Range.Last - decl->Range.First + 1; 245 unsigned file = decl->Declaration.File; 246 unsigned i; 247 248 if (file == TGSI_FILE_TEMPORARY) { 249 if (decl->Declaration.Array) { 250 /* for arrays, we create variables instead of registers: */ 251 nir_variable *var = rzalloc(b->shader, nir_variable); 252 253 var->type = glsl_array_type(glsl_vec4_type(), array_size); 254 var->data.mode = nir_var_global; 255 var->name = ralloc_asprintf(var, "arr_%d", decl->Array.ArrayID); 256 257 exec_list_push_tail(&b->shader->globals, &var->node); 258 259 for (i = 0; i < array_size; i++) { 260 /* point all the matching slots to the same var, 261 * with appropriate offset set, mostly just so 262 * we know what to do when tgsi does a non-indirect 263 * access 264 */ 265 c->temp_regs[decl->Range.First + i].reg = NULL; 266 c->temp_regs[decl->Range.First + i].var = var; 267 c->temp_regs[decl->Range.First + i].offset = i; 268 } 269 } else { 270 for (i = 0; i < array_size; i++) { 271 nir_register *reg = nir_local_reg_create(b->impl); 272 reg->num_components = 4; 273 c->temp_regs[decl->Range.First + i].reg = reg; 274 c->temp_regs[decl->Range.First + i].var = NULL; 275 c->temp_regs[decl->Range.First + i].offset = 0; 276 } 277 } 278 } else if (file == TGSI_FILE_ADDRESS) { 279 c->addr_reg = nir_local_reg_create(b->impl); 280 c->addr_reg->num_components = 4; 281 } else if (file == TGSI_FILE_SYSTEM_VALUE) { 282 /* Nothing to record for system values. */ 283 } else if (file == TGSI_FILE_SAMPLER) { 284 /* Nothing to record for samplers. */ 285 } else if (file == TGSI_FILE_SAMPLER_VIEW) { 286 struct tgsi_declaration_sampler_view *sview = &decl->SamplerView; 287 nir_alu_type type; 288 289 assert((sview->ReturnTypeX == sview->ReturnTypeY) && 290 (sview->ReturnTypeX == sview->ReturnTypeZ) && 291 (sview->ReturnTypeX == sview->ReturnTypeW)); 292 293 switch (sview->ReturnTypeX) { 294 case TGSI_RETURN_TYPE_SINT: 295 type = nir_type_int; 296 break; 297 case TGSI_RETURN_TYPE_UINT: 298 type = nir_type_uint; 299 break; 300 case TGSI_RETURN_TYPE_FLOAT: 301 default: 302 type = nir_type_float; 303 break; 304 } 305 306 for (i = 0; i < array_size; i++) { 307 c->samp_types[decl->Range.First + i] = type; 308 } 309 } else { 310 bool is_array = (array_size > 1); 311 312 assert(file == TGSI_FILE_INPUT || 313 file == TGSI_FILE_OUTPUT || 314 file == TGSI_FILE_CONSTANT); 315 316 /* nothing to do for UBOs: */ 317 if ((file == TGSI_FILE_CONSTANT) && decl->Declaration.Dimension) { 318 b->shader->info->num_ubos = 319 MAX2(b->shader->info->num_ubos, decl->Dim.Index2D); 320 return; 321 } 322 323 if ((file == TGSI_FILE_INPUT) || (file == TGSI_FILE_OUTPUT)) { 324 is_array = (is_array && decl->Declaration.Array && 325 (decl->Array.ArrayID != 0)); 326 } 327 328 for (i = 0; i < array_size; i++) { 329 unsigned idx = decl->Range.First + i; 330 nir_variable *var = rzalloc(b->shader, nir_variable); 331 332 var->data.driver_location = idx; 333 334 var->type = glsl_vec4_type(); 335 if (is_array) 336 var->type = glsl_array_type(var->type, array_size); 337 338 switch (file) { 339 case TGSI_FILE_INPUT: 340 var->data.read_only = true; 341 var->data.mode = nir_var_shader_in; 342 var->name = ralloc_asprintf(var, "in_%d", idx); 343 344 if (c->scan->processor == PIPE_SHADER_FRAGMENT) { 345 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) { 346 var->data.location = SYSTEM_VALUE_FRONT_FACE; 347 var->data.mode = nir_var_system_value; 348 } else { 349 var->data.location = 350 tgsi_varying_semantic_to_slot(decl->Semantic.Name, 351 decl->Semantic.Index); 352 } 353 } else { 354 assert(!decl->Declaration.Semantic); 355 var->data.location = VERT_ATTRIB_GENERIC0 + idx; 356 } 357 var->data.index = 0; 358 359 /* We definitely need to translate the interpolation field, because 360 * nir_print will decode it. 361 */ 362 switch (decl->Interp.Interpolate) { 363 case TGSI_INTERPOLATE_CONSTANT: 364 var->data.interpolation = INTERP_MODE_FLAT; 365 break; 366 case TGSI_INTERPOLATE_LINEAR: 367 var->data.interpolation = INTERP_MODE_NOPERSPECTIVE; 368 break; 369 case TGSI_INTERPOLATE_PERSPECTIVE: 370 var->data.interpolation = INTERP_MODE_SMOOTH; 371 break; 372 } 373 374 exec_list_push_tail(&b->shader->inputs, &var->node); 375 376 for (int i = 0; i < array_size; i++) 377 b->shader->info->inputs_read |= 1 << (var->data.location + i); 378 379 break; 380 case TGSI_FILE_OUTPUT: { 381 int semantic_name = decl->Semantic.Name; 382 int semantic_index = decl->Semantic.Index; 383 /* Since we can't load from outputs in the IR, we make temporaries 384 * for the outputs and emit stores to the real outputs at the end of 385 * the shader. 386 */ 387 nir_register *reg = nir_local_reg_create(b->impl); 388 reg->num_components = 4; 389 if (is_array) 390 reg->num_array_elems = array_size; 391 392 var->data.mode = nir_var_shader_out; 393 var->name = ralloc_asprintf(var, "out_%d", idx); 394 var->data.index = 0; 395 396 if (c->scan->processor == PIPE_SHADER_FRAGMENT) { 397 switch (semantic_name) { 398 case TGSI_SEMANTIC_COLOR: { 399 /* TODO tgsi loses some information, so we cannot 400 * actually differentiate here between DSB and MRT 401 * at this point. But so far no drivers using tgsi- 402 * to-nir support dual source blend: 403 */ 404 bool dual_src_blend = false; 405 if (dual_src_blend && (semantic_index == 1)) { 406 var->data.location = FRAG_RESULT_DATA0; 407 var->data.index = 1; 408 } else { 409 if (c->scan->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS]) 410 var->data.location = FRAG_RESULT_COLOR; 411 else 412 var->data.location = FRAG_RESULT_DATA0 + semantic_index; 413 } 414 break; 415 } 416 case TGSI_SEMANTIC_POSITION: 417 var->data.location = FRAG_RESULT_DEPTH; 418 break; 419 default: 420 fprintf(stderr, "Bad TGSI semantic: %d/%d\n", 421 decl->Semantic.Name, decl->Semantic.Index); 422 abort(); 423 } 424 } else { 425 var->data.location = 426 tgsi_varying_semantic_to_slot(semantic_name, semantic_index); 427 } 428 429 if (is_array) { 430 unsigned j; 431 for (j = 0; j < array_size; j++) { 432 c->output_regs[idx + j].offset = i + j; 433 c->output_regs[idx + j].reg = reg; 434 } 435 } else { 436 c->output_regs[idx].offset = i; 437 c->output_regs[idx].reg = reg; 438 } 439 440 exec_list_push_tail(&b->shader->outputs, &var->node); 441 442 for (int i = 0; i < array_size; i++) 443 b->shader->info->outputs_written |= 1 << (var->data.location + i); 444 } 445 break; 446 case TGSI_FILE_CONSTANT: 447 var->data.mode = nir_var_uniform; 448 var->name = ralloc_asprintf(var, "uniform_%d", idx); 449 450 exec_list_push_tail(&b->shader->uniforms, &var->node); 451 break; 452 default: 453 unreachable("bad declaration file"); 454 return; 455 } 456 457 if (is_array) 458 break; 459 } 460 461 } 462 } 463 464 static void 465 ttn_emit_immediate(struct ttn_compile *c) 466 { 467 nir_builder *b = &c->build; 468 struct tgsi_full_immediate *tgsi_imm = &c->token->FullImmediate; 469 nir_load_const_instr *load_const; 470 int i; 471 472 load_const = nir_load_const_instr_create(b->shader, 4, 32); 473 c->imm_defs[c->next_imm] = &load_const->def; 474 c->next_imm++; 475 476 for (i = 0; i < 4; i++) 477 load_const->value.u32[i] = tgsi_imm->u[i].Uint; 478 479 nir_builder_instr_insert(b, &load_const->instr); 480 } 481 482 static nir_ssa_def * 483 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect); 484 485 /* generate either a constant or indirect deref chain for accessing an 486 * array variable. 487 */ 488 static nir_deref_var * 489 ttn_array_deref(struct ttn_compile *c, nir_intrinsic_instr *instr, 490 nir_variable *var, unsigned offset, 491 struct tgsi_ind_register *indirect) 492 { 493 nir_deref_var *deref = nir_deref_var_create(instr, var); 494 nir_deref_array *arr = nir_deref_array_create(deref); 495 496 arr->base_offset = offset; 497 arr->deref.type = glsl_get_array_element(var->type); 498 499 if (indirect) { 500 arr->deref_array_type = nir_deref_array_type_indirect; 501 arr->indirect = nir_src_for_ssa(ttn_src_for_indirect(c, indirect)); 502 } else { 503 arr->deref_array_type = nir_deref_array_type_direct; 504 } 505 506 deref->deref.child = &arr->deref; 507 508 return deref; 509 } 510 511 static nir_src 512 ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index, 513 struct tgsi_ind_register *indirect, 514 struct tgsi_dimension *dim, 515 struct tgsi_ind_register *dimind) 516 { 517 nir_builder *b = &c->build; 518 nir_src src; 519 520 memset(&src, 0, sizeof(src)); 521 522 switch (file) { 523 case TGSI_FILE_TEMPORARY: 524 if (c->temp_regs[index].var) { 525 unsigned offset = c->temp_regs[index].offset; 526 nir_variable *var = c->temp_regs[index].var; 527 nir_intrinsic_instr *load; 528 529 load = nir_intrinsic_instr_create(b->shader, 530 nir_intrinsic_load_var); 531 load->num_components = 4; 532 load->variables[0] = ttn_array_deref(c, load, var, offset, indirect); 533 nir_ssa_dest_init(&load->instr, &load->dest, 534 4, 32, NULL); 535 nir_builder_instr_insert(b, &load->instr); 536 537 src = nir_src_for_ssa(&load->dest.ssa); 538 539 } else { 540 assert(!indirect); 541 src.reg.reg = c->temp_regs[index].reg; 542 } 543 assert(!dim); 544 break; 545 546 case TGSI_FILE_ADDRESS: 547 src.reg.reg = c->addr_reg; 548 assert(!dim); 549 break; 550 551 case TGSI_FILE_IMMEDIATE: 552 src = nir_src_for_ssa(c->imm_defs[index]); 553 assert(!indirect); 554 assert(!dim); 555 break; 556 557 case TGSI_FILE_SYSTEM_VALUE: { 558 nir_intrinsic_instr *load; 559 nir_intrinsic_op op; 560 unsigned ncomp = 1; 561 562 assert(!indirect); 563 assert(!dim); 564 565 switch (c->scan->system_value_semantic_name[index]) { 566 case TGSI_SEMANTIC_VERTEXID_NOBASE: 567 op = nir_intrinsic_load_vertex_id_zero_base; 568 break; 569 case TGSI_SEMANTIC_VERTEXID: 570 op = nir_intrinsic_load_vertex_id; 571 break; 572 case TGSI_SEMANTIC_BASEVERTEX: 573 op = nir_intrinsic_load_base_vertex; 574 break; 575 case TGSI_SEMANTIC_INSTANCEID: 576 op = nir_intrinsic_load_instance_id; 577 break; 578 default: 579 unreachable("bad system value"); 580 } 581 582 load = nir_intrinsic_instr_create(b->shader, op); 583 load->num_components = ncomp; 584 585 nir_ssa_dest_init(&load->instr, &load->dest, ncomp, 32, NULL); 586 nir_builder_instr_insert(b, &load->instr); 587 588 src = nir_src_for_ssa(&load->dest.ssa); 589 590 b->shader->info->system_values_read |= 591 (1 << nir_system_value_from_intrinsic(op)); 592 593 break; 594 } 595 596 case TGSI_FILE_INPUT: 597 case TGSI_FILE_CONSTANT: { 598 nir_intrinsic_instr *load; 599 nir_intrinsic_op op; 600 unsigned srcn = 0; 601 602 switch (file) { 603 case TGSI_FILE_INPUT: 604 /* Special case: Turn the frontface varying into a load of the 605 * frontface intrinsic plus math, and appending the silly floats. 606 */ 607 if (c->scan->processor == PIPE_SHADER_FRAGMENT && 608 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_FACE) { 609 nir_ssa_def *tgsi_frontface[4] = { 610 nir_bcsel(&c->build, 611 nir_load_system_value(&c->build, 612 nir_intrinsic_load_front_face, 0), 613 nir_imm_float(&c->build, 1.0), 614 nir_imm_float(&c->build, -1.0)), 615 nir_imm_float(&c->build, 0.0), 616 nir_imm_float(&c->build, 0.0), 617 nir_imm_float(&c->build, 1.0), 618 }; 619 620 return nir_src_for_ssa(nir_vec(&c->build, tgsi_frontface, 4)); 621 } 622 623 op = nir_intrinsic_load_input; 624 assert(!dim); 625 break; 626 case TGSI_FILE_CONSTANT: 627 if (dim) { 628 op = nir_intrinsic_load_ubo; 629 } else { 630 op = nir_intrinsic_load_uniform; 631 } 632 break; 633 default: 634 unreachable("No other load files supported"); 635 break; 636 } 637 638 load = nir_intrinsic_instr_create(b->shader, op); 639 640 load->num_components = 4; 641 if (dim) { 642 if (dimind) { 643 load->src[srcn] = 644 ttn_src_for_file_and_index(c, dimind->File, dimind->Index, 645 NULL, NULL, NULL); 646 } else { 647 /* UBOs start at index 1 in TGSI: */ 648 load->src[srcn] = 649 nir_src_for_ssa(nir_imm_int(b, dim->Index - 1)); 650 } 651 srcn++; 652 } 653 654 nir_ssa_def *offset; 655 if (op == nir_intrinsic_load_ubo) { 656 /* UBO loads don't have a base offset. */ 657 offset = nir_imm_int(b, index); 658 if (indirect) { 659 offset = nir_iadd(b, offset, ttn_src_for_indirect(c, indirect)); 660 } 661 /* UBO offsets are in bytes, but TGSI gives them to us in vec4's */ 662 offset = nir_ishl(b, offset, nir_imm_int(b, 4)); 663 } else { 664 nir_intrinsic_set_base(load, index); 665 if (indirect) { 666 offset = ttn_src_for_indirect(c, indirect); 667 } else { 668 offset = nir_imm_int(b, 0); 669 } 670 } 671 load->src[srcn++] = nir_src_for_ssa(offset); 672 673 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL); 674 nir_builder_instr_insert(b, &load->instr); 675 676 src = nir_src_for_ssa(&load->dest.ssa); 677 break; 678 } 679 680 default: 681 unreachable("bad src file"); 682 } 683 684 685 return src; 686 } 687 688 static nir_ssa_def * 689 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect) 690 { 691 nir_builder *b = &c->build; 692 nir_alu_src src; 693 memset(&src, 0, sizeof(src)); 694 for (int i = 0; i < 4; i++) 695 src.swizzle[i] = indirect->Swizzle; 696 src.src = ttn_src_for_file_and_index(c, 697 indirect->File, 698 indirect->Index, 699 NULL, NULL, NULL); 700 return nir_imov_alu(b, src, 1); 701 } 702 703 static nir_alu_dest 704 ttn_get_dest(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst) 705 { 706 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register; 707 nir_alu_dest dest; 708 unsigned index = tgsi_dst->Index; 709 710 memset(&dest, 0, sizeof(dest)); 711 712 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) { 713 if (c->temp_regs[index].var) { 714 nir_register *reg; 715 716 /* this works, because TGSI will give us a base offset 717 * (in case of indirect index) that points back into 718 * the array. Access can be direct or indirect, we 719 * don't really care. Just create a one-shot dst reg 720 * that will get store_var'd back into the array var 721 * at the end of ttn_emit_instruction() 722 */ 723 reg = nir_local_reg_create(c->build.impl); 724 reg->num_components = 4; 725 dest.dest.reg.reg = reg; 726 dest.dest.reg.base_offset = 0; 727 } else { 728 assert(!tgsi_dst->Indirect); 729 dest.dest.reg.reg = c->temp_regs[index].reg; 730 dest.dest.reg.base_offset = c->temp_regs[index].offset; 731 } 732 } else if (tgsi_dst->File == TGSI_FILE_OUTPUT) { 733 dest.dest.reg.reg = c->output_regs[index].reg; 734 dest.dest.reg.base_offset = c->output_regs[index].offset; 735 } else if (tgsi_dst->File == TGSI_FILE_ADDRESS) { 736 assert(index == 0); 737 dest.dest.reg.reg = c->addr_reg; 738 } 739 740 dest.write_mask = tgsi_dst->WriteMask; 741 dest.saturate = false; 742 743 if (tgsi_dst->Indirect && (tgsi_dst->File != TGSI_FILE_TEMPORARY)) { 744 nir_src *indirect = ralloc(c->build.shader, nir_src); 745 *indirect = nir_src_for_ssa(ttn_src_for_indirect(c, &tgsi_fdst->Indirect)); 746 dest.dest.reg.indirect = indirect; 747 } 748 749 return dest; 750 } 751 752 static nir_variable * 753 ttn_get_var(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst) 754 { 755 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register; 756 unsigned index = tgsi_dst->Index; 757 758 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) { 759 /* we should not have an indirect when there is no var! */ 760 if (!c->temp_regs[index].var) 761 assert(!tgsi_dst->Indirect); 762 return c->temp_regs[index].var; 763 } 764 765 return NULL; 766 } 767 768 static nir_ssa_def * 769 ttn_get_src(struct ttn_compile *c, struct tgsi_full_src_register *tgsi_fsrc) 770 { 771 nir_builder *b = &c->build; 772 struct tgsi_src_register *tgsi_src = &tgsi_fsrc->Register; 773 unsigned tgsi_opcode = c->token->FullInstruction.Instruction.Opcode; 774 unsigned tgsi_src_type = tgsi_opcode_infer_src_type(tgsi_opcode); 775 bool src_is_float = !(tgsi_src_type == TGSI_TYPE_SIGNED || 776 tgsi_src_type == TGSI_TYPE_UNSIGNED); 777 nir_alu_src src; 778 779 memset(&src, 0, sizeof(src)); 780 781 if (tgsi_src->File == TGSI_FILE_NULL) { 782 return nir_imm_float(b, 0.0); 783 } else if (tgsi_src->File == TGSI_FILE_SAMPLER) { 784 /* Only the index of the sampler gets used in texturing, and it will 785 * handle looking that up on its own instead of using the nir_alu_src. 786 */ 787 assert(!tgsi_src->Indirect); 788 return NULL; 789 } else { 790 struct tgsi_ind_register *ind = NULL; 791 struct tgsi_dimension *dim = NULL; 792 struct tgsi_ind_register *dimind = NULL; 793 if (tgsi_src->Indirect) 794 ind = &tgsi_fsrc->Indirect; 795 if (tgsi_src->Dimension) { 796 dim = &tgsi_fsrc->Dimension; 797 if (dim->Indirect) 798 dimind = &tgsi_fsrc->DimIndirect; 799 } 800 src.src = ttn_src_for_file_and_index(c, 801 tgsi_src->File, 802 tgsi_src->Index, 803 ind, dim, dimind); 804 } 805 806 src.swizzle[0] = tgsi_src->SwizzleX; 807 src.swizzle[1] = tgsi_src->SwizzleY; 808 src.swizzle[2] = tgsi_src->SwizzleZ; 809 src.swizzle[3] = tgsi_src->SwizzleW; 810 811 nir_ssa_def *def = nir_fmov_alu(b, src, 4); 812 813 if (tgsi_src->Absolute) { 814 if (src_is_float) 815 def = nir_fabs(b, def); 816 else 817 def = nir_iabs(b, def); 818 } 819 820 if (tgsi_src->Negate) { 821 if (src_is_float) 822 def = nir_fneg(b, def); 823 else 824 def = nir_ineg(b, def); 825 } 826 827 return def; 828 } 829 830 static void 831 ttn_alu(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 832 { 833 unsigned num_srcs = nir_op_infos[op].num_inputs; 834 nir_alu_instr *instr = nir_alu_instr_create(b->shader, op); 835 unsigned i; 836 837 for (i = 0; i < num_srcs; i++) 838 instr->src[i].src = nir_src_for_ssa(src[i]); 839 840 instr->dest = dest; 841 nir_builder_instr_insert(b, &instr->instr); 842 } 843 844 static void 845 ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest, 846 nir_ssa_def *def, unsigned write_mask) 847 { 848 if (!(dest.write_mask & write_mask)) 849 return; 850 851 nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_imov); 852 mov->dest = dest; 853 mov->dest.write_mask &= write_mask; 854 mov->src[0].src = nir_src_for_ssa(def); 855 for (unsigned i = def->num_components; i < 4; i++) 856 mov->src[0].swizzle[i] = def->num_components - 1; 857 nir_builder_instr_insert(b, &mov->instr); 858 } 859 860 static void 861 ttn_move_dest(nir_builder *b, nir_alu_dest dest, nir_ssa_def *def) 862 { 863 ttn_move_dest_masked(b, dest, def, TGSI_WRITEMASK_XYZW); 864 } 865 866 static void 867 ttn_arl(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 868 { 869 ttn_move_dest(b, dest, nir_f2i(b, nir_ffloor(b, src[0]))); 870 } 871 872 /* EXP - Approximate Exponential Base 2 873 * dst.x = 2^{\lfloor src.x\rfloor} 874 * dst.y = src.x - \lfloor src.x\rfloor 875 * dst.z = 2^{src.x} 876 * dst.w = 1.0 877 */ 878 static void 879 ttn_exp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 880 { 881 nir_ssa_def *srcx = ttn_channel(b, src[0], X); 882 883 ttn_move_dest_masked(b, dest, nir_fexp2(b, nir_ffloor(b, srcx)), 884 TGSI_WRITEMASK_X); 885 ttn_move_dest_masked(b, dest, nir_fsub(b, srcx, nir_ffloor(b, srcx)), 886 TGSI_WRITEMASK_Y); 887 ttn_move_dest_masked(b, dest, nir_fexp2(b, srcx), TGSI_WRITEMASK_Z); 888 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W); 889 } 890 891 /* LOG - Approximate Logarithm Base 2 892 * dst.x = \lfloor\log_2{|src.x|}\rfloor 893 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}} 894 * dst.z = \log_2{|src.x|} 895 * dst.w = 1.0 896 */ 897 static void 898 ttn_log(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 899 { 900 nir_ssa_def *abs_srcx = nir_fabs(b, ttn_channel(b, src[0], X)); 901 nir_ssa_def *log2 = nir_flog2(b, abs_srcx); 902 903 ttn_move_dest_masked(b, dest, nir_ffloor(b, log2), TGSI_WRITEMASK_X); 904 ttn_move_dest_masked(b, dest, 905 nir_fdiv(b, abs_srcx, nir_fexp2(b, nir_ffloor(b, log2))), 906 TGSI_WRITEMASK_Y); 907 ttn_move_dest_masked(b, dest, nir_flog2(b, abs_srcx), TGSI_WRITEMASK_Z); 908 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W); 909 } 910 911 /* DST - Distance Vector 912 * dst.x = 1.0 913 * dst.y = src0.y \times src1.y 914 * dst.z = src0.z 915 * dst.w = src1.w 916 */ 917 static void 918 ttn_dst(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 919 { 920 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_X); 921 ttn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), TGSI_WRITEMASK_Y); 922 ttn_move_dest_masked(b, dest, nir_fmov(b, src[0]), TGSI_WRITEMASK_Z); 923 ttn_move_dest_masked(b, dest, nir_fmov(b, src[1]), TGSI_WRITEMASK_W); 924 } 925 926 /* LIT - Light Coefficients 927 * dst.x = 1.0 928 * dst.y = max(src.x, 0.0) 929 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0 930 * dst.w = 1.0 931 */ 932 static void 933 ttn_lit(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 934 { 935 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_XW); 936 937 ttn_move_dest_masked(b, dest, nir_fmax(b, ttn_channel(b, src[0], X), 938 nir_imm_float(b, 0.0)), TGSI_WRITEMASK_Y); 939 940 if (dest.write_mask & TGSI_WRITEMASK_Z) { 941 nir_ssa_def *src0_y = ttn_channel(b, src[0], Y); 942 nir_ssa_def *wclamp = nir_fmax(b, nir_fmin(b, ttn_channel(b, src[0], W), 943 nir_imm_float(b, 128.0)), 944 nir_imm_float(b, -128.0)); 945 nir_ssa_def *pow = nir_fpow(b, nir_fmax(b, src0_y, nir_imm_float(b, 0.0)), 946 wclamp); 947 948 ttn_move_dest_masked(b, dest, 949 nir_bcsel(b, 950 nir_fge(b, 951 nir_imm_float(b, 0.0), 952 ttn_channel(b, src[0], X)), 953 nir_imm_float(b, 0.0), 954 pow), 955 TGSI_WRITEMASK_Z); 956 } 957 } 958 959 /* SCS - Sine Cosine 960 * dst.x = \cos{src.x} 961 * dst.y = \sin{src.x} 962 * dst.z = 0.0 963 * dst.w = 1.0 964 */ 965 static void 966 ttn_scs(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 967 { 968 ttn_move_dest_masked(b, dest, nir_fcos(b, ttn_channel(b, src[0], X)), 969 TGSI_WRITEMASK_X); 970 ttn_move_dest_masked(b, dest, nir_fsin(b, ttn_channel(b, src[0], X)), 971 TGSI_WRITEMASK_Y); 972 ttn_move_dest_masked(b, dest, nir_imm_float(b, 0.0), TGSI_WRITEMASK_Z); 973 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W); 974 } 975 976 static void 977 ttn_sle(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 978 { 979 ttn_move_dest(b, dest, nir_sge(b, src[1], src[0])); 980 } 981 982 static void 983 ttn_sgt(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 984 { 985 ttn_move_dest(b, dest, nir_slt(b, src[1], src[0])); 986 } 987 988 static void 989 ttn_clamp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 990 { 991 ttn_move_dest(b, dest, nir_fmin(b, nir_fmax(b, src[0], src[1]), src[2])); 992 } 993 994 static void 995 ttn_xpd(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 996 { 997 ttn_move_dest_masked(b, dest, 998 nir_fsub(b, 999 nir_fmul(b, 1000 ttn_swizzle(b, src[0], Y, Z, X, X), 1001 ttn_swizzle(b, src[1], Z, X, Y, X)), 1002 nir_fmul(b, 1003 ttn_swizzle(b, src[1], Y, Z, X, X), 1004 ttn_swizzle(b, src[0], Z, X, Y, X))), 1005 TGSI_WRITEMASK_XYZ); 1006 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W); 1007 } 1008 1009 static void 1010 ttn_dp2a(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 1011 { 1012 ttn_move_dest(b, dest, 1013 ttn_channel(b, nir_fadd(b, nir_fdot2(b, src[0], src[1]), 1014 src[2]), 1015 X)); 1016 } 1017 1018 static void 1019 ttn_dp2(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 1020 { 1021 ttn_move_dest(b, dest, nir_fdot2(b, src[0], src[1])); 1022 } 1023 1024 static void 1025 ttn_dp3(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 1026 { 1027 ttn_move_dest(b, dest, nir_fdot3(b, src[0], src[1])); 1028 } 1029 1030 static void 1031 ttn_dp4(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 1032 { 1033 ttn_move_dest(b, dest, nir_fdot4(b, src[0], src[1])); 1034 } 1035 1036 static void 1037 ttn_dph(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 1038 { 1039 ttn_move_dest(b, dest, nir_fadd(b, nir_fdot3(b, src[0], src[1]), 1040 ttn_channel(b, src[1], W))); 1041 } 1042 1043 static void 1044 ttn_umad(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 1045 { 1046 ttn_move_dest(b, dest, nir_iadd(b, nir_imul(b, src[0], src[1]), src[2])); 1047 } 1048 1049 static void 1050 ttn_arr(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 1051 { 1052 ttn_move_dest(b, dest, nir_ffloor(b, nir_fadd(b, src[0], nir_imm_float(b, 0.5)))); 1053 } 1054 1055 static void 1056 ttn_cmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 1057 { 1058 ttn_move_dest(b, dest, nir_bcsel(b, 1059 nir_flt(b, src[0], nir_imm_float(b, 0.0)), 1060 src[1], src[2])); 1061 } 1062 1063 static void 1064 ttn_ucmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 1065 { 1066 ttn_move_dest(b, dest, nir_bcsel(b, 1067 nir_ine(b, src[0], nir_imm_int(b, 0)), 1068 src[1], src[2])); 1069 } 1070 1071 static void 1072 ttn_kill(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 1073 { 1074 nir_intrinsic_instr *discard = 1075 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard); 1076 nir_builder_instr_insert(b, &discard->instr); 1077 b->shader->info->fs.uses_discard = true; 1078 } 1079 1080 static void 1081 ttn_kill_if(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src) 1082 { 1083 nir_ssa_def *cmp = nir_bany_inequal4(b, nir_flt(b, src[0], 1084 nir_imm_float(b, 0.0)), 1085 nir_imm_int(b, 0)); 1086 nir_intrinsic_instr *discard = 1087 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard_if); 1088 discard->src[0] = nir_src_for_ssa(cmp); 1089 nir_builder_instr_insert(b, &discard->instr); 1090 b->shader->info->fs.uses_discard = true; 1091 } 1092 1093 static void 1094 ttn_if(struct ttn_compile *c, nir_ssa_def *src, bool is_uint) 1095 { 1096 nir_builder *b = &c->build; 1097 1098 src = ttn_channel(b, src, X); 1099 1100 nir_if *if_stmt = nir_if_create(b->shader); 1101 if (is_uint) { 1102 if_stmt->condition = nir_src_for_ssa(nir_ine(b, src, nir_imm_int(b, 0))); 1103 } else { 1104 if_stmt->condition = nir_src_for_ssa(nir_fne(b, src, nir_imm_int(b, 0))); 1105 } 1106 nir_builder_cf_insert(b, &if_stmt->cf_node); 1107 1108 c->if_stack[c->if_stack_pos] = nir_after_cf_node(&if_stmt->cf_node); 1109 c->if_stack_pos++; 1110 1111 b->cursor = nir_after_cf_list(&if_stmt->then_list); 1112 1113 c->if_stack[c->if_stack_pos] = nir_after_cf_list(&if_stmt->else_list); 1114 c->if_stack_pos++; 1115 } 1116 1117 static void 1118 ttn_else(struct ttn_compile *c) 1119 { 1120 nir_builder *b = &c->build; 1121 1122 b->cursor = c->if_stack[c->if_stack_pos - 1]; 1123 } 1124 1125 static void 1126 ttn_endif(struct ttn_compile *c) 1127 { 1128 nir_builder *b = &c->build; 1129 1130 c->if_stack_pos -= 2; 1131 b->cursor = c->if_stack[c->if_stack_pos]; 1132 } 1133 1134 static void 1135 ttn_bgnloop(struct ttn_compile *c) 1136 { 1137 nir_builder *b = &c->build; 1138 1139 nir_loop *loop = nir_loop_create(b->shader); 1140 nir_builder_cf_insert(b, &loop->cf_node); 1141 1142 c->loop_stack[c->loop_stack_pos] = nir_after_cf_node(&loop->cf_node); 1143 c->loop_stack_pos++; 1144 1145 b->cursor = nir_after_cf_list(&loop->body); 1146 } 1147 1148 static void 1149 ttn_cont(nir_builder *b) 1150 { 1151 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_continue); 1152 nir_builder_instr_insert(b, &instr->instr); 1153 } 1154 1155 static void 1156 ttn_brk(nir_builder *b) 1157 { 1158 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break); 1159 nir_builder_instr_insert(b, &instr->instr); 1160 } 1161 1162 static void 1163 ttn_endloop(struct ttn_compile *c) 1164 { 1165 nir_builder *b = &c->build; 1166 1167 c->loop_stack_pos--; 1168 b->cursor = c->loop_stack[c->loop_stack_pos]; 1169 } 1170 1171 static void 1172 setup_texture_info(nir_tex_instr *instr, unsigned texture) 1173 { 1174 switch (texture) { 1175 case TGSI_TEXTURE_BUFFER: 1176 instr->sampler_dim = GLSL_SAMPLER_DIM_BUF; 1177 break; 1178 case TGSI_TEXTURE_1D: 1179 instr->sampler_dim = GLSL_SAMPLER_DIM_1D; 1180 break; 1181 case TGSI_TEXTURE_1D_ARRAY: 1182 instr->sampler_dim = GLSL_SAMPLER_DIM_1D; 1183 instr->is_array = true; 1184 break; 1185 case TGSI_TEXTURE_SHADOW1D: 1186 instr->sampler_dim = GLSL_SAMPLER_DIM_1D; 1187 instr->is_shadow = true; 1188 break; 1189 case TGSI_TEXTURE_SHADOW1D_ARRAY: 1190 instr->sampler_dim = GLSL_SAMPLER_DIM_1D; 1191 instr->is_shadow = true; 1192 instr->is_array = true; 1193 break; 1194 case TGSI_TEXTURE_2D: 1195 instr->sampler_dim = GLSL_SAMPLER_DIM_2D; 1196 break; 1197 case TGSI_TEXTURE_2D_ARRAY: 1198 instr->sampler_dim = GLSL_SAMPLER_DIM_2D; 1199 instr->is_array = true; 1200 break; 1201 case TGSI_TEXTURE_2D_MSAA: 1202 instr->sampler_dim = GLSL_SAMPLER_DIM_MS; 1203 break; 1204 case TGSI_TEXTURE_2D_ARRAY_MSAA: 1205 instr->sampler_dim = GLSL_SAMPLER_DIM_MS; 1206 instr->is_array = true; 1207 break; 1208 case TGSI_TEXTURE_SHADOW2D: 1209 instr->sampler_dim = GLSL_SAMPLER_DIM_2D; 1210 instr->is_shadow = true; 1211 break; 1212 case TGSI_TEXTURE_SHADOW2D_ARRAY: 1213 instr->sampler_dim = GLSL_SAMPLER_DIM_2D; 1214 instr->is_shadow = true; 1215 instr->is_array = true; 1216 break; 1217 case TGSI_TEXTURE_3D: 1218 instr->sampler_dim = GLSL_SAMPLER_DIM_3D; 1219 break; 1220 case TGSI_TEXTURE_CUBE: 1221 instr->sampler_dim = GLSL_SAMPLER_DIM_CUBE; 1222 break; 1223 case TGSI_TEXTURE_CUBE_ARRAY: 1224 instr->sampler_dim = GLSL_SAMPLER_DIM_CUBE; 1225 instr->is_array = true; 1226 break; 1227 case TGSI_TEXTURE_SHADOWCUBE: 1228 instr->sampler_dim = GLSL_SAMPLER_DIM_CUBE; 1229 instr->is_shadow = true; 1230 break; 1231 case TGSI_TEXTURE_SHADOWCUBE_ARRAY: 1232 instr->sampler_dim = GLSL_SAMPLER_DIM_CUBE; 1233 instr->is_shadow = true; 1234 instr->is_array = true; 1235 break; 1236 case TGSI_TEXTURE_RECT: 1237 instr->sampler_dim = GLSL_SAMPLER_DIM_RECT; 1238 break; 1239 case TGSI_TEXTURE_SHADOWRECT: 1240 instr->sampler_dim = GLSL_SAMPLER_DIM_RECT; 1241 instr->is_shadow = true; 1242 break; 1243 default: 1244 fprintf(stderr, "Unknown TGSI texture target %d\n", texture); 1245 abort(); 1246 } 1247 } 1248 1249 static void 1250 ttn_tex(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src) 1251 { 1252 nir_builder *b = &c->build; 1253 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction; 1254 nir_tex_instr *instr; 1255 nir_texop op; 1256 unsigned num_srcs, samp = 1, sview, i; 1257 1258 switch (tgsi_inst->Instruction.Opcode) { 1259 case TGSI_OPCODE_TEX: 1260 op = nir_texop_tex; 1261 num_srcs = 1; 1262 break; 1263 case TGSI_OPCODE_TEX2: 1264 op = nir_texop_tex; 1265 num_srcs = 1; 1266 samp = 2; 1267 break; 1268 case TGSI_OPCODE_TXP: 1269 op = nir_texop_tex; 1270 num_srcs = 2; 1271 break; 1272 case TGSI_OPCODE_TXB: 1273 op = nir_texop_txb; 1274 num_srcs = 2; 1275 break; 1276 case TGSI_OPCODE_TXB2: 1277 op = nir_texop_txb; 1278 num_srcs = 2; 1279 samp = 2; 1280 break; 1281 case TGSI_OPCODE_TXL: 1282 op = nir_texop_txl; 1283 num_srcs = 2; 1284 break; 1285 case TGSI_OPCODE_TXL2: 1286 op = nir_texop_txl; 1287 num_srcs = 2; 1288 samp = 2; 1289 break; 1290 case TGSI_OPCODE_TXF: 1291 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA || 1292 tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA) { 1293 op = nir_texop_txf_ms; 1294 } else { 1295 op = nir_texop_txf; 1296 } 1297 num_srcs = 2; 1298 break; 1299 case TGSI_OPCODE_TXD: 1300 op = nir_texop_txd; 1301 num_srcs = 3; 1302 samp = 3; 1303 break; 1304 case TGSI_OPCODE_LODQ: 1305 op = nir_texop_lod; 1306 num_srcs = 1; 1307 break; 1308 1309 default: 1310 fprintf(stderr, "unknown TGSI tex op %d\n", tgsi_inst->Instruction.Opcode); 1311 abort(); 1312 } 1313 1314 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || 1315 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY || 1316 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D || 1317 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY || 1318 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT || 1319 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE || 1320 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) { 1321 num_srcs++; 1322 } 1323 1324 num_srcs += tgsi_inst->Texture.NumOffsets; 1325 1326 instr = nir_tex_instr_create(b->shader, num_srcs); 1327 instr->op = op; 1328 1329 setup_texture_info(instr, tgsi_inst->Texture.Texture); 1330 1331 switch (instr->sampler_dim) { 1332 case GLSL_SAMPLER_DIM_1D: 1333 case GLSL_SAMPLER_DIM_BUF: 1334 instr->coord_components = 1; 1335 break; 1336 case GLSL_SAMPLER_DIM_2D: 1337 case GLSL_SAMPLER_DIM_RECT: 1338 case GLSL_SAMPLER_DIM_EXTERNAL: 1339 case GLSL_SAMPLER_DIM_MS: 1340 instr->coord_components = 2; 1341 break; 1342 case GLSL_SAMPLER_DIM_3D: 1343 case GLSL_SAMPLER_DIM_CUBE: 1344 instr->coord_components = 3; 1345 break; 1346 case GLSL_SAMPLER_DIM_SUBPASS: 1347 case GLSL_SAMPLER_DIM_SUBPASS_MS: 1348 unreachable("invalid sampler_dim"); 1349 } 1350 1351 if (instr->is_array) 1352 instr->coord_components++; 1353 1354 assert(tgsi_inst->Src[samp].Register.File == TGSI_FILE_SAMPLER); 1355 instr->texture_index = tgsi_inst->Src[samp].Register.Index; 1356 instr->sampler_index = tgsi_inst->Src[samp].Register.Index; 1357 1358 /* TODO if we supported any opc's which take an explicit SVIEW 1359 * src, we would use that here instead. But for the "legacy" 1360 * texture opc's the SVIEW index is same as SAMP index: 1361 */ 1362 sview = instr->texture_index; 1363 1364 if (op == nir_texop_lod) { 1365 instr->dest_type = nir_type_float; 1366 } else if (sview < c->num_samp_types) { 1367 instr->dest_type = c->samp_types[sview]; 1368 } else { 1369 instr->dest_type = nir_type_float; 1370 } 1371 1372 unsigned src_number = 0; 1373 1374 instr->src[src_number].src = 1375 nir_src_for_ssa(nir_swizzle(b, src[0], SWIZ(X, Y, Z, W), 1376 instr->coord_components, false)); 1377 instr->src[src_number].src_type = nir_tex_src_coord; 1378 src_number++; 1379 1380 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) { 1381 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W)); 1382 instr->src[src_number].src_type = nir_tex_src_projector; 1383 src_number++; 1384 } 1385 1386 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) { 1387 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W)); 1388 instr->src[src_number].src_type = nir_tex_src_bias; 1389 src_number++; 1390 } 1391 1392 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB2) { 1393 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X)); 1394 instr->src[src_number].src_type = nir_tex_src_bias; 1395 src_number++; 1396 } 1397 1398 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL) { 1399 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W)); 1400 instr->src[src_number].src_type = nir_tex_src_lod; 1401 src_number++; 1402 } 1403 1404 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL2) { 1405 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X)); 1406 instr->src[src_number].src_type = nir_tex_src_lod; 1407 src_number++; 1408 } 1409 1410 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF) { 1411 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W)); 1412 if (op == nir_texop_txf_ms) 1413 instr->src[src_number].src_type = nir_tex_src_ms_index; 1414 else 1415 instr->src[src_number].src_type = nir_tex_src_lod; 1416 src_number++; 1417 } 1418 1419 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXD) { 1420 instr->src[src_number].src = 1421 nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W), 1422 instr->coord_components, false)); 1423 instr->src[src_number].src_type = nir_tex_src_ddx; 1424 src_number++; 1425 instr->src[src_number].src = 1426 nir_src_for_ssa(nir_swizzle(b, src[2], SWIZ(X, Y, Z, W), 1427 instr->coord_components, false)); 1428 instr->src[src_number].src_type = nir_tex_src_ddy; 1429 src_number++; 1430 } 1431 1432 if (instr->is_shadow) { 1433 if (instr->coord_components == 4) 1434 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X)); 1435 else if (instr->coord_components == 3) 1436 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W)); 1437 else 1438 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], Z)); 1439 1440 instr->src[src_number].src_type = nir_tex_src_comparator; 1441 src_number++; 1442 } 1443 1444 for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++) { 1445 struct tgsi_texture_offset *tex_offset = &tgsi_inst->TexOffsets[i]; 1446 /* since TexOffset ins't using tgsi_full_src_register we get to 1447 * do some extra gymnastics: 1448 */ 1449 nir_alu_src src; 1450 1451 memset(&src, 0, sizeof(src)); 1452 1453 src.src = ttn_src_for_file_and_index(c, 1454 tex_offset->File, 1455 tex_offset->Index, 1456 NULL, NULL, NULL); 1457 1458 src.swizzle[0] = tex_offset->SwizzleX; 1459 src.swizzle[1] = tex_offset->SwizzleY; 1460 src.swizzle[2] = tex_offset->SwizzleZ; 1461 src.swizzle[3] = TGSI_SWIZZLE_W; 1462 1463 instr->src[src_number].src_type = nir_tex_src_offset; 1464 instr->src[src_number].src = nir_src_for_ssa( 1465 nir_fmov_alu(b, src, nir_tex_instr_src_size(instr, src_number))); 1466 src_number++; 1467 } 1468 1469 assert(src_number == num_srcs); 1470 1471 nir_ssa_dest_init(&instr->instr, &instr->dest, 4, 32, NULL); 1472 nir_builder_instr_insert(b, &instr->instr); 1473 1474 /* Resolve the writemask on the texture op. */ 1475 ttn_move_dest(b, dest, &instr->dest.ssa); 1476 } 1477 1478 /* TGSI_OPCODE_TXQ is actually two distinct operations: 1479 * 1480 * dst.x = texture\_width(unit, lod) 1481 * dst.y = texture\_height(unit, lod) 1482 * dst.z = texture\_depth(unit, lod) 1483 * dst.w = texture\_levels(unit) 1484 * 1485 * dst.xyz map to NIR txs opcode, and dst.w maps to query_levels 1486 */ 1487 static void 1488 ttn_txq(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src) 1489 { 1490 nir_builder *b = &c->build; 1491 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction; 1492 nir_tex_instr *txs, *qlv; 1493 1494 txs = nir_tex_instr_create(b->shader, 1); 1495 txs->op = nir_texop_txs; 1496 setup_texture_info(txs, tgsi_inst->Texture.Texture); 1497 1498 qlv = nir_tex_instr_create(b->shader, 0); 1499 qlv->op = nir_texop_query_levels; 1500 setup_texture_info(qlv, tgsi_inst->Texture.Texture); 1501 1502 assert(tgsi_inst->Src[1].Register.File == TGSI_FILE_SAMPLER); 1503 txs->texture_index = tgsi_inst->Src[1].Register.Index; 1504 qlv->texture_index = tgsi_inst->Src[1].Register.Index; 1505 1506 /* only single src, the lod: */ 1507 txs->src[0].src = nir_src_for_ssa(ttn_channel(b, src[0], X)); 1508 txs->src[0].src_type = nir_tex_src_lod; 1509 1510 nir_ssa_dest_init(&txs->instr, &txs->dest, 3, 32, NULL); 1511 nir_builder_instr_insert(b, &txs->instr); 1512 1513 nir_ssa_dest_init(&qlv->instr, &qlv->dest, 1, 32, NULL); 1514 nir_builder_instr_insert(b, &qlv->instr); 1515 1516 ttn_move_dest_masked(b, dest, &txs->dest.ssa, TGSI_WRITEMASK_XYZ); 1517 ttn_move_dest_masked(b, dest, &qlv->dest.ssa, TGSI_WRITEMASK_W); 1518 } 1519 1520 static const nir_op op_trans[TGSI_OPCODE_LAST] = { 1521 [TGSI_OPCODE_ARL] = 0, 1522 [TGSI_OPCODE_MOV] = nir_op_fmov, 1523 [TGSI_OPCODE_LIT] = 0, 1524 [TGSI_OPCODE_RCP] = nir_op_frcp, 1525 [TGSI_OPCODE_RSQ] = nir_op_frsq, 1526 [TGSI_OPCODE_EXP] = 0, 1527 [TGSI_OPCODE_LOG] = 0, 1528 [TGSI_OPCODE_MUL] = nir_op_fmul, 1529 [TGSI_OPCODE_ADD] = nir_op_fadd, 1530 [TGSI_OPCODE_DP3] = 0, 1531 [TGSI_OPCODE_DP4] = 0, 1532 [TGSI_OPCODE_DST] = 0, 1533 [TGSI_OPCODE_MIN] = nir_op_fmin, 1534 [TGSI_OPCODE_MAX] = nir_op_fmax, 1535 [TGSI_OPCODE_SLT] = nir_op_slt, 1536 [TGSI_OPCODE_SGE] = nir_op_sge, 1537 [TGSI_OPCODE_MAD] = nir_op_ffma, 1538 [TGSI_OPCODE_LRP] = 0, 1539 [TGSI_OPCODE_SQRT] = nir_op_fsqrt, 1540 [TGSI_OPCODE_DP2A] = 0, 1541 [TGSI_OPCODE_FRC] = nir_op_ffract, 1542 [TGSI_OPCODE_CLAMP] = 0, 1543 [TGSI_OPCODE_FLR] = nir_op_ffloor, 1544 [TGSI_OPCODE_ROUND] = nir_op_fround_even, 1545 [TGSI_OPCODE_EX2] = nir_op_fexp2, 1546 [TGSI_OPCODE_LG2] = nir_op_flog2, 1547 [TGSI_OPCODE_POW] = nir_op_fpow, 1548 [TGSI_OPCODE_XPD] = 0, 1549 [TGSI_OPCODE_DPH] = 0, 1550 [TGSI_OPCODE_COS] = nir_op_fcos, 1551 [TGSI_OPCODE_DDX] = nir_op_fddx, 1552 [TGSI_OPCODE_DDY] = nir_op_fddy, 1553 [TGSI_OPCODE_KILL] = 0, 1554 [TGSI_OPCODE_PK2H] = 0, /* XXX */ 1555 [TGSI_OPCODE_PK2US] = 0, /* XXX */ 1556 [TGSI_OPCODE_PK4B] = 0, /* XXX */ 1557 [TGSI_OPCODE_PK4UB] = 0, /* XXX */ 1558 [TGSI_OPCODE_SEQ] = nir_op_seq, 1559 [TGSI_OPCODE_SGT] = 0, 1560 [TGSI_OPCODE_SIN] = nir_op_fsin, 1561 [TGSI_OPCODE_SNE] = nir_op_sne, 1562 [TGSI_OPCODE_SLE] = 0, 1563 [TGSI_OPCODE_TEX] = 0, 1564 [TGSI_OPCODE_TXD] = 0, 1565 [TGSI_OPCODE_TXP] = 0, 1566 [TGSI_OPCODE_UP2H] = 0, /* XXX */ 1567 [TGSI_OPCODE_UP2US] = 0, /* XXX */ 1568 [TGSI_OPCODE_UP4B] = 0, /* XXX */ 1569 [TGSI_OPCODE_UP4UB] = 0, /* XXX */ 1570 [TGSI_OPCODE_ARR] = 0, 1571 1572 /* No function calls, yet. */ 1573 [TGSI_OPCODE_CAL] = 0, /* XXX */ 1574 [TGSI_OPCODE_RET] = 0, /* XXX */ 1575 1576 [TGSI_OPCODE_SSG] = nir_op_fsign, 1577 [TGSI_OPCODE_CMP] = 0, 1578 [TGSI_OPCODE_SCS] = 0, 1579 [TGSI_OPCODE_TXB] = 0, 1580 [TGSI_OPCODE_DIV] = nir_op_fdiv, 1581 [TGSI_OPCODE_DP2] = 0, 1582 [TGSI_OPCODE_TXL] = 0, 1583 1584 [TGSI_OPCODE_BRK] = 0, 1585 [TGSI_OPCODE_IF] = 0, 1586 [TGSI_OPCODE_UIF] = 0, 1587 [TGSI_OPCODE_ELSE] = 0, 1588 [TGSI_OPCODE_ENDIF] = 0, 1589 1590 [TGSI_OPCODE_DDX_FINE] = nir_op_fddx_fine, 1591 [TGSI_OPCODE_DDY_FINE] = nir_op_fddy_fine, 1592 1593 [TGSI_OPCODE_PUSHA] = 0, /* XXX */ 1594 [TGSI_OPCODE_POPA] = 0, /* XXX */ 1595 1596 [TGSI_OPCODE_CEIL] = nir_op_fceil, 1597 [TGSI_OPCODE_I2F] = nir_op_i2f, 1598 [TGSI_OPCODE_NOT] = nir_op_inot, 1599 [TGSI_OPCODE_TRUNC] = nir_op_ftrunc, 1600 [TGSI_OPCODE_SHL] = nir_op_ishl, 1601 [TGSI_OPCODE_AND] = nir_op_iand, 1602 [TGSI_OPCODE_OR] = nir_op_ior, 1603 [TGSI_OPCODE_MOD] = nir_op_umod, 1604 [TGSI_OPCODE_XOR] = nir_op_ixor, 1605 [TGSI_OPCODE_SAD] = 0, /* XXX */ 1606 [TGSI_OPCODE_TXF] = 0, 1607 [TGSI_OPCODE_TXQ] = 0, 1608 1609 [TGSI_OPCODE_CONT] = 0, 1610 1611 [TGSI_OPCODE_EMIT] = 0, /* XXX */ 1612 [TGSI_OPCODE_ENDPRIM] = 0, /* XXX */ 1613 1614 [TGSI_OPCODE_BGNLOOP] = 0, 1615 [TGSI_OPCODE_BGNSUB] = 0, /* XXX: no function calls */ 1616 [TGSI_OPCODE_ENDLOOP] = 0, 1617 [TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */ 1618 1619 [TGSI_OPCODE_TXQ_LZ] = 0, 1620 [TGSI_OPCODE_NOP] = 0, 1621 [TGSI_OPCODE_FSEQ] = nir_op_feq, 1622 [TGSI_OPCODE_FSGE] = nir_op_fge, 1623 [TGSI_OPCODE_FSLT] = nir_op_flt, 1624 [TGSI_OPCODE_FSNE] = nir_op_fne, 1625 1626 /* No control flow yet */ 1627 [TGSI_OPCODE_CALLNZ] = 0, /* XXX */ 1628 [TGSI_OPCODE_BREAKC] = 0, /* not emitted by glsl_to_tgsi.cpp */ 1629 1630 [TGSI_OPCODE_KILL_IF] = 0, 1631 1632 [TGSI_OPCODE_END] = 0, 1633 1634 [TGSI_OPCODE_F2I] = nir_op_f2i, 1635 [TGSI_OPCODE_IDIV] = nir_op_idiv, 1636 [TGSI_OPCODE_IMAX] = nir_op_imax, 1637 [TGSI_OPCODE_IMIN] = nir_op_imin, 1638 [TGSI_OPCODE_INEG] = nir_op_ineg, 1639 [TGSI_OPCODE_ISGE] = nir_op_ige, 1640 [TGSI_OPCODE_ISHR] = nir_op_ishr, 1641 [TGSI_OPCODE_ISLT] = nir_op_ilt, 1642 [TGSI_OPCODE_F2U] = nir_op_f2u, 1643 [TGSI_OPCODE_U2F] = nir_op_u2f, 1644 [TGSI_OPCODE_UADD] = nir_op_iadd, 1645 [TGSI_OPCODE_UDIV] = nir_op_udiv, 1646 [TGSI_OPCODE_UMAD] = 0, 1647 [TGSI_OPCODE_UMAX] = nir_op_umax, 1648 [TGSI_OPCODE_UMIN] = nir_op_umin, 1649 [TGSI_OPCODE_UMOD] = nir_op_umod, 1650 [TGSI_OPCODE_UMUL] = nir_op_imul, 1651 [TGSI_OPCODE_USEQ] = nir_op_ieq, 1652 [TGSI_OPCODE_USGE] = nir_op_uge, 1653 [TGSI_OPCODE_USHR] = nir_op_ushr, 1654 [TGSI_OPCODE_USLT] = nir_op_ult, 1655 [TGSI_OPCODE_USNE] = nir_op_ine, 1656 1657 [TGSI_OPCODE_SWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */ 1658 [TGSI_OPCODE_CASE] = 0, /* not emitted by glsl_to_tgsi.cpp */ 1659 [TGSI_OPCODE_DEFAULT] = 0, /* not emitted by glsl_to_tgsi.cpp */ 1660 [TGSI_OPCODE_ENDSWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */ 1661 1662 /* XXX: SAMPLE opcodes */ 1663 1664 [TGSI_OPCODE_UARL] = nir_op_imov, 1665 [TGSI_OPCODE_UCMP] = 0, 1666 [TGSI_OPCODE_IABS] = nir_op_iabs, 1667 [TGSI_OPCODE_ISSG] = nir_op_isign, 1668 1669 /* XXX: atomics */ 1670 1671 [TGSI_OPCODE_TEX2] = 0, 1672 [TGSI_OPCODE_TXB2] = 0, 1673 [TGSI_OPCODE_TXL2] = 0, 1674 1675 [TGSI_OPCODE_IMUL_HI] = nir_op_imul_high, 1676 [TGSI_OPCODE_UMUL_HI] = nir_op_umul_high, 1677 1678 [TGSI_OPCODE_TG4] = 0, 1679 [TGSI_OPCODE_LODQ] = 0, 1680 1681 [TGSI_OPCODE_IBFE] = nir_op_ibitfield_extract, 1682 [TGSI_OPCODE_UBFE] = nir_op_ubitfield_extract, 1683 [TGSI_OPCODE_BFI] = nir_op_bitfield_insert, 1684 [TGSI_OPCODE_BREV] = nir_op_bitfield_reverse, 1685 [TGSI_OPCODE_POPC] = nir_op_bit_count, 1686 [TGSI_OPCODE_LSB] = nir_op_find_lsb, 1687 [TGSI_OPCODE_IMSB] = nir_op_ifind_msb, 1688 [TGSI_OPCODE_UMSB] = nir_op_ufind_msb, 1689 1690 [TGSI_OPCODE_INTERP_CENTROID] = 0, /* XXX */ 1691 [TGSI_OPCODE_INTERP_SAMPLE] = 0, /* XXX */ 1692 [TGSI_OPCODE_INTERP_OFFSET] = 0, /* XXX */ 1693 }; 1694 1695 static void 1696 ttn_emit_instruction(struct ttn_compile *c) 1697 { 1698 nir_builder *b = &c->build; 1699 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction; 1700 unsigned i; 1701 unsigned tgsi_op = tgsi_inst->Instruction.Opcode; 1702 struct tgsi_full_dst_register *tgsi_dst = &tgsi_inst->Dst[0]; 1703 1704 if (tgsi_op == TGSI_OPCODE_END) 1705 return; 1706 1707 nir_ssa_def *src[TGSI_FULL_MAX_SRC_REGISTERS]; 1708 for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++) { 1709 src[i] = ttn_get_src(c, &tgsi_inst->Src[i]); 1710 } 1711 nir_alu_dest dest = ttn_get_dest(c, tgsi_dst); 1712 1713 switch (tgsi_op) { 1714 case TGSI_OPCODE_RSQ: 1715 ttn_move_dest(b, dest, nir_frsq(b, ttn_channel(b, src[0], X))); 1716 break; 1717 1718 case TGSI_OPCODE_SQRT: 1719 ttn_move_dest(b, dest, nir_fsqrt(b, ttn_channel(b, src[0], X))); 1720 break; 1721 1722 case TGSI_OPCODE_RCP: 1723 ttn_move_dest(b, dest, nir_frcp(b, ttn_channel(b, src[0], X))); 1724 break; 1725 1726 case TGSI_OPCODE_EX2: 1727 ttn_move_dest(b, dest, nir_fexp2(b, ttn_channel(b, src[0], X))); 1728 break; 1729 1730 case TGSI_OPCODE_LG2: 1731 ttn_move_dest(b, dest, nir_flog2(b, ttn_channel(b, src[0], X))); 1732 break; 1733 1734 case TGSI_OPCODE_POW: 1735 ttn_move_dest(b, dest, nir_fpow(b, 1736 ttn_channel(b, src[0], X), 1737 ttn_channel(b, src[1], X))); 1738 break; 1739 1740 case TGSI_OPCODE_COS: 1741 ttn_move_dest(b, dest, nir_fcos(b, ttn_channel(b, src[0], X))); 1742 break; 1743 1744 case TGSI_OPCODE_SIN: 1745 ttn_move_dest(b, dest, nir_fsin(b, ttn_channel(b, src[0], X))); 1746 break; 1747 1748 case TGSI_OPCODE_ARL: 1749 ttn_arl(b, op_trans[tgsi_op], dest, src); 1750 break; 1751 1752 case TGSI_OPCODE_EXP: 1753 ttn_exp(b, op_trans[tgsi_op], dest, src); 1754 break; 1755 1756 case TGSI_OPCODE_LOG: 1757 ttn_log(b, op_trans[tgsi_op], dest, src); 1758 break; 1759 1760 case TGSI_OPCODE_DST: 1761 ttn_dst(b, op_trans[tgsi_op], dest, src); 1762 break; 1763 1764 case TGSI_OPCODE_LIT: 1765 ttn_lit(b, op_trans[tgsi_op], dest, src); 1766 break; 1767 1768 case TGSI_OPCODE_CLAMP: 1769 ttn_clamp(b, op_trans[tgsi_op], dest, src); 1770 break; 1771 1772 case TGSI_OPCODE_XPD: 1773 ttn_xpd(b, op_trans[tgsi_op], dest, src); 1774 break; 1775 1776 case TGSI_OPCODE_DP2: 1777 ttn_dp2(b, op_trans[tgsi_op], dest, src); 1778 break; 1779 1780 case TGSI_OPCODE_DP3: 1781 ttn_dp3(b, op_trans[tgsi_op], dest, src); 1782 break; 1783 1784 case TGSI_OPCODE_DP4: 1785 ttn_dp4(b, op_trans[tgsi_op], dest, src); 1786 break; 1787 1788 case TGSI_OPCODE_DP2A: 1789 ttn_dp2a(b, op_trans[tgsi_op], dest, src); 1790 break; 1791 1792 case TGSI_OPCODE_DPH: 1793 ttn_dph(b, op_trans[tgsi_op], dest, src); 1794 break; 1795 1796 case TGSI_OPCODE_UMAD: 1797 ttn_umad(b, op_trans[tgsi_op], dest, src); 1798 break; 1799 1800 case TGSI_OPCODE_LRP: 1801 ttn_move_dest(b, dest, nir_flrp(b, src[2], src[1], src[0])); 1802 break; 1803 1804 case TGSI_OPCODE_KILL: 1805 ttn_kill(b, op_trans[tgsi_op], dest, src); 1806 break; 1807 1808 case TGSI_OPCODE_ARR: 1809 ttn_arr(b, op_trans[tgsi_op], dest, src); 1810 break; 1811 1812 case TGSI_OPCODE_CMP: 1813 ttn_cmp(b, op_trans[tgsi_op], dest, src); 1814 break; 1815 1816 case TGSI_OPCODE_UCMP: 1817 ttn_ucmp(b, op_trans[tgsi_op], dest, src); 1818 break; 1819 1820 case TGSI_OPCODE_SCS: 1821 ttn_scs(b, op_trans[tgsi_op], dest, src); 1822 break; 1823 1824 case TGSI_OPCODE_SGT: 1825 ttn_sgt(b, op_trans[tgsi_op], dest, src); 1826 break; 1827 1828 case TGSI_OPCODE_SLE: 1829 ttn_sle(b, op_trans[tgsi_op], dest, src); 1830 break; 1831 1832 case TGSI_OPCODE_KILL_IF: 1833 ttn_kill_if(b, op_trans[tgsi_op], dest, src); 1834 break; 1835 1836 case TGSI_OPCODE_TEX: 1837 case TGSI_OPCODE_TXP: 1838 case TGSI_OPCODE_TXL: 1839 case TGSI_OPCODE_TXB: 1840 case TGSI_OPCODE_TXD: 1841 case TGSI_OPCODE_TEX2: 1842 case TGSI_OPCODE_TXL2: 1843 case TGSI_OPCODE_TXB2: 1844 case TGSI_OPCODE_TXQ_LZ: 1845 case TGSI_OPCODE_TXF: 1846 case TGSI_OPCODE_TG4: 1847 case TGSI_OPCODE_LODQ: 1848 ttn_tex(c, dest, src); 1849 break; 1850 1851 case TGSI_OPCODE_TXQ: 1852 ttn_txq(c, dest, src); 1853 break; 1854 1855 case TGSI_OPCODE_NOP: 1856 break; 1857 1858 case TGSI_OPCODE_IF: 1859 ttn_if(c, src[0], false); 1860 break; 1861 1862 case TGSI_OPCODE_UIF: 1863 ttn_if(c, src[0], true); 1864 break; 1865 1866 case TGSI_OPCODE_ELSE: 1867 ttn_else(c); 1868 break; 1869 1870 case TGSI_OPCODE_ENDIF: 1871 ttn_endif(c); 1872 break; 1873 1874 case TGSI_OPCODE_BGNLOOP: 1875 ttn_bgnloop(c); 1876 break; 1877 1878 case TGSI_OPCODE_BRK: 1879 ttn_brk(b); 1880 break; 1881 1882 case TGSI_OPCODE_CONT: 1883 ttn_cont(b); 1884 break; 1885 1886 case TGSI_OPCODE_ENDLOOP: 1887 ttn_endloop(c); 1888 break; 1889 1890 default: 1891 if (op_trans[tgsi_op] != 0 || tgsi_op == TGSI_OPCODE_MOV) { 1892 ttn_alu(b, op_trans[tgsi_op], dest, src); 1893 } else { 1894 fprintf(stderr, "unknown TGSI opcode: %s\n", 1895 tgsi_get_opcode_name(tgsi_op)); 1896 abort(); 1897 } 1898 break; 1899 } 1900 1901 if (tgsi_inst->Instruction.Saturate) { 1902 assert(!dest.dest.is_ssa); 1903 ttn_move_dest(b, dest, nir_fsat(b, ttn_src_for_dest(b, &dest))); 1904 } 1905 1906 /* if the dst has a matching var, append store_var to move 1907 * output from reg to var 1908 */ 1909 nir_variable *var = ttn_get_var(c, tgsi_dst); 1910 if (var) { 1911 unsigned index = tgsi_dst->Register.Index; 1912 unsigned offset = c->temp_regs[index].offset; 1913 nir_intrinsic_instr *store = 1914 nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_var); 1915 struct tgsi_ind_register *indirect = tgsi_dst->Register.Indirect ? 1916 &tgsi_dst->Indirect : NULL; 1917 1918 store->num_components = 4; 1919 nir_intrinsic_set_write_mask(store, dest.write_mask); 1920 store->variables[0] = ttn_array_deref(c, store, var, offset, indirect); 1921 store->src[0] = nir_src_for_reg(dest.dest.reg.reg); 1922 1923 nir_builder_instr_insert(b, &store->instr); 1924 } 1925 } 1926 1927 /** 1928 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output 1929 * variables at the end of the shader. 1930 * 1931 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are 1932 * written, because there's no output load intrinsic, which means we couldn't 1933 * handle writemasks. 1934 */ 1935 static void 1936 ttn_add_output_stores(struct ttn_compile *c) 1937 { 1938 nir_builder *b = &c->build; 1939 1940 foreach_list_typed(nir_variable, var, node, &b->shader->outputs) { 1941 unsigned array_len = MAX2(glsl_get_length(var->type), 1); 1942 unsigned i; 1943 1944 for (i = 0; i < array_len; i++) { 1945 nir_intrinsic_instr *store = 1946 nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_output); 1947 unsigned loc = var->data.driver_location + i; 1948 1949 nir_src src = nir_src_for_reg(c->output_regs[loc].reg); 1950 src.reg.base_offset = c->output_regs[loc].offset; 1951 1952 if (c->build.shader->stage == MESA_SHADER_FRAGMENT && 1953 var->data.location == FRAG_RESULT_DEPTH) { 1954 /* TGSI uses TGSI_SEMANTIC_POSITION.z for the depth output, while 1955 * NIR uses a single float FRAG_RESULT_DEPTH. 1956 */ 1957 src = nir_src_for_ssa(nir_channel(b, nir_ssa_for_src(b, src, 4), 2)); 1958 store->num_components = 1; 1959 } else { 1960 store->num_components = 4; 1961 } 1962 store->src[0] = src; 1963 1964 nir_intrinsic_set_base(store, loc); 1965 nir_intrinsic_set_write_mask(store, 0xf); 1966 store->src[1] = nir_src_for_ssa(nir_imm_int(b, 0)); 1967 nir_builder_instr_insert(b, &store->instr); 1968 } 1969 } 1970 } 1971 1972 static gl_shader_stage 1973 tgsi_processor_to_shader_stage(unsigned processor) 1974 { 1975 switch (processor) { 1976 case PIPE_SHADER_FRAGMENT: return MESA_SHADER_FRAGMENT; 1977 case PIPE_SHADER_VERTEX: return MESA_SHADER_VERTEX; 1978 case PIPE_SHADER_GEOMETRY: return MESA_SHADER_GEOMETRY; 1979 case PIPE_SHADER_TESS_CTRL: return MESA_SHADER_TESS_CTRL; 1980 case PIPE_SHADER_TESS_EVAL: return MESA_SHADER_TESS_EVAL; 1981 case PIPE_SHADER_COMPUTE: return MESA_SHADER_COMPUTE; 1982 default: 1983 unreachable("invalid TGSI processor"); 1984 } 1985 } 1986 1987 struct nir_shader * 1988 tgsi_to_nir(const void *tgsi_tokens, 1989 const nir_shader_compiler_options *options) 1990 { 1991 struct tgsi_parse_context parser; 1992 struct tgsi_shader_info scan; 1993 struct ttn_compile *c; 1994 struct nir_shader *s; 1995 int ret; 1996 1997 c = rzalloc(NULL, struct ttn_compile); 1998 1999 tgsi_scan_shader(tgsi_tokens, &scan); 2000 c->scan = &scan; 2001 2002 nir_builder_init_simple_shader(&c->build, NULL, 2003 tgsi_processor_to_shader_stage(scan.processor), 2004 options); 2005 s = c->build.shader; 2006 2007 s->num_inputs = scan.file_max[TGSI_FILE_INPUT] + 1; 2008 s->num_uniforms = scan.const_file_max[0] + 1; 2009 s->num_outputs = scan.file_max[TGSI_FILE_OUTPUT] + 1; 2010 2011 c->output_regs = rzalloc_array(c, struct ttn_reg_info, 2012 scan.file_max[TGSI_FILE_OUTPUT] + 1); 2013 c->temp_regs = rzalloc_array(c, struct ttn_reg_info, 2014 scan.file_max[TGSI_FILE_TEMPORARY] + 1); 2015 c->imm_defs = rzalloc_array(c, nir_ssa_def *, 2016 scan.file_max[TGSI_FILE_IMMEDIATE] + 1); 2017 2018 c->num_samp_types = scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1; 2019 c->samp_types = rzalloc_array(c, nir_alu_type, c->num_samp_types); 2020 2021 c->if_stack = rzalloc_array(c, nir_cursor, 2022 (scan.opcode_count[TGSI_OPCODE_IF] + 2023 scan.opcode_count[TGSI_OPCODE_UIF]) * 2); 2024 c->loop_stack = rzalloc_array(c, nir_cursor, 2025 scan.opcode_count[TGSI_OPCODE_BGNLOOP]); 2026 2027 ret = tgsi_parse_init(&parser, tgsi_tokens); 2028 assert(ret == TGSI_PARSE_OK); 2029 2030 while (!tgsi_parse_end_of_tokens(&parser)) { 2031 tgsi_parse_token(&parser); 2032 c->token = &parser.FullToken; 2033 2034 switch (parser.FullToken.Token.Type) { 2035 case TGSI_TOKEN_TYPE_DECLARATION: 2036 ttn_emit_declaration(c); 2037 break; 2038 2039 case TGSI_TOKEN_TYPE_INSTRUCTION: 2040 ttn_emit_instruction(c); 2041 break; 2042 2043 case TGSI_TOKEN_TYPE_IMMEDIATE: 2044 ttn_emit_immediate(c); 2045 break; 2046 } 2047 } 2048 2049 tgsi_parse_free(&parser); 2050 2051 ttn_add_output_stores(c); 2052 2053 ralloc_free(c); 2054 return s; 2055 } 2056
