| /external/vixl/examples/aarch64/ |
| add3-double.cc | 37 __ Fadd(d0, d0, d1); // d0 <- x + y
38 __ Fadd(d0, d0, d2); // d0 <- d0 + z
|
| add4-double.cc | 44 __ Fadd(d0, d0, d1);
45 __ Fadd(d2, d2, d3);
46 __ Fadd(d0, d0, d2);
|
| custom-disassembler.cc | 128 __ Fadd(d30, d16, d17);
|
| /art/compiler/optimizing/ |
| code_generator_vector_arm64.cc | 427 __ Fadd(dst.V4S(), lhs.V4S(), rhs.V4S());
431 __ Fadd(dst.V2D(), lhs.V2D(), rhs.V2D());
[all...] |
| code_generator_arm64.cc | [all...] |
| /external/v8/src/compiler/arm64/ |
| code-generator-arm64.cc | [all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceConverter.cpp | 296 case Instruction::FAdd:
297 return convertArithInstruction(Instr, Ice::InstArithmetic::Fadd);
[all...] |
| IceTargetLoweringARM32.cpp | [all...] |
| WasmTranslator.cpp | 412 Control()->appendInst(InstArithmetic::create(Func, InstArithmetic::Fadd,
[all...] |
| IceTargetLoweringX86BaseImpl.h | 661 // fadd, fsub, fmul, fdiv (also vector types)
[all...] |
| IceTargetLoweringMIPS32.cpp | [all...] |
| PNaClTranslator.cpp | [all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 564 void MacroAssembler::Fadd(const FPRegister& fd,
568 fadd(fd, fn, fm);
[all...] |
| macro-assembler-arm64.h | 395 inline void Fadd(const FPRegister& fd,
[all...] |
| /external/v8/src/crankshaft/arm64/ |
| lithium-codegen-arm64.cc | [all...] |
| /external/vixl/test/aarch64/ |
| test-assembler-aarch64.cc | [all...] |
| test-simulator-aarch64.cc | [all...] |
| test-disasm-aarch64.cc | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | [all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.h | [all...] |
| /external/swiftshader/src/Reactor/ |
| SubzeroReactor.cpp | 698 case Ice::InstArithmetic::Fadd:
750 return createArithmetic(Ice::InstArithmetic::Fadd, lhs, rhs);
[all...] |
