| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| TargetOpcodes.h | 54 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
58 SUBREG_TO_REG = 9,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXCopy.cpp | 117 TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg)
|
| /external/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 10 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
85 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
111 // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
211 case TargetOpcode::SUBREG_TO_REG:
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 10 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
105 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
125 // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
221 case TargetOpcode::SUBREG_TO_REG:
|
| PeepholeOptimizer.cpp | 179 // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
186 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
188 // The problem here is that SUBREG_TO_REG is there to assert that an
192 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 809 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 265 case TargetOpcode::SUBREG_TO_REG:
305 case TargetOpcode::SUBREG_TO_REG:
|
| InstrEmitter.cpp | 530 Opc == TargetOpcode::SUBREG_TO_REG) {
557 // Create the insert_subreg or subreg_to_reg machine instruction.
561 // If creating a subreg_to_reg, then the first input operand
563 if (Opc == TargetOpcode::SUBREG_TO_REG) {
575 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
730 Opc == TargetOpcode::SUBREG_TO_REG) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 55 case TargetOpcode::SUBREG_TO_REG:
107 case TargetOpcode::SUBREG_TO_REG:
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 799 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/CodeGen/ |
| MachineInstr.h | 809 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/CodeGen/ |
| MachineInstr.h | 809 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /prebuilts/clang/host/darwin-x86/clang-4691093/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 799 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4393122/include/llvm/CodeGen/ |
| MachineInstr.h | 809 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4479392/include/llvm/CodeGen/ |
| MachineInstr.h | 809 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4579689/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-4630689/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-4639204/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-4691093/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| MachineInstr.h | 279 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 485 Opc == TargetOpcode::SUBREG_TO_REG) {
512 // Create the insert_subreg or subreg_to_reg machine instruction.
516 // If creating a subreg_to_reg, then the first input operand
518 if (Opc == TargetOpcode::SUBREG_TO_REG) {
530 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
664 Opc == TargetOpcode::SUBREG_TO_REG) {
[all...] |
