| /external/v8/src/arm/ |
| codegen-arm.cc | 81 __ sub(chars, chars, Operand(64), SetCC);
140 __ bic(temp1, chars, Operand(0x3), SetCC);
148 __ bic(temp2, chars, Operand(0x3), SetCC);
160 __ mov(chars, Operand(chars, LSL, 31), SetCC);
244 __ mov(chars, Operand(chars, LSL, 31), SetCC); // bit0 => ne, bit1 => cs
|
| macro-assembler-arm.cc | [all...] |
| code-stubs-arm.cc | 133 __ rsb(scratch, scratch, Operand(51), SetCC);
261 __ orr(r0, r3, Operand(r2), SetCC);
737 __ mov(scratch, Operand(scratch, LSR, 1), SetCC);
[all...] |
| constants-arm.h | 243 SetCC = 1 << 20, // Set condition code.
|
| macro-assembler-arm.h | [all...] |
| /external/v8/src/builtins/arm/ |
| builtins-arm.cc | 146 __ sub(r4, r4, Operand(1), SetCC);
240 __ sub(r0, r0, Operand(1), SetCC);
286 __ sub(r0, r0, Operand(1), SetCC);
362 __ sub(r0, r0, Operand(1), SetCC);
433 __ sub(r0, r0, Operand(1), SetCC);
628 __ sub(r4, r4, Operand(2), SetCC);
820 __ sub(r3, r3, Operand(Smi::FromInt(1)), SetCC);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 229 // setcc operations results (slt, sgt, ...).
264 // Used by legalize types to correctly generate the setcc result.
265 // Without this, every float setcc comes with a AND/OR with the result,
268 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
280 setOperationAction(ISD::SETCC, MVT::f32, Custom);
281 setOperationAction(ISD::SETCC, MVT::f64, Custom);
542 // Creates and returns an FPCmp node from a setcc node.
543 // Returns Op if setcc is not a floating point comparison.
545 // must be a SETCC node
546 if (Op.getOpcode() != ISD::SETCC)
[all...] |
| MipsSEISelLowering.cpp | 79 setTargetDAGCombine(ISD::SETCC);
175 setOperationAction(ISD::SETCC, MVT::i32, Legal);
179 setOperationAction(ISD::SETCC, MVT::f32, Legal);
184 setOperationAction(ISD::SETCC, MVT::f64, Legal);
222 setOperationAction(ISD::SETCC, MVT::i64, Legal);
285 setOperationAction(ISD::SETCC, Ty, Legal);
322 setOperationAction(ISD::SETCC, Ty, Legal);
[all...] |
| /external/v8/src/crankshaft/arm/ |
| lithium-codegen-arm.cc | 805 __ sub(r1, r1, Operand(1), SetCC);
985 __ rsb(dividend, dividend, Operand::Zero(), SetCC);
[all...] |
| /external/v8/src/regexp/arm/ |
| regexp-macro-assembler-arm.cc | 216 __ sub(r1, r1, r0, SetCC); // Length of capture.
359 __ sub(r1, r1, r0, SetCC); // Length to check.
656 __ sub(r0, sp, r0, SetCC);
719 __ sub(r2, r2, Operand(1), SetCC);
[all...] |
| /external/v8/src/compiler/arm/ |
| code-generator-arm.cc | 36 return SetCC;
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 73 setOperationAction(ISD::SETCC, MVT::i32, Custom);
178 case ISD::SETCC:
[all...] |
| /external/v8/src/x87/ |
| disasm-x87.cc | 325 int SetCC(byte* data);
648 int DisassemblerX87::SetCC(byte* data) {
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 82 // X86 is weird. It always uses i8 for shift amounts and setcc results.
390 setOperationAction(ISD::SETCC, VT, Custom);
396 setOperationAction(ISD::SETCC, VT, Custom);
681 setOperationAction(ISD::SETCC, VT, Expand);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 111 setOperationAction(ISD::SETCC, MVT::i1, Promote);
112 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
113 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
229 setTargetDAGCombine(ISD::SETCC);
541 // create setcc with i1 operands. We don't have instructions for i1 setcc.
542 if (VT == MVT::i1 && Op == ISD::SETCC)
[all...] |
| /external/v8/src/full-codegen/arm/ |
| full-codegen-arm.cc | 171 __ sub(r2, r2, Operand(1), SetCC);
346 __ sub(r3, r3, Operand(Smi::FromInt(delta)), SetCC);
[all...] |
| /external/v8/src/ia32/ |
| disasm-ia32.cc | 388 int SetCC(byte* data);
712 int DisassemblerIA32::SetCC(byte* data) {
[all...] |
| /external/v8/src/x64/ |
| disasm-x64.cc | 478 int SetCC(byte* data);
870 int DisassemblerX64::SetCC(byte* data) {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 495 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
496 // that selects between the values 1 and 0, making it equivalent to a setcc.
502 if (N.getOpcode() == ISD::SETCC) {
521 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
[all...] |
| LegalizeIntegerTypes.cpp | 69 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
518 // Get the SETCC result using the canonical SETCC type.
519 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
524 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
774 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 729 // Return true if this node is a setcc, or is a select_cc
731 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
736 if (N.getOpcode() == ISD::SETCC) {
758 /// Return true if this is a SetCC-equivalent operation with only one use.
[all...] |
| LegalizeIntegerTypes.cpp | 77 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
578 // Promote all the way up to the canonical SetCC type.
619 // Get the SETCC result using the canonical SETCC type.
620 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
625 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 63 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
108 setOperationAction(ISD::SETCC, MVT::i32, Custom);
109 setOperationAction(ISD::SETCC, MVT::i64, Custom);
110 setOperationAction(ISD::SETCC, MVT::f32, Custom);
111 setOperationAction(ISD::SETCC, MVT::f64, Custom);
159 setOperationAction(ISD::SETCC, MVT::f128, Custom);
262 setOperationAction(ISD::SETCC, MVT::f16, Promote);
332 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
365 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
543 setOperationAction(ISD::SETCC, MVT::v1f64, Expand)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86ISelLowering.cpp | 182 // X86 is weird, it always uses i8 for shift amounts and setcc results.
424 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
425 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
426 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
427 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
428 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
429 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
432 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
725 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
[all...] |
| /art/compiler/utils/x86_64/ |
| assembler_x86_64_test.cc | [all...] |
