| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 96 if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) {
99 DEBUG(dbgs() << " Ignoring, XZR or WZR already used by the instruction\n");
127 NewReg = AArch64::WZR;
|
| AArch64RedundantCopyElimination.cpp | 14 // %W0 = COPY %WZR
129 if ((SrcReg == AArch64::XZR || SrcReg == AArch64::WZR) &&
|
| AArch64InstrInfo.cpp | 333 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
350 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
455 BuildMI(MBB, I, DL, get(AArch64::SUBSWri), AArch64::WZR)
478 BuildMI(MBB, I, DL, get(AArch64::ANDSWri), AArch64::WZR)
792 if (MI.definesRegister(AArch64::WZR) || MI.definesRegister(AArch64::XZR))
891 if (CmpInstr.definesRegister(AArch64::WZR) ||
[all...] |
| AArch64ExpandPseudoInsts.cpp | 420 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) {
435 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
[all...] |
| AArch64RegisterInfo.cpp | 124 Reserved.set(AArch64::WZR);
154 case AArch64::WZR:
|
| AArch64FastISel.cpp | 345 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
486 unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
[all...] |
| AArch64AsmPrinter.cpp | 263 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
445 FMov.addOperand(MCOperand::createReg(AArch64::WZR));
|
| AArch64LoadStoreOptimizer.cpp | 627 getLdStRegOp(MI).getReg() == AArch64::WZR;
775 .addReg(isNarrowStore(Opc) ? AArch64::WZR : AArch64::XZR)
958 .addReg(IsStoreXReg ? AArch64::XZR : AArch64::WZR)
[all...] |
| AArch64ConditionalCompares.cpp | 257 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
|
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| plan9x.go | 118 if rno >= 0 && rno <= int(WZR) {
134 if rno <= uint16(WZR) {
152 if rno <= uint16(WZR) {
161 if rno <= uint16(WZR) {
174 if rno <= uint16(WZR) {
195 if rno <= uint16(WZR) {
203 if rno <= uint16(WZR) {
215 if rno <= uint16(WZR) {
227 if rno <= uint16(WZR) {
297 } else if rno <= uint16(WZR) {
[all...] |
| inst.go | 96 WZR
329 WSP = WZR // These are different registers with the same encoding.
337 case r == WZR:
338 return "WZR"
|
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| plan9x.go | 118 if rno >= 0 && rno <= int(WZR) {
134 if rno <= uint16(WZR) {
152 if rno <= uint16(WZR) {
161 if rno <= uint16(WZR) {
174 if rno <= uint16(WZR) {
195 if rno <= uint16(WZR) {
203 if rno <= uint16(WZR) {
215 if rno <= uint16(WZR) {
227 if rno <= uint16(WZR) {
297 } else if rno <= uint16(WZR) {
[all...] |
| inst.go | 96 WZR
329 WSP = WZR // These are different registers with the same encoding.
337 case r == WZR:
338 return "WZR"
|
| /art/compiler/utils/arm64/ |
| assembler_arm64.h | 133 } else if (code == WZR) {
134 return vixl::aarch64::wzr;
|
| managed_register_arm64_test.cc | 95 wreg = Arm64ManagedRegister::FromWRegister(WZR);
157 reg = Arm64ManagedRegister::FromWRegister(WZR);
384 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
406 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
428 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
443 reg_o = Arm64ManagedRegister::FromWRegister(WZR);
463 reg_o = Arm64ManagedRegister::FromWRegister(WZR);
466 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
485 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
506 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
[all...] |
| managed_register_arm64.h | 83 if (IsZeroRegister()) return WZR;
|
| /art/runtime/arch/arm64/ |
| registers_arm64.h | 107 WZR = 32,
|
| /external/llvm/test/MC/AArch64/ |
| arm64-aliases.s | 29 orr w2, wzr, w9
43 ands wzr, w1, w2, lsl #2
58 ; ADDS to WZR/XZR is a CMN
80 ; SUBS to WZR/XZR is a CMP
90 cmp wzr, w1
103 ; CHECK: cmp wzr, w1 ; encoding: [0xff,0x03,0x01,0x6b]
110 ; SUB/SUBS from WZR/XZR is a NEG
142 mov wzr, #0xffffffff
143 mov wzr, #0xffffff00
147 ; CHECK: mov wzr, #-0x
[all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 64 case AArch64::XZR: return AArch64::WZR;
104 case AArch64::WZR: return AArch64::XZR;
|
| /art/compiler/optimizing/ |
| common_arm64.h | 43 static_assert((SP == 31) && (WSP == 31) && (XZR == 32) && (WZR == 32),
149 : vixl::aarch64::Register(vixl::aarch64::wzr);
297 // only SP/WSP and ZXR/WZR codes are different between art and vixl.
|
| code_generator_arm64.cc | 633 DCHECK_NE(ref_.reg(), WZR);
1541 Register wzr = Register(VIXLRegCodeFromART(WZR), kWRegSize); local
[all...] |
| intrinsics_arm64.cc | 197 DCHECK_NE(tmp_.reg(), WZR);
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 166 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
222 // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
258 MI->getOperand(1).getReg() == AArch64::WZR) &&
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 408 AArch64::W30, AArch64::WZR
429 if (Register == AArch64::WZR)
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
