| /external/llvm/lib/Target/AArch64/ |
| AArch64CallLowering.cpp | 84 MIRBuilder.getMBB().addLiveIn(VA.getLocReg());
85 MIRBuilder.buildInstr(TargetOpcode::COPY, VRegs[i], VA.getLocReg());
|
| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 222 Regs.push_back(MCPhysReg(Locs[I].getLocReg()));
279 if (Loc1.getLocReg() != Loc2.getLocReg())
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 186 TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
188 assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
192 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
244 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
269 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Opi, SDValue());
330 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
391 unsigned Reg = RV.getLocReg();
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 104 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
114 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
187 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
202 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
213 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
479 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
483 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
517 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
521 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
600 unsigned Reg = RVLocs[i].getLocReg();
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 249 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag);
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
253 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1,
256 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
260 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
343 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
351 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
355 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
420 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi)
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 183 RegInfo.addLiveIn(VA.getLocReg(), VReg);
291 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
375 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
380 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
413 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(),
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 331 RegInfo.addLiveIn(VA.getLocReg(), VReg);
429 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
528 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
575 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
595 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| CallingConvLower.h | 121 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86FastISel.cpp | 750 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
779 unsigned DstReg = VA.getLocReg();
788 MRI.addLiveOut(VA.getLocReg());
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 742 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
849 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
|
| /external/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 448 RegInfo.addLiveIn(VA.getLocReg(), VReg);
542 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
546 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
674 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
775 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 448 RegInfo.addLiveIn(VA.getLocReg(), VReg);
533 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
539 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
604 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
705 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 339 RegInfo.addLiveIn(VA.getLocReg(), VReg);
410 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
420 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
492 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
583 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 579 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
583 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
633 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
643 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
785 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
|
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/CodeGen/ |
| CallingConvLower.h | 148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
|
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/CodeGen/ |
| CallingConvLower.h | 148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
|
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/CodeGen/ |
| CallingConvLower.h | 149 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
|
| /prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/CodeGen/ |
| CallingConvLower.h | 149 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
|
| /prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/CodeGen/ |
| CallingConvLower.h | 149 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
|
