| /external/mesa3d/src/gallium/drivers/ilo/core/ |
| ilo_state_zs.h | 62 uint32_t hiz[3]; member in struct:ilo_state_zs
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| ilo_state_zs.c | 208 * Experiments on Gen7.5 show that HiZ resolve also requires the rectangle
210 * always require a level to be aligned when HiZ is enabled.
561 STATIC_ASSERT(ARRAY_SIZE(zs->hiz) >= 3);
562 zs->hiz[0] = 0;
563 zs->hiz[1] = 0;
565 zs->hiz[2] = 0;
585 /* offset to the level as Gen6 does not support mipmapped HiZ */
589 STATIC_ASSERT(ARRAY_SIZE(zs->hiz) >= 3);
590 zs->hiz[0] = dw1;
591 zs->hiz[1] = dw2
[all...] |
| ilo_builder_3d_bottom.h | 789 dw[1] = zs->hiz[0];
792 dw[4] = zs->hiz[2];
798 zs->hiz_vma->bo_offset + zs->hiz[1],
802 dw[1] = zs->hiz[0];
809 zs->hiz_vma->bo_offset + zs->hiz[1],
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| gen6_depth_state.c | 43 bool hiz, bool separate_stencil,
57 /* Enable the hiz bit if we're doing separate stencil, because it and the
66 bool enable_hiz_ss = hiz || separate_stencil;
118 ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
152 if (hiz || separate_stencil) {
155 * stencil enable' and 'hiz enable' bits were set. Therefore we must
161 /* Emit hiz buffer. */
162 if (hiz) {
232 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
237 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes
[all...] |
| gen7_misc_state.c | 38 bool hiz, bool separate_stencil,
110 ((hiz ? 1 : 0) << 22) |
141 if (!hiz) {
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| gen8_depth_state.c | 45 bool hiz,
68 (hiz ? 1 : 0) << 22 |
84 if (!hiz) {
153 bool hiz, bool separate_stencil,
223 hiz, width, height, depth, lod, min_array_element);
254 * 3DSTATE_DEPTH_BUFFER::HIZ Enable
269 * HiZ operations are done outside of the normal state upload, so they're
395 * Emit packets to perform a depth/HiZ resolve or fast depth/stencil clear.
407 /* Disable the PMA stall fix since we're about to do a HiZ operation. */
415 * requirements for most HiZ operations. Otherwise, use the actual siz
[all...] |
| brw_misc_state.c | 158 * between the depth, hiz, and stencil buffers. Because it can be hard to get
191 /* Each HiZ row represents 2 rows of pixels */
490 bool hiz = depth_irb && intel_renderbuffer_has_hiz(depth_irb); local
521 if ((brw->gen < 7 && hiz) || brw->gen >= 7) {
525 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
526 assert(brw->gen >= 7 || !separate_stencil || hiz);
529 assert(!hiz || depth_mt->tiling == I915_TILING_Y);
562 stencil_mt, hiz, separate_stencil,
572 bool hiz, bool separate_stencil,
576 /* Enable the hiz bit if we're doing separate stencil, because it and th
[all...] |
| brw_context.h | 679 * HiZ buffers (i965+ only)
687 bool hiz, bool separate_stencil,
[all...] |
| intel_screen.c | 60 DRI_CONF_OPT_BEGIN_B(hiz, "true")
[all...] |
| /external/mesa3d/src/intel/blorp/ |
| blorp_genX_exec.h | 314 * dw2: Viewport Index. The HiZ op disables viewport mapping and
316 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
853 blorp_emit(batch, GENX(3DSTATE_HIER_DEPTH_BUFFER), hiz) {
855 hiz.SurfacePitch = params->depth.aux_surf.row_pitch - 1;
856 hiz.SurfaceBaseAddress = params->depth.aux_addr;
857 hiz.HierarchicalDepthBufferMOCS = mocs;
859 hiz.SurfaceQPitch =
886 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
[all...] |
