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      1 /*
      2  * Copyright  2011 Intel Corporation
      3  *
      4  * Permission is hereby granted, free of charge, to any person obtaining a
      5  * copy of this software and associated documentation files (the "Software"),
      6  * to deal in the Software without restriction, including without limitation
      7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8  * and/or sell copies of the Software, and to permit persons to whom the
      9  * Software is furnished to do so, subject to the following conditions:
     10  *
     11  * The above copyright notice and this permission notice (including the next
     12  * paragraph) shall be included in all copies or substantial portions of the
     13  * Software.
     14  *
     15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
     21  * IN THE SOFTWARE.
     22  */
     23 
     24 #include "main/mtypes.h"
     25 #include "intel_batchbuffer.h"
     26 #include "intel_mipmap_tree.h"
     27 #include "intel_fbo.h"
     28 #include "brw_context.h"
     29 #include "brw_state.h"
     30 #include "brw_defines.h"
     31 
     32 void
     33 gen7_emit_depth_stencil_hiz(struct brw_context *brw,
     34                             struct intel_mipmap_tree *depth_mt,
     35                             uint32_t depth_offset, uint32_t depthbuffer_format,
     36                             uint32_t depth_surface_type,
     37                             struct intel_mipmap_tree *stencil_mt,
     38                             bool hiz, bool separate_stencil,
     39                             uint32_t width, uint32_t height,
     40                             uint32_t tile_x, uint32_t tile_y)
     41 {
     42    struct gl_context *ctx = &brw->ctx;
     43    const uint8_t mocs = GEN7_MOCS_L3;
     44    struct gl_framebuffer *fb = ctx->DrawBuffer;
     45    uint32_t surftype;
     46    unsigned int depth = 1;
     47    unsigned int min_array_element;
     48    GLenum gl_target = GL_TEXTURE_2D;
     49    unsigned int lod;
     50    const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
     51    const struct intel_renderbuffer *irb = NULL;
     52    const struct gl_renderbuffer *rb = NULL;
     53 
     54    /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
     55    if (!mt && brw->no_depth_or_stencil) {
     56       assert(brw->hw_ctx);
     57       return;
     58    }
     59 
     60    brw_emit_depth_stall_flushes(brw);
     61 
     62    irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
     63    if (!irb)
     64       irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
     65    rb = (struct gl_renderbuffer*) irb;
     66 
     67    if (rb) {
     68       depth = MAX2(irb->layer_count, 1);
     69       if (rb->TexImage)
     70          gl_target = rb->TexImage->TexObject->Target;
     71    }
     72 
     73    switch (gl_target) {
     74    case GL_TEXTURE_CUBE_MAP_ARRAY:
     75    case GL_TEXTURE_CUBE_MAP:
     76       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
     77        * situation, but experiments show that gl_Layer doesn't work when we do
     78        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
     79        * equivalent.
     80        */
     81       surftype = BRW_SURFACE_2D;
     82       depth *= 6;
     83       break;
     84    case GL_TEXTURE_3D:
     85       assert(mt);
     86       depth = MAX2(mt->logical_depth0, 1);
     87       /* fallthrough */
     88    default:
     89       surftype = translate_tex_target(gl_target);
     90       break;
     91    }
     92 
     93    min_array_element = irb ? irb->mt_layer : 0;
     94 
     95    lod = irb ? irb->mt_level - irb->mt->first_level : 0;
     96 
     97    if (mt) {
     98       width = mt->logical_width0;
     99       height = mt->logical_height0;
    100    }
    101 
    102    /* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */
    103    BEGIN_BATCH(7);
    104    /* 3DSTATE_DEPTH_BUFFER dw0 */
    105    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
    106 
    107    /* 3DSTATE_DEPTH_BUFFER dw1 */
    108    OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
    109              (depthbuffer_format << 18) |
    110              ((hiz ? 1 : 0) << 22) |
    111              ((stencil_mt != NULL && ctx->Stencil._WriteEnabled) << 27) |
    112              (brw_depth_writes_enabled(brw) << 28) |
    113              (surftype << 29));
    114 
    115    /* 3DSTATE_DEPTH_BUFFER dw2 */
    116    if (depth_mt) {
    117       OUT_RELOC(depth_mt->bo,
    118 	        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
    119 	        0);
    120    } else {
    121       OUT_BATCH(0);
    122    }
    123 
    124    /* 3DSTATE_DEPTH_BUFFER dw3 */
    125    OUT_BATCH(((width - 1) << 4) |
    126              ((height - 1) << 18) |
    127              lod);
    128 
    129    /* 3DSTATE_DEPTH_BUFFER dw4 */
    130    OUT_BATCH(((depth - 1) << 21) |
    131              (min_array_element << 10) |
    132              mocs);
    133 
    134    /* 3DSTATE_DEPTH_BUFFER dw5 */
    135    OUT_BATCH(0);
    136 
    137    /* 3DSTATE_DEPTH_BUFFER dw6 */
    138    OUT_BATCH((depth - 1) << 21);
    139    ADVANCE_BATCH();
    140 
    141    if (!hiz) {
    142       BEGIN_BATCH(3);
    143       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
    144       OUT_BATCH(0);
    145       OUT_BATCH(0);
    146       ADVANCE_BATCH();
    147    } else {
    148       assert(depth_mt);
    149       struct intel_miptree_hiz_buffer *hiz_buf = depth_mt->hiz_buf;
    150 
    151       BEGIN_BATCH(3);
    152       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
    153       OUT_BATCH((mocs << 25) |
    154                 (hiz_buf->aux_base.pitch - 1));
    155       OUT_RELOC(hiz_buf->aux_base.bo,
    156                 I915_GEM_DOMAIN_RENDER,
    157                 I915_GEM_DOMAIN_RENDER,
    158                 0);
    159       ADVANCE_BATCH();
    160    }
    161 
    162    if (stencil_mt == NULL) {
    163       BEGIN_BATCH(3);
    164       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
    165       OUT_BATCH(0);
    166       OUT_BATCH(0);
    167       ADVANCE_BATCH();
    168    } else {
    169       stencil_mt->r8stencil_needs_update = true;
    170       const int enabled = brw->is_haswell ? HSW_STENCIL_ENABLED : 0;
    171 
    172       BEGIN_BATCH(3);
    173       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
    174       /* The stencil buffer has quirky pitch requirements.  From the
    175        * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
    176        * dword 1 bits 16:0 - Surface Pitch):
    177        *
    178        *    The pitch must be set to 2x the value computed based on width, as
    179        *    the stencil buffer is stored with two rows interleaved.
    180        *
    181        * While the Ivybridge PRM lacks this comment, the BSpec contains the
    182        * same text, and experiments indicate that this is necessary.
    183        */
    184       OUT_BATCH(enabled |
    185                 mocs << 25 |
    186 	        (2 * stencil_mt->pitch - 1));
    187       OUT_RELOC(stencil_mt->bo,
    188 	        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
    189 		0);
    190       ADVANCE_BATCH();
    191    }
    192 
    193    BEGIN_BATCH(3);
    194    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
    195    OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
    196    OUT_BATCH(1);
    197    ADVANCE_BATCH();
    198 
    199    brw->no_depth_or_stencil = !mt;
    200 }
    201 
    202 /**
    203  * \see brw_context.state.depth_region
    204  */
    205 const struct brw_tracked_state gen7_depthbuffer = {
    206    .dirty = {
    207       .mesa = _NEW_BUFFERS |
    208               _NEW_DEPTH |
    209               _NEW_STENCIL,
    210       .brw = BRW_NEW_BATCH |
    211              BRW_NEW_BLORP,
    212    },
    213    .emit = brw_emit_depthbuffer,
    214 };
    215