1 /* 2 * Copyright 2006 VMware, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 /** @file intel_mipmap_tree.h 27 * 28 * This file defines the structure that wraps a BO and describes how the 29 * mipmap levels and slices of a texture are laid out. 30 * 31 * The hardware has a fixed layout of a texture depending on parameters such 32 * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of 33 * mipmap levels. The individual level/layer slices are each 2D rectangles of 34 * pixels at some x/y offset from the start of the drm_intel_bo. 35 * 36 * Original OpenGL allowed texture miplevels to be specified in arbitrary 37 * order, and a texture may change size over time. Thus, each 38 * intel_texture_image has a reference to a miptree that contains the pixel 39 * data sized appropriately for it, which will later be referenced by/copied 40 * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so 41 * that there's a single miptree for the complete texture. 42 */ 43 44 #ifndef INTEL_MIPMAP_TREE_H 45 #define INTEL_MIPMAP_TREE_H 46 47 #include <assert.h> 48 49 #include "main/mtypes.h" 50 #include "isl/isl.h" 51 #include "intel_bufmgr.h" 52 #include "intel_resolve_map.h" 53 #include <GL/internal/dri_interface.h> 54 55 #ifdef __cplusplus 56 extern "C" { 57 #endif 58 59 struct brw_context; 60 struct intel_renderbuffer; 61 62 struct intel_resolve_map; 63 struct intel_texture_image; 64 65 /** 66 * This bit extends the set of GL_MAP_*_BIT enums. 67 * 68 * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a 69 * depthstencil-split-to-separate-stencil miptree, we'll normally make a 70 * temporary and recreate the kind of data requested by Mesa core, since we're 71 * satisfying some glGetTexImage() request or something. 72 * 73 * However, occasionally you want to actually map the miptree's current data 74 * without transcoding back. This flag to intel_miptree_map() gets you that. 75 */ 76 #define BRW_MAP_DIRECT_BIT 0x80000000 77 78 struct intel_miptree_map { 79 /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */ 80 GLbitfield mode; 81 /** Region of interest for the map. */ 82 int x, y, w, h; 83 /** Possibly malloced temporary buffer for the mapping. */ 84 void *buffer; 85 /** Possible pointer to a temporary linear miptree for the mapping. */ 86 struct intel_mipmap_tree *linear_mt; 87 /** Pointer to the start of (map_x, map_y) returned by the mapping. */ 88 void *ptr; 89 /** Stride of the mapping. */ 90 int stride; 91 }; 92 93 /** 94 * Describes the location of each texture image within a miptree. 95 */ 96 struct intel_mipmap_level 97 { 98 /** Offset to this miptree level, used in computing x_offset. */ 99 GLuint level_x; 100 /** Offset to this miptree level, used in computing y_offset. */ 101 GLuint level_y; 102 103 /** 104 * \brief Number of 2D slices in this miplevel. 105 * 106 * The exact semantics of depth varies according to the texture target: 107 * - For GL_TEXTURE_CUBE_MAP, depth is 6. 108 * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is 109 * identical for all miplevels in the texture. 110 * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its 111 * value, like width and height, varies with miplevel. 112 * - For other texture types, depth is 1. 113 * - Additionally, for UMS and CMS miptrees, depth is multiplied by 114 * sample count. 115 */ 116 GLuint depth; 117 118 /** 119 * \brief Is HiZ enabled for this level? 120 * 121 * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been 122 * allocated and (2) the HiZ memory for the slices in this level reside at 123 * \c mt->hiz_mt->level[l]. 124 */ 125 bool has_hiz; 126 127 /** 128 * \brief List of 2D images in this mipmap level. 129 * 130 * This may be a list of cube faces, array slices in 2D array texture, or 131 * layers in a 3D texture. The list's length is \c depth. 132 */ 133 struct intel_mipmap_slice { 134 /** 135 * \name Offset to slice 136 * \{ 137 * 138 * Hardware formats are so diverse that that there is no unified way to 139 * compute the slice offsets, so we store them in this table. 140 * 141 * The (x, y) offset to slice \c s at level \c l relative the miptrees 142 * base address is 143 * \code 144 * x = mt->level[l].slice[s].x_offset 145 * y = mt->level[l].slice[s].y_offset 146 * 147 * On some hardware generations, we program these offsets into 148 * RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset. 149 */ 150 GLuint x_offset; 151 GLuint y_offset; 152 /** \} */ 153 154 /** 155 * Mapping information. Persistent for the duration of 156 * intel_miptree_map/unmap on this slice. 157 */ 158 struct intel_miptree_map *map; 159 } *slice; 160 }; 161 162 /** 163 * Enum for keeping track of the different MSAA layouts supported by Gen7. 164 */ 165 enum intel_msaa_layout 166 { 167 /** 168 * Ordinary surface with no MSAA. 169 */ 170 INTEL_MSAA_LAYOUT_NONE, 171 172 /** 173 * Interleaved Multisample Surface. The additional samples are 174 * accommodated by scaling up the width and the height of the surface so 175 * that all the samples corresponding to a pixel are located at nearby 176 * memory locations. 177 * 178 * @see PRM section "Interleaved Multisampled Surfaces" 179 */ 180 INTEL_MSAA_LAYOUT_IMS, 181 182 /** 183 * Uncompressed Multisample Surface. The surface is stored as a 2D array, 184 * with array slice n containing all pixel data for sample n. 185 * 186 * @see PRM section "Uncompressed Multisampled Surfaces" 187 */ 188 INTEL_MSAA_LAYOUT_UMS, 189 190 /** 191 * Compressed Multisample Surface. The surface is stored as in 192 * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS 193 * (Multisample Control Surface) buffer. Each pixel in the MCS buffer 194 * indicates the mapping from sample number to array slice. This allows 195 * the common case (where all samples constituting a pixel have the same 196 * color value) to be stored efficiently by just using a single array 197 * slice. 198 * 199 * @see PRM section "Compressed Multisampled Surfaces" 200 */ 201 INTEL_MSAA_LAYOUT_CMS, 202 }; 203 204 enum miptree_array_layout { 205 /* Each array slice contains all miplevels packed together. 206 * 207 * Gen hardware usually wants multilevel miptrees configured this way. 208 * 209 * A 2D Array texture with 2 slices and multiple LODs using 210 * ALL_LOD_IN_EACH_SLICE would look somewhat like this: 211 * 212 * +----------+ 213 * | | 214 * | | 215 * +----------+ 216 * +---+ +-+ 217 * | | +-+ 218 * +---+ * 219 * +----------+ 220 * | | 221 * | | 222 * +----------+ 223 * +---+ +-+ 224 * | | +-+ 225 * +---+ * 226 */ 227 ALL_LOD_IN_EACH_SLICE, 228 229 /* Each LOD contains all slices of that LOD packed together. 230 * 231 * In some situations, Gen7+ hardware can use the array_spacing_lod0 232 * feature to save space when the surface only contains LOD 0. 233 * 234 * Gen6 uses this for separate stencil and hiz since gen6 does not support 235 * multiple LODs for separate stencil and hiz. 236 * 237 * A 2D Array texture with 2 slices and multiple LODs using 238 * ALL_SLICES_AT_EACH_LOD would look somewhat like this: 239 * 240 * +----------+ 241 * | | 242 * | | 243 * +----------+ 244 * | | 245 * | | 246 * +----------+ 247 * +---+ +-+ 248 * | | +-+ 249 * +---+ +-+ 250 * | | : 251 * +---+ 252 */ 253 ALL_SLICES_AT_EACH_LOD, 254 }; 255 256 enum intel_aux_disable { 257 INTEL_AUX_DISABLE_NONE = 0, 258 INTEL_AUX_DISABLE_HIZ = 1 << 1, 259 INTEL_AUX_DISABLE_MCS = 1 << 2, 260 INTEL_AUX_DISABLE_CCS = 1 << 3, 261 INTEL_AUX_DISABLE_ALL = INTEL_AUX_DISABLE_HIZ | 262 INTEL_AUX_DISABLE_MCS | 263 INTEL_AUX_DISABLE_CCS 264 }; 265 266 /** 267 * Miptree aux buffer. These buffers are associated with a miptree, but the 268 * format is managed by the hardware. 269 * 270 * For Gen7+, we always give the hardware the start of the buffer, and let it 271 * handle all accesses to the buffer. Therefore we don't need the full miptree 272 * layout structure for this buffer. 273 */ 274 struct intel_miptree_aux_buffer 275 { 276 /** 277 * Buffer object containing the pixel data. 278 * 279 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress 280 * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress 281 */ 282 drm_intel_bo *bo; 283 284 /** 285 * Offset into bo where the surface starts. 286 * 287 * @see intel_mipmap_aux_buffer::bo 288 * 289 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress 290 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress 291 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress 292 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress 293 */ 294 uint32_t offset; 295 296 /* 297 * Size of the MCS surface. 298 * 299 * This is needed when doing any gtt mapped operations on the buffer (which 300 * will be Y-tiled). It is possible that it will not be the same as bo->size 301 * when the drm allocator rounds up the requested size. 302 */ 303 size_t size; 304 305 /** 306 * Pitch in bytes. 307 * 308 * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch 309 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch 310 */ 311 uint32_t pitch; 312 313 /** 314 * The distance in rows between array slices. 315 * 316 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch 317 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch 318 */ 319 uint32_t qpitch; 320 }; 321 /** 322 * The HiZ buffer requires extra attributes on earlier GENs. This is easily 323 * contained within an intel_mipmap_tree. To make sure we do not abuse this, we 324 * keep the hiz datastructure separate. 325 */ 326 struct intel_miptree_hiz_buffer 327 { 328 struct intel_miptree_aux_buffer aux_base; 329 330 /** 331 * Hiz miptree. Used only by Gen6. 332 */ 333 struct intel_mipmap_tree *mt; 334 }; 335 336 /* Tile resource modes */ 337 enum intel_miptree_tr_mode { 338 INTEL_MIPTREE_TRMODE_NONE, 339 INTEL_MIPTREE_TRMODE_YF, 340 INTEL_MIPTREE_TRMODE_YS 341 }; 342 343 struct intel_mipmap_tree 344 { 345 /** 346 * Buffer object containing the surface. 347 * 348 * @see intel_mipmap_tree::offset 349 * @see RENDER_SURFACE_STATE.SurfaceBaseAddress 350 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress 351 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress 352 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress 353 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress 354 */ 355 drm_intel_bo *bo; 356 357 /** 358 * Pitch in bytes. 359 * 360 * @see RENDER_SURFACE_STATE.SurfacePitch 361 * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch 362 * @see 3DSTATE_DEPTH_BUFFER.SurfacePitch 363 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch 364 * @see 3DSTATE_STENCIL_BUFFER.SurfacePitch 365 */ 366 uint32_t pitch; 367 368 /** 369 * One of the I915_TILING_* flags. 370 * 371 * @see RENDER_SURFACE_STATE.TileMode 372 * @see 3DSTATE_DEPTH_BUFFER.TileMode 373 */ 374 uint32_t tiling; 375 376 /** 377 * @see RENDER_SURFACE_STATE.TiledResourceMode 378 * @see 3DSTATE_DEPTH_BUFFER.TiledResourceMode 379 */ 380 enum intel_miptree_tr_mode tr_mode; 381 382 /** 383 * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc. 384 * 385 * @see RENDER_SURFACE_STATE.SurfaceType 386 * @see RENDER_SURFACE_STATE.SurfaceArray 387 * @see 3DSTATE_DEPTH_BUFFER.SurfaceType 388 */ 389 GLenum target; 390 391 /** 392 * Generally, this is just the same as the gl_texture_image->TexFormat or 393 * gl_renderbuffer->Format. 394 * 395 * However, for textures and renderbuffers with packed depth/stencil formats 396 * on hardware where we want or need to use separate stencil, there will be 397 * two miptrees for storing the data. If the depthstencil texture or rb is 398 * MESA_FORMAT_Z32_FLOAT_S8X24_UINT, then mt->format will be 399 * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be 400 * MESA_FORMAT_Z24_UNORM_X8_UINT. 401 * 402 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture 403 * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format. 404 * 405 * @see RENDER_SURFACE_STATE.SurfaceFormat 406 * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat 407 */ 408 mesa_format format; 409 410 /** 411 * This variable stores the value of ETC compressed texture format 412 * 413 * @see RENDER_SURFACE_STATE.SurfaceFormat 414 */ 415 mesa_format etc_format; 416 417 /** 418 * @name Surface Alignment 419 * @{ 420 * 421 * This defines the alignment of the upperleft pixel of each "slice" in the 422 * surface. The alignment is in pixel coordinates relative to the surface's 423 * most upperleft pixel, which is the pixel at (x=0, y=0, layer=0, 424 * level=0). 425 * 426 * The hardware docs do not use the term "slice". We use "slice" to mean 427 * the pixels at a given miplevel and layer. For 2D surfaces, the layer is 428 * the array slice; for 3D surfaces, the layer is the z offset. 429 * 430 * In the surface layout equations found in the hardware docs, the 431 * horizontal and vertical surface alignments often appear as variables 'i' 432 * and 'j'. 433 */ 434 435 /** @see RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */ 436 uint32_t halign; 437 438 /** @see RENDER_SURFACE_STATE.SurfaceVerticalAlignment */ 439 uint32_t valign; 440 /** @} */ 441 442 GLuint first_level; 443 GLuint last_level; 444 445 /** 446 * Level zero image dimensions. These dimensions correspond to the 447 * physical layout of data in memory. Accordingly, they account for the 448 * extra width, height, and or depth that must be allocated in order to 449 * accommodate multisample formats, and they account for the extra factor 450 * of 6 in depth that must be allocated in order to accommodate cubemap 451 * textures. 452 */ 453 GLuint physical_width0, physical_height0, physical_depth0; 454 455 /** Bytes per pixel (or bytes per block if compressed) */ 456 GLuint cpp; 457 458 /** 459 * @see RENDER_SURFACE_STATE.NumberOfMultisamples 460 * @see 3DSTATE_MULTISAMPLE.NumberOfMultisamples 461 */ 462 GLuint num_samples; 463 464 bool compressed; 465 466 /** 467 * @name Level zero image dimensions 468 * @{ 469 * 470 * These dimensions correspond to the 471 * logical width, height, and depth of the texture as seen by client code. 472 * Accordingly, they do not account for the extra width, height, and/or 473 * depth that must be allocated in order to accommodate multisample 474 * formats, nor do they account for the extra factor of 6 in depth that 475 * must be allocated in order to accommodate cubemap textures. 476 */ 477 478 /** 479 * @see RENDER_SURFACE_STATE.Width 480 * @see 3DSTATE_DEPTH_BUFFER.Width 481 */ 482 uint32_t logical_width0; 483 484 /** 485 * @see RENDER_SURFACE_STATE.Height 486 * @see 3DSTATE_DEPTH_BUFFER.Height 487 */ 488 uint32_t logical_height0; 489 490 /** 491 * @see RENDER_SURFACE_STATE.Depth 492 * @see 3DSTATE_DEPTH_BUFFER.Depth 493 */ 494 uint32_t logical_depth0; 495 /** @} */ 496 497 /** 498 * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE), 499 * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD). 500 */ 501 enum miptree_array_layout array_layout; 502 503 /** 504 * The distance in between array slices. 505 * 506 * The value is the one that is sent in the surface state. The actual 507 * meaning depends on certain criteria. Usually it is simply the number of 508 * uncompressed rows between each slice. However on Gen9+ for compressed 509 * surfaces it is the number of blocks. For 1D array surfaces that have the 510 * mipmap tree stored horizontally it is the number of pixels between each 511 * slice. 512 * 513 * @see RENDER_SURFACE_STATE.SurfaceQPitch 514 * @see 3DSTATE_DEPTH_BUFFER.SurfaceQPitch 515 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch 516 * @see 3DSTATE_STENCIL_BUFFER.SurfaceQPitch 517 */ 518 uint32_t qpitch; 519 520 /** 521 * MSAA layout used by this buffer. 522 * 523 * @see RENDER_SURFACE_STATE.MultisampledSurfaceStorageFormat 524 */ 525 enum intel_msaa_layout msaa_layout; 526 527 /* Derived from the above: 528 */ 529 GLuint total_width; 530 GLuint total_height; 531 532 /** 533 * The depth value used during the most recent fast depth clear performed 534 * on the surface. This field is invalid only if surface has never 535 * underwent a fast depth clear. 536 * 537 * @see 3DSTATE_CLEAR_PARAMS.DepthClearValue 538 */ 539 uint32_t depth_clear_value; 540 541 /* Includes image offset tables: */ 542 struct intel_mipmap_level level[MAX_TEXTURE_LEVELS]; 543 544 /** 545 * Offset into bo where the surface starts. 546 * 547 * @see intel_mipmap_tree::bo 548 * 549 * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress 550 * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress 551 * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress 552 * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress 553 */ 554 uint32_t offset; 555 556 /** 557 * \brief HiZ aux buffer 558 * 559 * To allocate the hiz buffer, use intel_miptree_alloc_hiz(). 560 * 561 * To determine if hiz is enabled, do not check this pointer. Instead, use 562 * intel_miptree_slice_has_hiz(). 563 */ 564 struct intel_miptree_hiz_buffer *hiz_buf; 565 566 /** 567 * \brief Maps of miptree slices to needed resolves. 568 * 569 * hiz_map is used only when the miptree has a child HiZ miptree. 570 * 571 * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is 572 * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c 573 * mt->hiz_mt->hiz_map, is unused. 574 * 575 * 576 * color_resolve_map is used only when the miptree uses fast clear (Gen7+) 577 * lossless compression (Gen9+). It should be noted that absence in the 578 * map means implicitly RESOLVED state. If item is found it always 579 * indicates state other than RESOLVED. 580 */ 581 struct exec_list hiz_map; /* List of intel_resolve_map. */ 582 struct exec_list color_resolve_map; /* List of intel_resolve_map. */ 583 584 /** 585 * \brief Stencil miptree for depthstencil textures. 586 * 587 * This miptree is used for depthstencil textures and renderbuffers that 588 * require separate stencil. It always has the true copy of the stencil 589 * bits, regardless of mt->format. 590 * 591 * \see 3DSTATE_STENCIL_BUFFER 592 * \see intel_miptree_map_depthstencil() 593 * \see intel_miptree_unmap_depthstencil() 594 */ 595 struct intel_mipmap_tree *stencil_mt; 596 597 /** 598 * \brief Stencil texturing miptree for sampling from a stencil texture 599 * 600 * Some hardware doesn't support sampling from the stencil texture as 601 * required by the GL_ARB_stencil_texturing extenion. To workaround this we 602 * blit the texture into a new texture that can be sampled. 603 * 604 * \see intel_update_r8stencil() 605 */ 606 struct intel_mipmap_tree *r8stencil_mt; 607 bool r8stencil_needs_update; 608 609 /** 610 * \brief MCS auxiliary buffer. 611 * 612 * This buffer contains the "multisample control surface", which stores 613 * the necessary information to implement compressed MSAA 614 * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+. 615 * 616 * NULL if no MCS buffer is in use for this surface. 617 */ 618 struct intel_miptree_aux_buffer *mcs_buf; 619 620 /** 621 * Planes 1 and 2 in case this is a planar surface. 622 */ 623 struct intel_mipmap_tree *plane[2]; 624 625 /** 626 * The SURFACE_STATE bits associated with the last fast color clear to this 627 * color mipmap tree, if any. 628 * 629 * Prior to GEN9 there is a single bit for RGBA clear values which gives you 630 * the option of 2^4 clear colors. Each bit determines if the color channel 631 * is fully saturated or unsaturated (Cherryview does add a 32b value per 632 * channel, but it is globally applied instead of being part of the render 633 * surface state). Starting with GEN9, the surface state accepts a 32b value 634 * for each color channel. 635 * 636 * @see RENDER_SURFACE_STATE.RedClearColor 637 * @see RENDER_SURFACE_STATE.GreenClearColor 638 * @see RENDER_SURFACE_STATE.BlueClearColor 639 * @see RENDER_SURFACE_STATE.AlphaClearColor 640 */ 641 union { 642 uint32_t fast_clear_color_value; 643 union gl_color_union gen9_fast_clear_color; 644 }; 645 646 /** 647 * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS 648 * buffer. This is useful for sharing the miptree bo with an external client 649 * that doesn't understand auxiliary buffers. 650 */ 651 enum intel_aux_disable aux_disable; 652 653 /** 654 * Tells if the underlying buffer is to be also consumed by entities other 655 * than the driver. This allows logic to turn off features such as lossless 656 * compression which is not currently understood by client applications. 657 */ 658 bool is_scanout; 659 660 /* These are also refcounted: 661 */ 662 GLuint refcount; 663 }; 664 665 bool 666 intel_miptree_is_lossless_compressed(const struct brw_context *brw, 667 const struct intel_mipmap_tree *mt); 668 669 bool 670 intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw, 671 unsigned tiling); 672 673 bool 674 intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw, 675 const struct intel_mipmap_tree *mt); 676 677 bool 678 intel_miptree_supports_lossless_compressed(struct brw_context *brw, 679 const struct intel_mipmap_tree *mt); 680 681 bool 682 intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, 683 struct intel_mipmap_tree *mt, 684 bool is_lossless_compressed); 685 686 enum { 687 MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0, 688 MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD = 1 << 1, 689 MIPTREE_LAYOUT_FOR_BO = 1 << 2, 690 MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3, 691 MIPTREE_LAYOUT_FORCE_HALIGN16 = 1 << 4, 692 693 MIPTREE_LAYOUT_TILING_Y = 1 << 5, 694 MIPTREE_LAYOUT_TILING_NONE = 1 << 6, 695 MIPTREE_LAYOUT_TILING_ANY = MIPTREE_LAYOUT_TILING_Y | 696 MIPTREE_LAYOUT_TILING_NONE, 697 698 MIPTREE_LAYOUT_FOR_SCANOUT = 1 << 7, 699 }; 700 701 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw, 702 GLenum target, 703 mesa_format format, 704 GLuint first_level, 705 GLuint last_level, 706 GLuint width0, 707 GLuint height0, 708 GLuint depth0, 709 GLuint num_samples, 710 uint32_t flags); 711 712 struct intel_mipmap_tree * 713 intel_miptree_create_for_bo(struct brw_context *brw, 714 drm_intel_bo *bo, 715 mesa_format format, 716 uint32_t offset, 717 uint32_t width, 718 uint32_t height, 719 uint32_t depth, 720 int pitch, 721 uint32_t layout_flags); 722 723 void 724 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel, 725 struct intel_renderbuffer *irb, 726 drm_intel_bo *bo, 727 uint32_t width, uint32_t height, 728 uint32_t pitch); 729 730 /** 731 * Create a miptree appropriate as the storage for a non-texture renderbuffer. 732 * The miptree has the following properties: 733 * - The target is GL_TEXTURE_2D. 734 * - There are no levels other than the base level 0. 735 * - Depth is 1. 736 */ 737 struct intel_mipmap_tree* 738 intel_miptree_create_for_renderbuffer(struct brw_context *brw, 739 mesa_format format, 740 uint32_t width, 741 uint32_t height, 742 uint32_t num_samples); 743 744 mesa_format 745 intel_depth_format_for_depthstencil_format(mesa_format format); 746 747 mesa_format 748 intel_lower_compressed_format(struct brw_context *brw, mesa_format format); 749 750 /** \brief Assert that the level and layer are valid for the miptree. */ 751 static inline void 752 intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt, 753 uint32_t level, 754 uint32_t layer) 755 { 756 (void) mt; 757 (void) level; 758 (void) layer; 759 760 assert(level >= mt->first_level); 761 assert(level <= mt->last_level); 762 assert(layer < mt->level[level].depth); 763 } 764 765 void intel_miptree_reference(struct intel_mipmap_tree **dst, 766 struct intel_mipmap_tree *src); 767 768 void intel_miptree_release(struct intel_mipmap_tree **mt); 769 770 /* Check if an image fits an existing mipmap tree layout 771 */ 772 bool intel_miptree_match_image(struct intel_mipmap_tree *mt, 773 struct gl_texture_image *image); 774 775 void 776 intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt, 777 GLuint level, GLuint slice, 778 GLuint *x, GLuint *y); 779 780 enum isl_surf_dim 781 get_isl_surf_dim(GLenum target); 782 783 enum isl_dim_layout 784 get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling, 785 GLenum target); 786 787 enum isl_tiling 788 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt); 789 790 void 791 intel_miptree_get_isl_surf(struct brw_context *brw, 792 const struct intel_mipmap_tree *mt, 793 struct isl_surf *surf); 794 void 795 intel_miptree_get_aux_isl_surf(struct brw_context *brw, 796 const struct intel_mipmap_tree *mt, 797 struct isl_surf *surf, 798 enum isl_aux_usage *usage); 799 800 union isl_color_value 801 intel_miptree_get_isl_clear_color(struct brw_context *brw, 802 const struct intel_mipmap_tree *mt); 803 804 void 805 intel_get_image_dims(struct gl_texture_image *image, 806 int *width, int *height, int *depth); 807 808 void 809 intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp, 810 uint32_t *mask_x, uint32_t *mask_y); 811 812 void 813 intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp, 814 uint32_t *tile_w, uint32_t *tile_h); 815 816 uint32_t 817 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt, 818 GLuint level, GLuint slice, 819 uint32_t *tile_x, 820 uint32_t *tile_y); 821 uint32_t 822 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt, 823 uint32_t x, uint32_t y); 824 825 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt, 826 GLuint level, 827 GLuint x, GLuint y, GLuint d); 828 829 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt, 830 GLuint level, 831 GLuint img, GLuint x, GLuint y); 832 833 void 834 intel_miptree_copy_teximage(struct brw_context *brw, 835 struct intel_texture_image *intelImage, 836 struct intel_mipmap_tree *dst_mt, bool invalidate); 837 838 /** 839 * \name Miptree HiZ functions 840 * \{ 841 * 842 * It is safe to call the "slice_set_need_resolve" and "slice_resolve" 843 * functions on a miptree without HiZ. In that case, each function is a no-op. 844 */ 845 846 bool 847 intel_miptree_wants_hiz_buffer(struct brw_context *brw, 848 struct intel_mipmap_tree *mt); 849 850 /** 851 * \brief Allocate the miptree's embedded HiZ miptree. 852 * \see intel_mipmap_tree:hiz_mt 853 * \return false if allocation failed 854 */ 855 bool 856 intel_miptree_alloc_hiz(struct brw_context *brw, 857 struct intel_mipmap_tree *mt); 858 859 bool 860 intel_miptree_level_has_hiz(struct intel_mipmap_tree *mt, uint32_t level); 861 862 void 863 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt, 864 uint32_t level, 865 uint32_t depth); 866 void 867 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt, 868 uint32_t level, 869 uint32_t depth); 870 871 void 872 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt, 873 uint32_t level); 874 875 /** 876 * \return false if no resolve was needed 877 */ 878 bool 879 intel_miptree_slice_resolve_hiz(struct brw_context *brw, 880 struct intel_mipmap_tree *mt, 881 unsigned int level, 882 unsigned int depth); 883 884 /** 885 * \return false if no resolve was needed 886 */ 887 bool 888 intel_miptree_slice_resolve_depth(struct brw_context *brw, 889 struct intel_mipmap_tree *mt, 890 unsigned int level, 891 unsigned int depth); 892 893 /** 894 * \return false if no resolve was needed 895 */ 896 bool 897 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw, 898 struct intel_mipmap_tree *mt); 899 900 /** 901 * \return false if no resolve was needed 902 */ 903 bool 904 intel_miptree_all_slices_resolve_depth(struct brw_context *brw, 905 struct intel_mipmap_tree *mt); 906 907 /**\}*/ 908 909 enum intel_fast_clear_state 910 intel_miptree_get_fast_clear_state(const struct intel_mipmap_tree *mt, 911 unsigned level, unsigned layer); 912 913 void 914 intel_miptree_set_fast_clear_state(const struct brw_context *brw, 915 struct intel_mipmap_tree *mt, 916 unsigned level, 917 unsigned first_layer, 918 unsigned num_layers, 919 enum intel_fast_clear_state new_state); 920 921 bool 922 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt, 923 unsigned start_level, unsigned num_levels, 924 unsigned start_layer, unsigned num_layers); 925 926 /** 927 * Update the fast clear state for a miptree to indicate that it has been used 928 * for rendering. 929 */ 930 void 931 intel_miptree_used_for_rendering(const struct brw_context *brw, 932 struct intel_mipmap_tree *mt, unsigned level, 933 unsigned start_layer, unsigned num_layers); 934 935 /** 936 * Flag values telling color resolve pass which special types of buffers 937 * can be ignored. 938 * 939 * INTEL_MIPTREE_IGNORE_CCS_E: Lossless compressed (single-sample 940 * compression scheme since gen9) 941 */ 942 #define INTEL_MIPTREE_IGNORE_CCS_E (1 << 0) 943 944 bool 945 intel_miptree_resolve_color(struct brw_context *brw, 946 struct intel_mipmap_tree *mt, unsigned level, 947 unsigned start_layer, unsigned num_layers, 948 int flags); 949 950 void 951 intel_miptree_all_slices_resolve_color(struct brw_context *brw, 952 struct intel_mipmap_tree *mt, 953 int flags); 954 955 void 956 intel_miptree_make_shareable(struct brw_context *brw, 957 struct intel_mipmap_tree *mt); 958 959 void 960 intel_miptree_updownsample(struct brw_context *brw, 961 struct intel_mipmap_tree *src, 962 struct intel_mipmap_tree *dst); 963 964 void 965 intel_update_r8stencil(struct brw_context *brw, 966 struct intel_mipmap_tree *mt); 967 968 /** 969 * Horizontal distance from one slice to the next in the two-dimensional 970 * miptree layout. 971 */ 972 unsigned 973 brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw, 974 const struct intel_mipmap_tree *mt, 975 unsigned level); 976 977 /** 978 * Vertical distance from one slice to the next in the two-dimensional miptree 979 * layout. 980 */ 981 unsigned 982 brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw, 983 const struct intel_mipmap_tree *mt, 984 unsigned level); 985 986 void 987 brw_miptree_layout(struct brw_context *brw, 988 struct intel_mipmap_tree *mt, 989 uint32_t layout_flags); 990 991 void 992 intel_miptree_map(struct brw_context *brw, 993 struct intel_mipmap_tree *mt, 994 unsigned int level, 995 unsigned int slice, 996 unsigned int x, 997 unsigned int y, 998 unsigned int w, 999 unsigned int h, 1000 GLbitfield mode, 1001 void **out_ptr, 1002 ptrdiff_t *out_stride); 1003 1004 void 1005 intel_miptree_unmap(struct brw_context *brw, 1006 struct intel_mipmap_tree *mt, 1007 unsigned int level, 1008 unsigned int slice); 1009 1010 void 1011 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, 1012 unsigned int level, unsigned int layer, enum blorp_hiz_op op); 1013 1014 bool 1015 intel_miptree_sample_with_hiz(struct brw_context *brw, 1016 struct intel_mipmap_tree *mt); 1017 1018 #ifdef __cplusplus 1019 } 1020 #endif 1021 1022 #endif 1023
