| /device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/ |
| hikey960_bl1_setup.c | 153 mmio_write_32(0xfff350b4, 0xf0002000);
155 mmio_write_32(0xfff350bc, 0xfc004c00);
167 mmio_write_32(PMC_PPLL3_CTRL0_REG, 0x4904305);
168 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x2300000);
169 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x6300000);
179 mmio_write_32(PMC_NOC_POWER_IDLEREQ_REG, pmc_value);
198 mmio_write_32(CRG_CLKDIV20_REG, 0x00020002);
199 mmio_write_32(CRG_PEREN0_REG, 0x00001000);
205 mmio_write_32(CRG_CLKDIV5_REG, 0x003f000b);
207 mmio_write_32(CRG_CLKDIV3_REG, 0xf0001000)
[all...] |
| hikey960_boardid.c | 50 mmio_write_32(CRG_PERRSTEN2_REG, PERRSTEN2_HKADCSSI);
53 mmio_write_32(CRG_PERRSTDIS2_REG, PERRSTEN2_HKADCSSI);
56 mmio_write_32(CRG_PERDIS2_REG, PEREN2_HKADCSSI);
58 mmio_write_32(CRG_PEREN2_REG, PEREN2_HKADCSSI);
71 mmio_write_32(HKADC_WR01_DATA_REG, HKADC_WR01_VALUE | channel);
72 mmio_write_32(HKADC_WR23_DATA_REG, HKADC_WR23_VALUE);
73 mmio_write_32(HKADC_WR45_DATA_REG, HKADC_WR45_VALUE);
75 mmio_write_32(HKADC_WR_NUM_REG, HKADC_WR_NUM_VALUE);
77 mmio_write_32(HKADC_DELAY01_REG, HKADC_CHANNEL0_DELAY01_VALUE);
78 mmio_write_32(HKADC_DELAY23_REG, HKADC_DELAY23_VALUE)
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/soc/common/ |
| soc_css_security.c | 28 mmio_write_32(SOC_CSS_NIC400_BASE +
30 mmio_write_32(SOC_CSS_NIC400_BASE +
32 mmio_write_32(SOC_CSS_NIC400_BASE +
34 mmio_write_32(SOC_CSS_NIC400_BASE +
36 mmio_write_32(SOC_CSS_NIC400_BASE +
38 mmio_write_32(SOC_CSS_NIC400_BASE +
65 mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG,
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/secure/ |
| secure.c | 19 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
23 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
69 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn),
73 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn + 8),
76 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
87 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3),
99 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3),
106 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
107 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff);
109 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0)
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/ |
| spm.c | 94 mmio_write_32(SPM_POWERON_CONFIG_SET, SPM_REGWR_CFG_KEY | SPM_REGWR_EN);
96 mmio_write_32(SPM_POWER_ON_VAL0, 0);
97 mmio_write_32(SPM_POWER_ON_VAL1, POWER_ON_VAL1_DEF);
98 mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
100 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET);
101 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY);
105 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS);
106 mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_EVENT_LOCK_EN |
108 mmio_write_32(SPM_PCM_IM_PTR, 0);
109 mmio_write_32(SPM_PCM_IM_LEN, 0)
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/ |
| hikey_ddr.c | 26 mmio_write_32((0xf7032000 + 0x000), data);
35 mmio_write_32((0xf7800000 + 0x000), data);
42 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2101);
44 mmio_write_32(0xf7032000 + 0x02c, 0x5110103e);
47 mmio_write_32(0xf7032000 + 0x050, data);
48 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2101);
59 mmio_write_32((0xf7032000 + 0x374), 0x4a);
60 mmio_write_32((0xf7032000 + 0x368), 0xda);
61 mmio_write_32((0xf7032000 + 0x36c), 0x01);
62 mmio_write_32((0xf7032000 + 0x370), 0x01)
[all...] |
| hisi_pwrc.c | 46 mmio_write_32(ACPU_SC_SNOOP_PWD, reg);
50 mmio_write_32(ACPU_SC_SNOOP_PWD, reg);
62 mmio_write_32(ACPU_SC_PDBGUP_MBIST, val | enable);
76 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(0), sec_entrypoint >> 2);
77 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(1), sec_entrypoint >> 2);
78 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(2), sec_entrypoint >> 2);
79 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(3), sec_entrypoint >> 2);
80 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(4), sec_entrypoint >> 2);
81 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(5), sec_entrypoint >> 2);
82 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(6), sec_entrypoint >> 2)
[all...] |
| hikey_bl2_setup.c | 368 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0);
373 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0);
378 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0);
383 mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
388 mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
394 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0);
405 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr);
409 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0);
410 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b);
412 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234)
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/ |
| m0_ctl.c | 21 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7));
22 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12));
25 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3),
28 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7),
43 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0,
46 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5));
52 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
56 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0);
59 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
64 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0
[all...] |
| pmu.c | 476 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
480 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 0);
491 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
513 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
524 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
556 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3),
569 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3),
686 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
710 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE);
779 mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_32K_CNT_MS(30))
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/ |
| dram.c | 19 mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, 0x3fffffff);
38 mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, gatedis_con0);
43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE));
45 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1));
46 mmio_write_32(CRU_BASE + CRU_DPLL_CON0,
48 mmio_write_32(CRU_BASE + CRU_DPLL_CON1,
50 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0));
55 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE));
64 mmio_write_32(CIC_BASE + CIC_CTRL0,
72 mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002)
[all...] |
| main.c | 23 mmio_write_32(PARAM_ADDR + PARAM_M0_DONE, M0_DONE_FLAG);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/board/fvp/drivers/pwrc/ |
| fvp_pwrc.c | 29 mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
38 mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr);
45 mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr);
52 mmio_write_32(PWRC_BASE + PWKUPR_OFF,
60 mmio_write_32(PWRC_BASE + PWKUPR_OFF,
68 mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/board/juno/ |
| juno_security.c | 24 mmio_write_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET, reg);
33 mmio_write_32(PLAT_SOC_CSS_NIC400_BASE +
45 mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_SET,
49 mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR,
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/ |
| soc.c | 60 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT0, 0xffffffff);
61 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT1, 0xffffffff);
64 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN);
70 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON_NS);
71 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SOC_CON7_BITS);
72 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SOC_CON_NS);
75 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(0), SGRF_BUSDMAC_CON0_NS);
76 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(1), SGRF_BUSDMAC_CON1_NS);
80 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1),
83 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4)
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3328/drivers/soc/ |
| soc.c | 86 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT0, 0xffffffff);
87 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT1, 0xffffffff);
89 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN);
105 mmio_write_32(FIREWALL_DDR_BASE +
108 mmio_write_32(FIREWALL_DDR_BASE +
114 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0);
117 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(0),
119 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(1),
121 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(2),
123 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(3)
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/ |
| pmu.c | 60 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
65 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
76 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
95 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
103 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
176 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE);
185 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE);
192 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID));
193 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID));
194 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID))
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/drivers/arm/sp804/ |
| sp804_delay_timer.c | 48 mmio_write_32(SP804_TIMER1_CONTROL, 0);
49 mmio_write_32(SP804_TIMER1_LOAD, UINT32_MAX);
50 mmio_write_32(SP804_TIMER1_VALUE, UINT32_MAX);
53 mmio_write_32(SP804_TIMER1_CONTROL,
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/include/ |
| rk3399_mcu.h | 16 #define mmio_write_32(c, v) ((*(volatile unsigned int *)(c)) = (v)) macro
19 mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)))
21 mmio_write_32(addr, (mmio_read_32(addr)) | (set))
23 mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/ |
| soc.c | 49 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE);
51 mmio_write_32((CRU_BASE +
58 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE);
60 mmio_write_32(CRU_BASE +
67 mmio_write_32(PMUCRU_BASE +
70 mmio_write_32(CRU_BASE +
119 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE);
121 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK);
122 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK);
123 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2])
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/ |
| plat_secondary.c | 32 mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW,
35 mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pwm/ |
| pwm.c | 40 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val);
49 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val);
58 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val);
67 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val);
77 mmio_write_32(PWM_BASE + PWM_CTRL(i), val & ~PWM_ENABLE);
92 mmio_write_32(PWM_BASE + PWM_CTRL(i), val | PWM_ENABLE);
100 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val);
107 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val);
114 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val);
121 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val)
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/drivers/synopsys/emmc/ |
| dw_mmc.c | 141 mmio_write_32(dw_params.reg_base + DWMMC_CMD,
173 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 0);
176 mmio_write_32(dw_params.reg_base + DWMMC_CLKDIV, div);
180 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 1);
181 mmio_write_32(dw_params.reg_base + DWMMC_CLKSRC, 0);
193 mmio_write_32(base + DWMMC_PWREN, 1);
194 mmio_write_32(base + DWMMC_CTRL, CTRL_RESET_ALL);
201 mmio_write_32(base + DWMMC_CTRL, data);
202 mmio_write_32(base + DWMMC_RINTSTS, ~0);
203 mmio_write_32(base + DWMMC_INTMASK, 0)
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/gpio/ |
| rk3399_gpio.c | 76 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
84 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
92 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
100 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
108 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
126 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
131 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
136 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
141 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
147 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31)
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/drivers/arm/sp805/ |
| sp805.c | 15 mmio_write_32(base + SP805_WDOG_LOAD_OFF, value);
20 mmio_write_32(base + SP805_WDOG_CTR_OFF, value);
25 mmio_write_32(base + SP805_WDOG_LOCK_OFF, value);
|
