| /external/clang/test/CodeGen/ |
| mips-vector-arg.c | 9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
24 extern test_v4i32_2(v4i32, int, v4i32);
25 void test_v4i32(v4i32 a1, int a2, v4i32 a3) {
|
| mips-inline-asm-modifiers.c | 8 typedef int v4i32 __attribute__((vector_size(16))); typedef
17 v4i32 v4i32_r;
|
| mips-vector-return.c | 9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
28 v4i32 test_v4i32(int a) {
29 return (v4i32){0, a, 0, 0};
|
| compound-literal.c | 6 typedef int v4i32 __attribute((vector_size(16))); typedef
7 v4i32 *y = &(v4i32){1,2,3,4};
|
| mips-varargs.c | 10 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
130 v4i32 v = va_arg(va, v4i32);
|
| /external/gemmlowp/fixedpoint/ |
| fixedpoint_msa.h | 26 struct FixedPointRawTypeTraits<v4i32> {
38 inline v4i32 BitAnd(v4i32 a, v4i32 b) {
39 return reinterpret_cast<v4i32>(__builtin_msa_and_v(reinterpret_cast<v16u8>(a),
50 inline v4i32 BitOr(v4i32 a, v4i32 b) {
51 return reinterpret_cast<v4i32>(__builtin_msa_or_v(reinterpret_cast<v16u8>(a),
62 inline v4i32 BitXor(v4i32 a, v4i32 b)
[all...] |
| /prebuilts/gcc/darwin-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9.x/include/ |
| msa.h | 39 typedef int v4i32 __attribute__((vector_size(16), aligned(16))); typedef
55 extern v4i32 __builtin_msa_sll_w(v4i32, v4i32);
59 extern v4i32 __builtin_msa_slli_w(v4i32, unsigned char);
63 extern v4i32 __builtin_msa_sra_w(v4i32, v4i32);
67 extern v4i32 __builtin_msa_srai_w(v4i32, unsigned char)
[all...] |
| /prebuilts/gcc/linux-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9.x/include/ |
| msa.h | 39 typedef int v4i32 __attribute__((vector_size(16), aligned(16))); typedef
55 extern v4i32 __builtin_msa_sll_w(v4i32, v4i32);
59 extern v4i32 __builtin_msa_slli_w(v4i32, unsigned char);
63 extern v4i32 __builtin_msa_sra_w(v4i32, v4i32);
67 extern v4i32 __builtin_msa_srai_w(v4i32, unsigned char)
[all...] |
| /external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/useful-harnesses/ |
| vecoperations.c | 5 typedef int v4i32 __attribute__((ext_vector_type(4))); typedef
50 void print_v4i32(const char *str, v4i32 v) {
76 v4i32 v4i32_shuffle_1(v4i32 a) {
77 v4i32 c2 = a.yzwx;
81 v4i32 v4i32_shuffle_2(v4i32 a) {
82 v4i32 c2 = a.zwxy;
86 v4i32 v4i32_shuffle_3(v4i32 a)
[all...] |
| /external/libyuv/files/source/ |
| rotate_msa.cc | 40 out0 = (v16u8)__msa_ilvr_w((v4i32)in1, (v4i32)in0); \
41 out1 = (v16u8)__msa_ilvl_w((v4i32)in1, (v4i32)in0); \
42 out2 = (v16u8)__msa_ilvr_w((v4i32)in3, (v4i32)in2); \
43 out3 = (v16u8)__msa_ilvl_w((v4i32)in3, (v4i32)in2); \
132 res8 = (v16u8)__msa_ilvr_w((v4i32)reg4, (v4i32)reg0)
[all...] |
| scale_msa.cc | 35 dst0 = (v16u8)__msa_pckod_w((v4i32)src1, (v4i32)src0);
53 vec0 = (v16u8)__msa_pckev_w((v4i32)src1, (v4i32)src0);
54 vec1 = (v16u8)__msa_pckod_w((v4i32)src1, (v4i32)src0);
335 reg0 = (v4u32)__msa_srari_w((v4i32)reg0, 4);
336 reg1 = (v4u32)__msa_srari_w((v4i32)reg1, 4);
337 reg2 = (v4u32)__msa_srari_w((v4i32)reg2, 4);
338 reg3 = (v4u32)__msa_srari_w((v4i32)reg3, 4)
[all...] |
| /external/webp/src/dsp/ |
| msa_macro.h | 27 #define ADDVI_W(a, b) __msa_addvi_w((v4i32)a, b)
30 #define SRAI_W(a, b) __msa_srai_w((v4i32)a, b)
32 #define SLLI_B(a, b) __msa_slli_b((v4i32)a, b)
58 #define LD_SW(...) LD_W(v4i32, __VA_ARGS__)
70 #define ST_SW(...) ST_W(v4i32, __VA_ARGS__)
275 #define LD_SW2(...) LD_W2(v4i32, __VA_ARGS__)
282 #define LD_SW3(...) LD_W3(v4i32, __VA_ARGS__)
289 #define LD_SW4(...) LD_W4(v4i32, __VA_ARGS__)
329 #define ST_SW2(...) ST_W2(v4i32, __VA_ARGS__)
336 #define ST_SW3(...) ST_W3(v4i32, __VA_ARGS__
[all...] |
| lossless_enc_msa.c | 23 v4i32 t4, t5; \
29 t4 = __msa_srli_w((v4i32)src0, 16); \
30 t5 = __msa_srli_w((v4i32)src1, 16); \
41 v4i32 t2; \
44 t2 = __msa_srli_w((v4i32)src, 16); \
83 const uint32_t pix_w = __msa_copy_s_w((v4i32)dst0, 2);
90 const uint32_t pix_w = __msa_copy_s_w((v4i32)dst0, 0);
|
| lossless_msa.c | 40 pix_w = __msa_copy_s_w((v4i32)dst2, 0); \
58 uint32_t pix_w = __msa_copy_s_w((v4i32)dst0, 2); \
84 v4i32 t4, t5; \
90 t4 = __msa_srli_w((v4i32)t0, 16); \
91 t5 = __msa_srli_w((v4i32)t1, 16); \
102 v4i32 t2; \
105 t2 = __msa_srli_w((v4i32)t0, 16); \
324 const uint32_t pix_w = __msa_copy_s_w((v4i32)dst0, 2);
331 const uint32_t pix_w = __msa_copy_s_w((v4i32)dst0, 0);
|
| /external/llvm/lib/Target/AMDGPU/ |
| SITypeRewriter.cpp | 39 Type *v4i32; member in class:__anon27588::SITypeRewriter
60 v4i32 = VectorType::get(Type::getInt32Ty(M.getContext()), 4);
81 PointerType::get(v4i32,PtrTy->getPointerAddressSpace()));
108 Args.push_back(Builder.CreateBitCast(Arg, v4i32));
109 Types.push_back(v4i32);
111 Name = Name + ".v4i32";
144 if (I.getDestTy() != v4i32) {
149 if (Op->getSrcTy() == v4i32) {
|
| /external/libvpx/libvpx/vp8/encoder/mips/msa/ |
| dct_msa.c | 48 v4i32 tmp0_m; \
49 v4i32 one_m = __msa_ldi_w(1); \
60 v4i32 tmp0_m; \
62 v4i32 one_m = __msa_ldi_w(1); \
74 v4i32 out0, out1, out2, out3;
87 out0 = (v4i32)__msa_ilvev_h(zero, in1);
89 out1 = __msa_splati_w((v4i32)coeff, 0);
106 out1 = __msa_splati_w((v4i32)coeff, 1);
110 out1 += (v4i32)temp1;
121 v4i32 vec0_w, vec1_w, vec2_w, vec3_w
[all...] |
| encodeopt_msa.c | 19 v4i32 diff0, diff1;
49 v4i32 diff0, diff1;
55 mask0 = (v16u8)__msa_insve_w((v4i32)mask0, 0, (v4i32)zero);
81 diff0 = (v4i32)__msa_bmnz_v(zero, (v16u8)diff0, mask0);
93 diff0 = (v4i32)__msa_bmnz_v(zero, (v16u8)diff0, mask0);
115 v4i32 diff0, diff1;
|
| /external/gemmlowp/internal/ |
| output_msa.h | 40 v4i32 tmp = __builtin_msa_sat_s_w(input.reg[0], 8);
42 tmp = reinterpret_cast<v4i32>(__builtin_msa_pckev_h(
51 tmp = reinterpret_cast<v4i32>(__builtin_msa_pckev_b(
73 v4i32 tmp_lo = __builtin_msa_sat_s_w(input.reg[0], 8);
74 v4i32 tmp_hi = __builtin_msa_sat_s_w(input.reg[1], 8);
77 tmp_lo = reinterpret_cast<v4i32>(__builtin_msa_pckev_h(
86 tmp_lo = reinterpret_cast<v4i32>(__builtin_msa_pckev_b(
97 v4i32 tmp0 = __builtin_msa_sat_s_w(in0, 8); \
98 v4i32 tmp1 = __builtin_msa_sat_s_w(in1, 8); \
99 v4i32 tmp2 = __builtin_msa_sat_s_w(in2, 8);
[all...] |
| pack_msa.h | 155 v4i32 sums_of_4_cells[kCells][4];
158 v4i32 tmp0 = reinterpret_cast<v4i32>(__builtin_msa_ilvr_h(
160 v4i32 tmp1 = reinterpret_cast<v4i32>(__builtin_msa_ilvl_h(
167 v4i32 s01 = __builtin_msa_addv_w(sums_of_4_cells[cell][0],
169 v4i32 s23 = __builtin_msa_addv_w(sums_of_4_cells[cell][2],
171 v4i32 s = __builtin_msa_addv_w(s01, s23);
174 v4i32 tmp = __builtin_msa_ld_w(sums_of_each_slice_ptr, 0);
330 v4i32 sums_of_16[kCells]
[all...] |
| /external/libvpx/libvpx/vpx_dsp/mips/ |
| macros_msa.h | 24 #define LD_SW(...) LD_V(v4i32, __VA_ARGS__)
30 #define ST_SW(...) ST_V(v4i32, __VA_ARGS__)
243 #define LD_SW2(...) LD_V2(v4i32, __VA_ARGS__)
321 #define ST_SW2(...) ST_V2(v4i32, __VA_ARGS__)
378 out0_m = __msa_copy_u_w((v4i32)in, 0); \
379 out1_m = __msa_copy_u_w((v4i32)in, 1); \
401 out0_m = __msa_copy_u_w((v4i32)in0, idx0); \
402 out1_m = __msa_copy_u_w((v4i32)in0, idx1); \
403 out2_m = __msa_copy_u_w((v4i32)in1, idx2); \
404 out3_m = __msa_copy_u_w((v4i32)in1, idx3);
[all...] |
| txfm_macros_msa.h | 18 v4i32 s0_m, s1_m, s2_m, s3_m, s4_m, s5_m; \
43 v4i32 tp0_m, tp1_m, tp2_m, tp3_m, tp4_m; \
44 v4i32 tp5_m, tp6_m, tp7_m, tp8_m, tp9_m; \
61 v4i32 tp0_m, tp1_m; \
72 v4i32 madd0_m, madd1_m, madd2_m, madd3_m; \
86 v4i32 tmp0_m, tmp1_m, tmp2_m, tmp3_m, m4_m, m5_m; \
|
| intrapred_msa.c | 168 sum_w = (v4u32)__msa_srari_w((v4i32)sum_d, 3);
170 val0 = __msa_copy_u_w((v4i32)store, 0);
183 data = (v16i8)__msa_insert_w((v4i32)data, 0, val0);
186 sum_w = (v4u32)__msa_srari_w((v4i32)sum_w, 2);
188 val0 = __msa_copy_u_w((v4i32)store, 0);
197 out = __msa_copy_u_w((v4i32)store, 0);
218 sum_w = (v4u32)__msa_pckev_w((v4i32)sum_d, (v4i32)sum_d);
220 sum_w = (v4u32)__msa_srari_w((v4i32)sum_d, 4);
243 sum_w = (v4u32)__msa_srari_w((v4i32)sum_d, 3)
[all...] |
| fwd_txfm_msa.h | 21 v4i32 vec4_m, vec5_m, vec6_m, vec7_m; \
298 v4i32 temp_m; \
299 v4i32 one_m = __msa_ldi_w(1); \
330 v4i32 s0_m, s1_m, s2_m, s3_m, s4_m, s5_m, s6_m, s7_m; \
332 v4i32 k0_m = __msa_fill_w((int32_t)const0); \
348 out0 = __msa_pckev_w((v4i32)tp0_m, (v4i32)tp1_m); \
349 out1 = __msa_pckev_w((v4i32)tp2_m, (v4i32)tp3_m); \
357 out2 = __msa_pckev_w((v4i32)tp0_m, (v4i32)tp1_m);
[all...] |
| /external/libvpx/libvpx/vp8/common/mips/msa/ |
| vp8_macros_msa.h | 29 #define LD_SW(...) LD_W(v4i32, __VA_ARGS__)
40 #define ST_SW(...) ST_W(v4i32, __VA_ARGS__)
433 out0_m = __msa_copy_u_w((v4i32)in0, idx0); \
434 out1_m = __msa_copy_u_w((v4i32)in0, idx1); \
435 out2_m = __msa_copy_u_w((v4i32)in1, idx2); \
436 out3_m = __msa_copy_u_w((v4i32)in1, idx3); \
652 #define DOTP_SH4_SW(...) DOTP_SH4(v4i32, __VA_ARGS__)
666 out0 = (RTYPE)__msa_dotp_s_d((v4i32)mult0, (v4i32)cnst0); \
667 out1 = (RTYPE)__msa_dotp_s_d((v4i32)mult1, (v4i32)cnst1);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 151 { ISD::SHL, MVT::v4i32, 1 },
152 { ISD::SRL, MVT::v4i32, 1 },
153 { ISD::SRA, MVT::v4i32, 1 },
184 { ISD::SHL, MVT::v4i32, 1 },
185 { ISD::SRL, MVT::v4i32, 2 },
186 { ISD::SRA, MVT::v4i32, 2 },
250 { ISD::SHL, MVT::v4i32, 1 }, // pslld
259 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
268 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
275 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequenc
[all...] |
