| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4.h | 159 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
164 bool is_supported_64bit_region(vec4_instruction *inst, unsigned arg);
169 vec4_instruction *inst, int arg);
171 vec4_instruction *emit(vec4_instruction *inst);
173 vec4_instruction *emit(enum opcode opcode);
174 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
175 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
177 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
179 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst
[all...] |
| brw_vec4_tes.h | 59 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
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| brw_vec4_cse.cpp | 41 vec4_instruction *generator;
49 is_expression(const vec4_instruction *const inst)
98 operands_match(const vec4_instruction *a, const vec4_instruction *b)
116 instructions_match(vec4_instruction *a, vec4_instruction *b)
147 foreach_inst_in_block (vec4_instruction, inst, block) {
191 vec4_instruction *copy =
212 vec4_instruction *copy =
226 vec4_instruction *prev = (vec4_instruction *)inst->prev
[all...] |
| brw_vec4_visitor.cpp | 31 vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst, function in class:brw::vec4_instruction
64 vec4_instruction *
65 vec4_visitor::emit(vec4_instruction *inst)
75 vec4_instruction *
76 vec4_visitor::emit_before(bblock_t *block, vec4_instruction *inst,
77 vec4_instruction *new_inst)
87 vec4_instruction *
91 return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0, src1, src2));
95 vec4_instruction *
[all...] |
| brw_ir_vec4.h | 266 class vec4_instruction : public backend_instruction { class in namespace:brw
268 DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
270 vec4_instruction(enum opcode opcode,
339 inline vec4_instruction *
341 vec4_instruction *inst)
351 inline vec4_instruction *
352 set_predicate(enum brw_predicate pred, vec4_instruction *inst)
361 inline vec4_instruction *
362 set_condmod(enum brw_conditional_mod mod, vec4_instruction *inst)
372 inline vec4_instruction *
[all...] |
| brw_vec4_gs_visitor.h | 59 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
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| brw_vec4_tcs.h | 77 virtual vec4_instruction *emit_urb_write_opcode(bool complete) { return NULL; }
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| brw_vs.h | 91 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
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| test_vec4_register_coalesce.cpp | 86 virtual vec4_instruction *emit_urb_write_opcode(bool complete)
138 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
162 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
185 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2));
203 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2));
229 vec4_instruction *mul = v->emit(v->MUL(temp, some_src_1, some_src_2));
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| brw_vec4.cpp | 148 vec4_instruction::is_send_from_grf()
189 vec4_instruction::has_source_and_destination_hazard() const
208 vec4_instruction::size_read(unsigned arg) const
243 vec4_instruction::can_do_source_mods(const struct gen_device_info *devinfo)
258 vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo)
293 vec4_instruction::can_change_types() const
312 vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
385 vec4_instruction *imm_inst[4];
389 foreach_inst_in_block_safe(vec4_instruction, inst, block) {
428 vec4_instruction *mov = MOV(imm_inst[0]->dst, brw_imm_vf(vf))
[all...] |
| brw_vec4_reg_allocate.cpp | 55 foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
75 foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
227 foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
269 foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
303 can_use_scratch_for_source(const vec4_instruction *inst, unsigned i,
316 for (vec4_instruction *prev_inst = (vec4_instruction *) inst->prev;
318 prev_inst = (vec4_instruction *) prev_inst->prev) {
399 foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
525 foreach_block_and_inst(block, vec4_instruction, inst, cfg)
[all...] |
| brw_vec4_tes.cpp | 80 foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
142 vec4_instruction *
151 vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE);
234 vec4_instruction *read =
255 vec4_instruction *read =
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| brw_vec4_vs_visitor.cpp | 86 vec4_instruction *
95 vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE);
118 vec4_instruction *inst = emit_generic_urb_slot(reg, varying, 0);
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| test_vec4_copy_propagation.cpp | 83 virtual vec4_instruction *emit_urb_write_opcode(bool complete)
138 vec4_instruction *test_mov =
167 vec4_instruction *test_mov =
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| brw_vec4_cmod_propagation.cpp | 44 foreach_inst_in_block_reverse_safe(vec4_instruction, inst, block) {
70 foreach_inst_in_block_reverse_starting_from(vec4_instruction, scan_inst, inst) {
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| brw_vec4_gs_visitor.cpp | 159 vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, brw_imm_ud(0u));
217 vec4_instruction *last = (vec4_instruction *) instructions.get_tail();
228 vec4_instruction *inst = emit(MOV(mrf_reg, r0));
254 vec4_instruction *inst = emit(MOV(mrf_reg, r0));
261 vec4_instruction *
270 vec4_instruction *inst = emit(GS_OPCODE_URB_WRITE);
351 vec4_instruction *inst = emit(MOV(mrf_reg, r0));
487 vec4_instruction *inst =
[all...] |
| gen6_gs_visitor.cpp | 74 vec4_instruction *inst = emit(MOV(dst_reg(MRF, 1),
169 vec4_instruction *inst = emit(MOV(dst, src_reg(tmp)));
225 vec4_instruction *inst = emit(CMP(dst_null_ud(),
293 vec4_instruction *inst = NULL;
358 vec4_instruction *inst;
417 vec4_instruction *inst = emit(MOV(reg, data));
479 vec4_instruction *inst = emit(GS_OPCODE_THREAD_END);
614 vec4_instruction *inst = emit(MOV(dst_reg(destination_indices),
668 vec4_instruction *inst = emit(GS_OPCODE_SVB_SET_DST_INDEX,
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| brw_vec4_copy_propagation.cpp | 44 is_direct_copy(vec4_instruction *inst)
58 is_dominated_by_previous_instruction(vec4_instruction *inst)
67 is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch)
136 vec4_instruction *inst,
310 vec4_instruction *inst, int arg,
475 foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
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| brw_vec4_tcs.cpp | 111 vec4_instruction *inst;
173 vec4_instruction *inst;
208 vec4_instruction *inst;
216 vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header));
239 vec4_instruction *inst;
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| brw_vec4_generator.cpp | 32 vec4_instruction *inst,
55 vec4_instruction *inst,
74 vec4_instruction *inst,
110 vec4_instruction *inst,
346 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
360 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
375 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst)
400 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
492 vec4_instruction *inst,
534 vec4_instruction *inst
[all...] |
| brw_vec4_dead_code_eliminate.cpp | 56 foreach_inst_in_block_reverse_safe(vec4_instruction, inst, block) {
|
| brw_vec4_live_variables.cpp | 73 foreach_inst_in_block(vec4_instruction, inst, block) {
255 foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
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| test_vec4_cmod_propagation.cpp | 90 virtual vec4_instruction *emit_urb_write_opcode(bool complete)
113 static vec4_instruction *
116 vec4_instruction *inst = (vec4_instruction *)block->start();
118 inst = (vec4_instruction *)inst->next;
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| brw_vec4_nir.cpp | 184 vec4_instruction *inst = emit(MOV(dst_null_d(), condition));
486 vec4_instruction *inst = new(mem_ctx)
487 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE, result_dst);
[all...] |
| brw_schedule_instructions.cpp | [all...] |
