| /hardware/intel/img/psb_video/src/x11/ |
| psb_coverlay.c | 401 struct _WsbmBufferObject *bo = subpicture->bo; local
479 ximg->data = wsbmBOMap(bo, WSBM_ACCESS_READ);
518 wsbmBOUnmap(bo);
[all...] |
| /bionic/libc/kernel/uapi/drm/ |
| vc4_drm.h | 122 __u64 bo; member in struct:drm_vc4_get_hang_state
|
| /cts/hostsidetests/security/securityPatch/CVE-2016-8431/ |
| local_poc.h | 67 struct host1x_bo *bo; member in struct:host1x_waitchk
|
| /cts/hostsidetests/security/securityPatch/CVE-2016-8432/ |
| local_poc.h | 67 struct host1x_bo *bo; member in struct:host1x_waitchk
|
| /external/deqp/external/openglcts/modules/gl/ |
| gl4cDirectStateAccessVertexArraysTests.cpp | 3534 glw::GLuint bo = 0; local
4398 glw::GLuint bo = 0; local
4533 glw::GLuint bo = 0; local
[all...] |
| /external/kernel-headers/original/uapi/drm/ |
| vc4_drm.h | 83 * BO.
91 * to the tile allocation BO.
101 * and an attribute count), so those BO indices into bo_handles are
113 * the program. Following the texture BO handle indices is the actual
137 /* Number of BO handles passed in (size is that times 4). */
192 * completion of the last DRM_VC4_SUBMIT_CL on a BO.
195 * rendering to a BO and you want to wait for all rendering to be
213 /** Returned GEM handle for the BO. */
254 /** Returned GEM handle for the BO. */
273 __u64 bo; member in struct:drm_vc4_get_hang_state
[all...] |
| /external/libdrm/intel/ |
| intel_bufmgr_fake.c | 110 drm_intel_bo *bo; member in struct:block
169 int (*exec) (drm_intel_bo *bo, unsigned int used, void *priv);
187 drm_intel_bo bo; member in struct:_drm_intel_bo_fake
224 void (*invalidate_cb) (drm_intel_bo *bo, void *ptr);
423 alloc_block(drm_intel_bo *bo)
425 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
427 (drm_intel_bufmgr_fake *) bo->bufmgr;
435 sz = (bo->size + bo_fake->alignment - 1) & ~(bo_fake->alignment - 1);
450 block->bo = bo;
[all...] |
| /external/libdrm/tests/amdgpu/ |
| basic_tests.c | 244 amdgpu_bo_handle bo; local
250 bo = gpu_mem_alloc(device_handle,
256 r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
260 bo = gpu_mem_alloc(device_handle,
266 r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
270 bo = gpu_mem_alloc(device_handle,
275 r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
279 bo = gpu_mem_alloc(device_handle,
285 r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
801 amdgpu_bo_handle bo; local
902 amdgpu_bo_handle bo; local
[all...] |
| /external/libdrm/tests/modetest/ |
| modetest.c | 123 struct bo *bo; member in struct:device::__anon24683
124 struct bo *cursor_bo;
715 struct bo *bo; member in struct:plane_arg
964 struct bo *plane_bo;
1020 p->bo = plane_bo;
1061 if (p[i].bo)
1062 bo_destroy(p[i].bo);
1071 struct bo *bo local
1160 struct bo *bo; local
[all...] |
| /external/mesa3d/src/egl/drivers/dri2/ |
| egl_dri2.h | 282 struct gbm_bo *bo; member in struct:dri2_egl_surface::__anon29357
|
| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| nv50_surface.c | 86 struct nouveau_bo *bo = mt->base.bo; local
114 if (!nouveau_bo_memtype(bo)) {
287 struct nouveau_bo *bo = mt->base.bo; local
301 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
320 if (nouveau_bo_memtype(bo))
334 if (!nouveau_bo_memtype(bo)) {
378 struct nouveau_bo *bo = mt->base.bo; local
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| nvc0_surface.c | 88 struct nouveau_bo *bo = mt->base.bo; local
117 if (!nouveau_bo_memtype(bo)) {
125 PUSH_DATAh(push, bo->offset + offset);
126 PUSH_DATA (push, bo->offset + offset);
137 PUSH_DATAh(push, bo->offset + offset);
138 PUSH_DATA (push, bo->offset + offset);
297 PUSH_REFN (push, res->bo, res->domain | NOUVEAU_BO_WR);
314 if (likely(nouveau_bo_memtype(res->bo))) {
373 nouveau_bufctx_refn(nvc0->bufctx, 0, buf->bo, buf->domain | NOUVEAU_BO_WR)
[all...] |
| /external/mesa3d/src/intel/vulkan/ |
| anv_device.c | 815 struct anv_bo bo, *exec_bos[1]; local
823 result = anv_bo_pool_alloc(&device->batch_bo_pool, &bo, size);
827 memcpy(bo.map, batch->start, size);
829 anv_clflush_range(bo.map, size);
831 exec_bos[0] = &bo;
832 exec2_objects[0].handle = bo.gem_handle;
836 exec2_objects[0].offset = bo.offset;
860 ret = anv_gem_wait(device, bo.gem_handle, &timeout);
868 anv_bo_pool_free(&device->batch_bo_pool, &bo);
[all...] |
| genX_cmd_buffer.c | 36 uint32_t reg, struct anv_bo *bo, uint32_t offset)
40 lrm.MemoryAddress = (struct anv_address) { bo, offset };
82 (struct anv_address) { &device->dynamic_state_block_pool.bo, 0 };
91 (struct anv_address) { &device->instruction_block_pool.bo, 0 };
97 * these fields. However, since we will be growing the BO's live, we
158 struct anv_bo *bo, uint32_t offset)
163 state.offset + isl_dev->ss.addr_offset, bo, offset);
176 iview->bo, iview->offset);
191 iview->bo, aux_offset);
662 struct anv_bo *ss_bo = &primary->device->surface_state_block_pool.bo;
1116 struct anv_bo *bo = cmd_buffer->state.num_workgroups_bo; local
1708 struct anv_bo *bo = buffer->bo; local
1740 struct anv_bo *bo = buffer->bo; local
1938 struct anv_bo *bo = buffer->bo; local
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_wm_surface_state.c | 146 aux_bo = mt->mcs_buf->bo;
147 aux_offset = mt->mcs_buf->bo->offset64 + mt->mcs_buf->offset;
149 aux_bo = mt->hiz_buf->aux_base.bo;
150 aux_offset = mt->hiz_buf->aux_base.bo->offset64;
165 .address = mt->bo->offset64 + offset,
171 drm_intel_bo_emit_reloc(brw->batch.bo,
173 mt->bo, offset,
185 drm_intel_bo_emit_reloc(brw->batch.bo,
651 drm_intel_bo *bo,
664 .address = (bo ? bo->offset64 : 0) + buffer_offset
689 drm_intel_bo *bo = NULL; local
764 drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_bo, local
901 drm_intel_bo *bo = NULL; local
1398 drm_intel_bo *bo = local
1423 drm_intel_bo *bo = local
1502 drm_intel_bo *bo = intel_bufferobj_buffer( local
1857 drm_intel_bo *bo; local
1866 &bo, local
[all...] |
| intel_screen.c | 146 drm_intel_gem_bo_aub_dump_bmp(irb->mt->bo,
321 drm_intel_bo_get_tiling(image->bo, &tiling, &swizzle);
400 drm_intel_bo_unreference(image->bo);
401 image->bo = mt->bo;
402 drm_intel_bo_reference(mt->bo);
426 image->bo = drm_intel_bo_gem_create_from_name(screen->bufmgr, "image",
428 if (!image->bo) {
462 drm_intel_bo_unreference(image->bo);
463 image->bo = irb->mt->bo
1286 drm_intel_bo *results, *bo; local
1935 drm_intel_bo *bo; member in struct:intel_buffer
[all...] |
| intel_mipmap_tree.c | 126 * the miptree's BO.
577 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
653 mt->bo = drm_intel_bo_alloc_for_render(brw->bufmgr, "miptree",
658 mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
664 mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
694 /* If the BO is too large to fit in the aperture, we need to use the
698 if (brw->gen < 6 && mt->bo->size >= brw->max_gtt_map_object_size &&
708 drm_intel_bo_unreference(mt->bo);
709 mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
717 if (!mt->bo) {
2505 drm_intel_bo *bo = mt->bo; local
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_screen.h | 106 struct radeon_bo *bo; member in struct:__DRIimageRec
|
| /external/mesa3d/src/mesa/main/ |
| varray.c | 2385 const struct gl_buffer_object *bo = binding->BufferObj; local
[all...] |
| /frameworks/native/opengl/libagl/ |
| array.cpp | 311 const GLvoid *pointer, const buffer_t* bo, GLsizei count)
330 this->bo = bo;
336 physical_pointer = (bo) ? (bo->data + uintptr_t(pointer)) : pointer;
1460 buffer_t const* bo = 0; local
1487 buffer_t const* bo = ((target == GL_ARRAY_BUFFER) ? local
1517 buffer_t const* bo = ((target == GL_ARRAY_BUFFER) ? local
[all...] |
| /external/libdrm/exynos/ |
| exynos_fimg2d.h | 284 unsigned int bo[G2D_PLANE_MAX_NR]; member in struct:g2d_image
|
| /external/mesa3d/src/amd/vulkan/ |
| radv_cmd_buffer.c | 195 struct radeon_winsys_bo *bo; local
202 bo = device->ws->buffer_create(device->ws,
207 if (!bo) {
212 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
218 device->ws->buffer_destroy(bo);
226 cmd_buffer->upload.upload_bo = bo;
466 va = ws->buffer_get_va(vs->bo);
467 ws->cs_add_buffer(cmd_buffer->cs, vs->bo, 8);
536 va = ws->buffer_get_va(ps->bo);
537 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_shader.h | 511 struct r600_resource *bo; member in struct:si_shader
|
| /external/mesa3d/src/gallium/drivers/vc4/ |
| vc4_context.h | 148 struct vc4_bo *bo; member in struct:vc4_compiled_shader
|
| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| intel_context.h | 109 drm_intel_bo *bo; member in struct:intel_batchbuffer
110 /** Last BO submitted to the hardware. Used for glFinish(). */
201 drm_intel_bo *bo; member in struct:intel_context::__anon30397
|
