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Searched
full:immediates
(Results
451 - 475
of
608
) sorted by null
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/external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/
LoopStrengthReduce.cpp
212
/// computing satisfying a use. It may include broken-out
immediates
and scaled
836
// Tally up the non-zero
immediates
.
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/external/v8/src/crankshaft/x64/
lithium-codegen-x64.cc
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/external/valgrind/VEX/priv/
host_mips_isel.c
225
immediate; this guaranteed that all signed
immediates
that are
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/prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/clang/include/clang/Driver/
Options.td
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/prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/clang/include/clang/Driver/
Options.td
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/toolchain/binutils/binutils-2.27/gas/config/
tc-metag.c
71
/*
Immediates
must be prefixed with a hash. */
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/external/clang/utils/TableGen/
NeonEmitter.cpp
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/external/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp
180
// Only plain
immediates
are inlinable (e.g. "clamp" attribute is not)
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/external/llvm/lib/Target/ARM/
ARMExpandPseudoInsts.cpp
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/external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp
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/external/llvm/lib/Target/Hexagon/AsmParser/
HexagonAsmParser.cpp
750
// For instruction aliases,
immediates
are generated rather than
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/external/llvm/lib/Target/Hexagon/
HexagonHardwareLoops.cpp
740
// Both, start and end are
immediates
.
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/external/llvm/lib/Target/PowerPC/AsmParser/
PPCAsmParser.cpp
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/external/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp
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PPCInstr64Bit.td
32
// to accept
immediates
in the range -65536..65535 for compatibility with
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/external/llvm/lib/Target/X86/AsmParser/
X86AsmParser.cpp
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/external/llvm/lib/Target/X86/
X86ISelLowering.cpp
510
// Expand FP
immediates
into loads from the stack, except for the special
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X86InstrCompiler.td
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/external/llvm/lib/Transforms/Scalar/
Reassociate.cpp
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/external/mesa3d/src/gallium/drivers/nouveau/codegen/
nv50_ir_ra.cpp
846
//
Immediates
are always in src1. Every other situation can be resolved by
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all
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/external/mesa3d/src/gallium/drivers/svga/
svga_tgsi_insn.c
209
/*
Immediates
are appended after TGSI constants in the D3D
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/external/swiftshader/third_party/LLVM/include/llvm/Target/
TargetLowering.h
18
//
immediates
.
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
ARMBaseInstrInfo.cpp
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
PPCInstrInfo.td
228
// imm16Shifted* - These match
immediates
where the low 16-bits are zero. There
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/external/swiftshader/third_party/LLVM/lib/Target/X86/
X86ISelDAGToDAG.cpp
739
// If this is already a %rip relative address, we can only merge
immediates
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