1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains a pass that expands pseudo instructions into target 11 // instructions to allow proper scheduling, if-conversion, and other late 12 // optimizations. This pass should be run after register allocation but before 13 // the post-regalloc scheduling pass. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "ARM.h" 18 #include "ARMBaseInstrInfo.h" 19 #include "ARMBaseRegisterInfo.h" 20 #include "ARMConstantPoolValue.h" 21 #include "ARMMachineFunctionInfo.h" 22 #include "MCTargetDesc/ARMAddressingModes.h" 23 #include "llvm/CodeGen/LivePhysRegs.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunctionPass.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineInstrBundle.h" 28 #include "llvm/IR/GlobalValue.h" 29 #include "llvm/Support/CommandLine.h" 30 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove! 31 #include "llvm/Target/TargetFrameLowering.h" 32 #include "llvm/Target/TargetRegisterInfo.h" 33 using namespace llvm; 34 35 #define DEBUG_TYPE "arm-pseudo" 36 37 static cl::opt<bool> 38 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, 39 cl::desc("Verify machine code after expanding ARM pseudos")); 40 41 namespace { 42 class ARMExpandPseudo : public MachineFunctionPass { 43 public: 44 static char ID; 45 ARMExpandPseudo() : MachineFunctionPass(ID) {} 46 47 const ARMBaseInstrInfo *TII; 48 const TargetRegisterInfo *TRI; 49 const ARMSubtarget *STI; 50 ARMFunctionInfo *AFI; 51 52 bool runOnMachineFunction(MachineFunction &Fn) override; 53 54 MachineFunctionProperties getRequiredProperties() const override { 55 return MachineFunctionProperties().set( 56 MachineFunctionProperties::Property::AllVRegsAllocated); 57 } 58 59 const char *getPassName() const override { 60 return "ARM pseudo instruction expansion pass"; 61 } 62 63 private: 64 void TransferImpOps(MachineInstr &OldMI, 65 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 66 bool ExpandMI(MachineBasicBlock &MBB, 67 MachineBasicBlock::iterator MBBI, 68 MachineBasicBlock::iterator &NextMBBI); 69 bool ExpandMBB(MachineBasicBlock &MBB); 70 void ExpandVLD(MachineBasicBlock::iterator &MBBI); 71 void ExpandVST(MachineBasicBlock::iterator &MBBI); 72 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); 73 void ExpandVTBL(MachineBasicBlock::iterator &MBBI, 74 unsigned Opc, bool IsExt); 75 void ExpandMOV32BitImm(MachineBasicBlock &MBB, 76 MachineBasicBlock::iterator &MBBI); 77 bool ExpandCMP_SWAP(MachineBasicBlock &MBB, 78 MachineBasicBlock::iterator MBBI, unsigned LdrexOp, 79 unsigned StrexOp, unsigned UxtOp, 80 MachineBasicBlock::iterator &NextMBBI); 81 82 bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB, 83 MachineBasicBlock::iterator MBBI, 84 MachineBasicBlock::iterator &NextMBBI); 85 }; 86 char ARMExpandPseudo::ID = 0; 87 } 88 89 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to 90 /// the instructions created from the expansion. 91 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, 92 MachineInstrBuilder &UseMI, 93 MachineInstrBuilder &DefMI) { 94 const MCInstrDesc &Desc = OldMI.getDesc(); 95 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); 96 i != e; ++i) { 97 const MachineOperand &MO = OldMI.getOperand(i); 98 assert(MO.isReg() && MO.getReg()); 99 if (MO.isUse()) 100 UseMI.addOperand(MO); 101 else 102 DefMI.addOperand(MO); 103 } 104 } 105 106 namespace { 107 // Constants for register spacing in NEON load/store instructions. 108 // For quad-register load-lane and store-lane pseudo instructors, the 109 // spacing is initially assumed to be EvenDblSpc, and that is changed to 110 // OddDblSpc depending on the lane number operand. 111 enum NEONRegSpacing { 112 SingleSpc, 113 EvenDblSpc, 114 OddDblSpc 115 }; 116 117 // Entries for NEON load/store information table. The table is sorted by 118 // PseudoOpc for fast binary-search lookups. 119 struct NEONLdStTableEntry { 120 uint16_t PseudoOpc; 121 uint16_t RealOpc; 122 bool IsLoad; 123 bool isUpdating; 124 bool hasWritebackOperand; 125 uint8_t RegSpacing; // One of type NEONRegSpacing 126 uint8_t NumRegs; // D registers loaded or stored 127 uint8_t RegElts; // elements per D register; used for lane ops 128 // FIXME: Temporary flag to denote whether the real instruction takes 129 // a single register (like the encoding) or all of the registers in 130 // the list (like the asm syntax and the isel DAG). When all definitions 131 // are converted to take only the single encoded register, this will 132 // go away. 133 bool copyAllListRegs; 134 135 // Comparison methods for binary search of the table. 136 bool operator<(const NEONLdStTableEntry &TE) const { 137 return PseudoOpc < TE.PseudoOpc; 138 } 139 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { 140 return TE.PseudoOpc < PseudoOpc; 141 } 142 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, 143 const NEONLdStTableEntry &TE) { 144 return PseudoOpc < TE.PseudoOpc; 145 } 146 }; 147 } 148 149 static const NEONLdStTableEntry NEONLdStTable[] = { 150 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true}, 151 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true}, 152 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true}, 153 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true}, 154 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true}, 155 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true}, 156 157 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false}, 158 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false}, 159 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false}, 160 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false}, 161 162 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true}, 163 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true}, 164 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true}, 165 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true}, 166 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true}, 167 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true}, 168 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true}, 169 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true}, 170 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true}, 171 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true}, 172 173 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false}, 174 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false}, 175 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false}, 176 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false}, 177 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false}, 178 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false}, 179 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false}, 180 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false}, 181 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false}, 182 183 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true}, 184 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true}, 185 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true}, 186 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true}, 187 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true}, 188 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true}, 189 190 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true}, 191 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 192 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true}, 193 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 194 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true}, 195 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 196 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true}, 197 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 198 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true}, 199 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 200 201 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true}, 202 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 203 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true}, 204 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 205 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true}, 206 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 207 208 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 209 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true}, 210 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true}, 211 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 212 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true}, 213 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true}, 214 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true}, 215 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true}, 216 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true}, 217 218 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true}, 219 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true}, 220 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true}, 221 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true}, 222 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true}, 223 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true}, 224 225 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true}, 226 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 227 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true}, 228 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 229 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true}, 230 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 231 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true}, 232 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 233 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true}, 234 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 235 236 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true}, 237 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 238 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true}, 239 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 240 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true}, 241 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 242 243 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 244 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true}, 245 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true}, 246 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 247 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true}, 248 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true}, 249 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true}, 250 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true}, 251 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true}, 252 253 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true}, 254 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true}, 255 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true}, 256 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true}, 257 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true}, 258 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true}, 259 260 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false}, 261 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false}, 262 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false}, 263 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false}, 264 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false}, 265 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false}, 266 267 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true}, 268 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true}, 269 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true}, 270 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true}, 271 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true}, 272 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true}, 273 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true}, 274 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true}, 275 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true}, 276 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true}, 277 278 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false}, 279 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false}, 280 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false}, 281 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false}, 282 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false}, 283 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false}, 284 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false}, 285 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false}, 286 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false}, 287 288 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true}, 289 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 290 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true}, 291 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 292 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true}, 293 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 294 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true}, 295 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true}, 296 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true}, 297 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true}, 298 299 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true}, 300 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 301 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true}, 302 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 303 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true}, 304 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 305 306 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true}, 307 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true}, 308 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true}, 309 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true}, 310 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true}, 311 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true}, 312 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true}, 313 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true}, 314 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true}, 315 316 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true}, 317 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 318 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true}, 319 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 320 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true}, 321 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 322 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true}, 323 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true}, 324 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true}, 325 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true}, 326 327 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true}, 328 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 329 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true}, 330 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 331 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true}, 332 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 333 334 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true}, 335 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true}, 336 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true}, 337 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true}, 338 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true}, 339 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true}, 340 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true}, 341 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true}, 342 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true} 343 }; 344 345 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON 346 /// load or store pseudo instruction. 347 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { 348 #ifndef NDEBUG 349 // Make sure the table is sorted. 350 static bool TableChecked = false; 351 if (!TableChecked) { 352 assert(std::is_sorted(std::begin(NEONLdStTable), std::end(NEONLdStTable)) && 353 "NEONLdStTable is not sorted!"); 354 TableChecked = true; 355 } 356 #endif 357 358 auto I = std::lower_bound(std::begin(NEONLdStTable), 359 std::end(NEONLdStTable), Opcode); 360 if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode) 361 return I; 362 return nullptr; 363 } 364 365 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, 366 /// corresponding to the specified register spacing. Not all of the results 367 /// are necessarily valid, e.g., a Q register only has 2 D subregisters. 368 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, 369 const TargetRegisterInfo *TRI, unsigned &D0, 370 unsigned &D1, unsigned &D2, unsigned &D3) { 371 if (RegSpc == SingleSpc) { 372 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 373 D1 = TRI->getSubReg(Reg, ARM::dsub_1); 374 D2 = TRI->getSubReg(Reg, ARM::dsub_2); 375 D3 = TRI->getSubReg(Reg, ARM::dsub_3); 376 } else if (RegSpc == EvenDblSpc) { 377 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 378 D1 = TRI->getSubReg(Reg, ARM::dsub_2); 379 D2 = TRI->getSubReg(Reg, ARM::dsub_4); 380 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 381 } else { 382 assert(RegSpc == OddDblSpc && "unknown register spacing"); 383 D0 = TRI->getSubReg(Reg, ARM::dsub_1); 384 D1 = TRI->getSubReg(Reg, ARM::dsub_3); 385 D2 = TRI->getSubReg(Reg, ARM::dsub_5); 386 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 387 } 388 } 389 390 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register 391 /// operands to real VLD instructions with D register operands. 392 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { 393 MachineInstr &MI = *MBBI; 394 MachineBasicBlock &MBB = *MI.getParent(); 395 396 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 397 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); 398 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 399 unsigned NumRegs = TableEntry->NumRegs; 400 401 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 402 TII->get(TableEntry->RealOpc)); 403 unsigned OpIdx = 0; 404 405 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 406 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 407 unsigned D0, D1, D2, D3; 408 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 409 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 410 if (NumRegs > 1 && TableEntry->copyAllListRegs) 411 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 412 if (NumRegs > 2 && TableEntry->copyAllListRegs) 413 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 414 if (NumRegs > 3 && TableEntry->copyAllListRegs) 415 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 416 417 if (TableEntry->isUpdating) 418 MIB.addOperand(MI.getOperand(OpIdx++)); 419 420 // Copy the addrmode6 operands. 421 MIB.addOperand(MI.getOperand(OpIdx++)); 422 MIB.addOperand(MI.getOperand(OpIdx++)); 423 // Copy the am6offset operand. 424 if (TableEntry->hasWritebackOperand) 425 MIB.addOperand(MI.getOperand(OpIdx++)); 426 427 // For an instruction writing double-spaced subregs, the pseudo instruction 428 // has an extra operand that is a use of the super-register. Record the 429 // operand index and skip over it. 430 unsigned SrcOpIdx = 0; 431 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) 432 SrcOpIdx = OpIdx++; 433 434 // Copy the predicate operands. 435 MIB.addOperand(MI.getOperand(OpIdx++)); 436 MIB.addOperand(MI.getOperand(OpIdx++)); 437 438 // Copy the super-register source operand used for double-spaced subregs over 439 // to the new instruction as an implicit operand. 440 if (SrcOpIdx != 0) { 441 MachineOperand MO = MI.getOperand(SrcOpIdx); 442 MO.setImplicit(true); 443 MIB.addOperand(MO); 444 } 445 // Add an implicit def for the super-register. 446 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 447 TransferImpOps(MI, MIB, MIB); 448 449 // Transfer memoperands. 450 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 451 452 MI.eraseFromParent(); 453 } 454 455 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register 456 /// operands to real VST instructions with D register operands. 457 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { 458 MachineInstr &MI = *MBBI; 459 MachineBasicBlock &MBB = *MI.getParent(); 460 461 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 462 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); 463 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 464 unsigned NumRegs = TableEntry->NumRegs; 465 466 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 467 TII->get(TableEntry->RealOpc)); 468 unsigned OpIdx = 0; 469 if (TableEntry->isUpdating) 470 MIB.addOperand(MI.getOperand(OpIdx++)); 471 472 // Copy the addrmode6 operands. 473 MIB.addOperand(MI.getOperand(OpIdx++)); 474 MIB.addOperand(MI.getOperand(OpIdx++)); 475 // Copy the am6offset operand. 476 if (TableEntry->hasWritebackOperand) 477 MIB.addOperand(MI.getOperand(OpIdx++)); 478 479 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 480 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef(); 481 unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 482 unsigned D0, D1, D2, D3; 483 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); 484 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); 485 if (NumRegs > 1 && TableEntry->copyAllListRegs) 486 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); 487 if (NumRegs > 2 && TableEntry->copyAllListRegs) 488 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); 489 if (NumRegs > 3 && TableEntry->copyAllListRegs) 490 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); 491 492 // Copy the predicate operands. 493 MIB.addOperand(MI.getOperand(OpIdx++)); 494 MIB.addOperand(MI.getOperand(OpIdx++)); 495 496 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg. 497 MIB->addRegisterKilled(SrcReg, TRI, true); 498 else if (!SrcIsUndef) 499 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. 500 TransferImpOps(MI, MIB, MIB); 501 502 // Transfer memoperands. 503 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 504 505 MI.eraseFromParent(); 506 } 507 508 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ 509 /// register operands to real instructions with D register operands. 510 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { 511 MachineInstr &MI = *MBBI; 512 MachineBasicBlock &MBB = *MI.getParent(); 513 514 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 515 assert(TableEntry && "NEONLdStTable lookup failed"); 516 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 517 unsigned NumRegs = TableEntry->NumRegs; 518 unsigned RegElts = TableEntry->RegElts; 519 520 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 521 TII->get(TableEntry->RealOpc)); 522 unsigned OpIdx = 0; 523 // The lane operand is always the 3rd from last operand, before the 2 524 // predicate operands. 525 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 526 527 // Adjust the lane and spacing as needed for Q registers. 528 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 529 if (RegSpc == EvenDblSpc && Lane >= RegElts) { 530 RegSpc = OddDblSpc; 531 Lane -= RegElts; 532 } 533 assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 534 535 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; 536 unsigned DstReg = 0; 537 bool DstIsDead = false; 538 if (TableEntry->IsLoad) { 539 DstIsDead = MI.getOperand(OpIdx).isDead(); 540 DstReg = MI.getOperand(OpIdx++).getReg(); 541 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 542 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 543 if (NumRegs > 1) 544 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 545 if (NumRegs > 2) 546 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 547 if (NumRegs > 3) 548 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 549 } 550 551 if (TableEntry->isUpdating) 552 MIB.addOperand(MI.getOperand(OpIdx++)); 553 554 // Copy the addrmode6 operands. 555 MIB.addOperand(MI.getOperand(OpIdx++)); 556 MIB.addOperand(MI.getOperand(OpIdx++)); 557 // Copy the am6offset operand. 558 if (TableEntry->hasWritebackOperand) 559 MIB.addOperand(MI.getOperand(OpIdx++)); 560 561 // Grab the super-register source. 562 MachineOperand MO = MI.getOperand(OpIdx++); 563 if (!TableEntry->IsLoad) 564 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); 565 566 // Add the subregs as sources of the new instruction. 567 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | 568 getKillRegState(MO.isKill())); 569 MIB.addReg(D0, SrcFlags); 570 if (NumRegs > 1) 571 MIB.addReg(D1, SrcFlags); 572 if (NumRegs > 2) 573 MIB.addReg(D2, SrcFlags); 574 if (NumRegs > 3) 575 MIB.addReg(D3, SrcFlags); 576 577 // Add the lane number operand. 578 MIB.addImm(Lane); 579 OpIdx += 1; 580 581 // Copy the predicate operands. 582 MIB.addOperand(MI.getOperand(OpIdx++)); 583 MIB.addOperand(MI.getOperand(OpIdx++)); 584 585 // Copy the super-register source to be an implicit source. 586 MO.setImplicit(true); 587 MIB.addOperand(MO); 588 if (TableEntry->IsLoad) 589 // Add an implicit def for the super-register. 590 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 591 TransferImpOps(MI, MIB, MIB); 592 // Transfer memoperands. 593 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 594 MI.eraseFromParent(); 595 } 596 597 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ 598 /// register operands to real instructions with D register operands. 599 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, 600 unsigned Opc, bool IsExt) { 601 MachineInstr &MI = *MBBI; 602 MachineBasicBlock &MBB = *MI.getParent(); 603 604 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 605 unsigned OpIdx = 0; 606 607 // Transfer the destination register operand. 608 MIB.addOperand(MI.getOperand(OpIdx++)); 609 if (IsExt) 610 MIB.addOperand(MI.getOperand(OpIdx++)); 611 612 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 613 unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 614 unsigned D0, D1, D2, D3; 615 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); 616 MIB.addReg(D0); 617 618 // Copy the other source register operand. 619 MIB.addOperand(MI.getOperand(OpIdx++)); 620 621 // Copy the predicate operands. 622 MIB.addOperand(MI.getOperand(OpIdx++)); 623 MIB.addOperand(MI.getOperand(OpIdx++)); 624 625 // Add an implicit kill and use for the super-reg. 626 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill)); 627 TransferImpOps(MI, MIB, MIB); 628 MI.eraseFromParent(); 629 } 630 631 static bool IsAnAddressOperand(const MachineOperand &MO) { 632 // This check is overly conservative. Unless we are certain that the machine 633 // operand is not a symbol reference, we return that it is a symbol reference. 634 // This is important as the load pair may not be split up Windows. 635 switch (MO.getType()) { 636 case MachineOperand::MO_Register: 637 case MachineOperand::MO_Immediate: 638 case MachineOperand::MO_CImmediate: 639 case MachineOperand::MO_FPImmediate: 640 return false; 641 case MachineOperand::MO_MachineBasicBlock: 642 return true; 643 case MachineOperand::MO_FrameIndex: 644 return false; 645 case MachineOperand::MO_ConstantPoolIndex: 646 case MachineOperand::MO_TargetIndex: 647 case MachineOperand::MO_JumpTableIndex: 648 case MachineOperand::MO_ExternalSymbol: 649 case MachineOperand::MO_GlobalAddress: 650 case MachineOperand::MO_BlockAddress: 651 return true; 652 case MachineOperand::MO_RegisterMask: 653 case MachineOperand::MO_RegisterLiveOut: 654 return false; 655 case MachineOperand::MO_Metadata: 656 case MachineOperand::MO_MCSymbol: 657 return true; 658 case MachineOperand::MO_CFIIndex: 659 return false; 660 } 661 llvm_unreachable("unhandled machine operand type"); 662 } 663 664 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, 665 MachineBasicBlock::iterator &MBBI) { 666 MachineInstr &MI = *MBBI; 667 unsigned Opcode = MI.getOpcode(); 668 unsigned PredReg = 0; 669 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 670 unsigned DstReg = MI.getOperand(0).getReg(); 671 bool DstIsDead = MI.getOperand(0).isDead(); 672 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; 673 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); 674 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO); 675 MachineInstrBuilder LO16, HI16; 676 677 if (!STI->hasV6T2Ops() && 678 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { 679 // FIXME Windows CE supports older ARM CPUs 680 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+"); 681 682 // Expand into a movi + orr. 683 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 684 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) 685 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 686 .addReg(DstReg); 687 688 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); 689 unsigned ImmVal = (unsigned)MO.getImm(); 690 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 691 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 692 LO16 = LO16.addImm(SOImmValV1); 693 HI16 = HI16.addImm(SOImmValV2); 694 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 695 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 696 LO16.addImm(Pred).addReg(PredReg).addReg(0); 697 HI16.addImm(Pred).addReg(PredReg).addReg(0); 698 TransferImpOps(MI, LO16, HI16); 699 MI.eraseFromParent(); 700 return; 701 } 702 703 unsigned LO16Opc = 0; 704 unsigned HI16Opc = 0; 705 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { 706 LO16Opc = ARM::t2MOVi16; 707 HI16Opc = ARM::t2MOVTi16; 708 } else { 709 LO16Opc = ARM::MOVi16; 710 HI16Opc = ARM::MOVTi16; 711 } 712 713 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); 714 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) 715 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 716 .addReg(DstReg); 717 718 switch (MO.getType()) { 719 case MachineOperand::MO_Immediate: { 720 unsigned Imm = MO.getImm(); 721 unsigned Lo16 = Imm & 0xffff; 722 unsigned Hi16 = (Imm >> 16) & 0xffff; 723 LO16 = LO16.addImm(Lo16); 724 HI16 = HI16.addImm(Hi16); 725 break; 726 } 727 case MachineOperand::MO_ExternalSymbol: { 728 const char *ES = MO.getSymbolName(); 729 unsigned TF = MO.getTargetFlags(); 730 LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16); 731 HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16); 732 break; 733 } 734 default: { 735 const GlobalValue *GV = MO.getGlobal(); 736 unsigned TF = MO.getTargetFlags(); 737 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); 738 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); 739 break; 740 } 741 } 742 743 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 744 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 745 LO16.addImm(Pred).addReg(PredReg); 746 HI16.addImm(Pred).addReg(PredReg); 747 748 if (RequiresBundling) 749 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator()); 750 751 TransferImpOps(MI, LO16, HI16); 752 MI.eraseFromParent(); 753 } 754 755 static void addPostLoopLiveIns(MachineBasicBlock *MBB, LivePhysRegs &LiveRegs) { 756 for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I) 757 MBB->addLiveIn(*I); 758 } 759 760 /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as 761 /// possible. This only gets used at -O0 so we don't care about efficiency of the 762 /// generated code. 763 bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB, 764 MachineBasicBlock::iterator MBBI, 765 unsigned LdrexOp, unsigned StrexOp, 766 unsigned UxtOp, 767 MachineBasicBlock::iterator &NextMBBI) { 768 bool IsThumb = STI->isThumb(); 769 MachineInstr &MI = *MBBI; 770 DebugLoc DL = MI.getDebugLoc(); 771 MachineOperand &Dest = MI.getOperand(0); 772 unsigned StatusReg = MI.getOperand(1).getReg(); 773 MachineOperand &Addr = MI.getOperand(2); 774 MachineOperand &Desired = MI.getOperand(3); 775 MachineOperand &New = MI.getOperand(4); 776 777 LivePhysRegs LiveRegs(&TII->getRegisterInfo()); 778 LiveRegs.addLiveOuts(MBB); 779 for (auto I = std::prev(MBB.end()); I != MBBI; --I) 780 LiveRegs.stepBackward(*I); 781 782 MachineFunction *MF = MBB.getParent(); 783 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 784 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 785 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 786 787 MF->insert(++MBB.getIterator(), LoadCmpBB); 788 MF->insert(++LoadCmpBB->getIterator(), StoreBB); 789 MF->insert(++StoreBB->getIterator(), DoneBB); 790 791 if (UxtOp) { 792 MachineInstrBuilder MIB = 793 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), Desired.getReg()) 794 .addReg(Desired.getReg(), RegState::Kill); 795 if (!IsThumb) 796 MIB.addImm(0); 797 AddDefaultPred(MIB); 798 } 799 800 // .Lloadcmp: 801 // ldrex rDest, [rAddr] 802 // cmp rDest, rDesired 803 // bne .Ldone 804 LoadCmpBB->addLiveIn(Addr.getReg()); 805 LoadCmpBB->addLiveIn(Dest.getReg()); 806 LoadCmpBB->addLiveIn(Desired.getReg()); 807 addPostLoopLiveIns(LoadCmpBB, LiveRegs); 808 809 MachineInstrBuilder MIB; 810 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg()); 811 MIB.addReg(Addr.getReg()); 812 if (LdrexOp == ARM::t2LDREX) 813 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset. 814 AddDefaultPred(MIB); 815 816 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; 817 AddDefaultPred(BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 818 .addReg(Dest.getReg(), getKillRegState(Dest.isDead())) 819 .addOperand(Desired)); 820 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; 821 BuildMI(LoadCmpBB, DL, TII->get(Bcc)) 822 .addMBB(DoneBB) 823 .addImm(ARMCC::NE) 824 .addReg(ARM::CPSR, RegState::Kill); 825 LoadCmpBB->addSuccessor(DoneBB); 826 LoadCmpBB->addSuccessor(StoreBB); 827 828 // .Lstore: 829 // strex rStatus, rNew, [rAddr] 830 // cmp rStatus, #0 831 // bne .Lloadcmp 832 StoreBB->addLiveIn(Addr.getReg()); 833 StoreBB->addLiveIn(New.getReg()); 834 addPostLoopLiveIns(StoreBB, LiveRegs); 835 836 837 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), StatusReg); 838 MIB.addOperand(New); 839 MIB.addOperand(Addr); 840 if (StrexOp == ARM::t2STREX) 841 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset. 842 AddDefaultPred(MIB); 843 844 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; 845 AddDefaultPred(BuildMI(StoreBB, DL, TII->get(CMPri)) 846 .addReg(StatusReg, RegState::Kill) 847 .addImm(0)); 848 BuildMI(StoreBB, DL, TII->get(Bcc)) 849 .addMBB(LoadCmpBB) 850 .addImm(ARMCC::NE) 851 .addReg(ARM::CPSR, RegState::Kill); 852 StoreBB->addSuccessor(LoadCmpBB); 853 StoreBB->addSuccessor(DoneBB); 854 855 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); 856 DoneBB->transferSuccessors(&MBB); 857 addPostLoopLiveIns(DoneBB, LiveRegs); 858 859 MBB.addSuccessor(LoadCmpBB); 860 861 NextMBBI = MBB.end(); 862 MI.eraseFromParent(); 863 return true; 864 } 865 866 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a 867 /// single GPRPair register), Thumb's take two separate registers so we need to 868 /// extract the subregs from the pair. 869 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, 870 unsigned Flags, bool IsThumb, 871 const TargetRegisterInfo *TRI) { 872 if (IsThumb) { 873 unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); 874 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); 875 MIB.addReg(RegLo, Flags | getKillRegState(Reg.isDead())); 876 MIB.addReg(RegHi, Flags | getKillRegState(Reg.isDead())); 877 } else 878 MIB.addReg(Reg.getReg(), Flags | getKillRegState(Reg.isDead())); 879 } 880 881 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop. 882 bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB, 883 MachineBasicBlock::iterator MBBI, 884 MachineBasicBlock::iterator &NextMBBI) { 885 bool IsThumb = STI->isThumb(); 886 MachineInstr &MI = *MBBI; 887 DebugLoc DL = MI.getDebugLoc(); 888 MachineOperand &Dest = MI.getOperand(0); 889 unsigned StatusReg = MI.getOperand(1).getReg(); 890 MachineOperand &Addr = MI.getOperand(2); 891 MachineOperand &Desired = MI.getOperand(3); 892 MachineOperand &New = MI.getOperand(4); 893 894 unsigned DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); 895 unsigned DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1); 896 unsigned DesiredLo = TRI->getSubReg(Desired.getReg(), ARM::gsub_0); 897 unsigned DesiredHi = TRI->getSubReg(Desired.getReg(), ARM::gsub_1); 898 899 LivePhysRegs LiveRegs(&TII->getRegisterInfo()); 900 LiveRegs.addLiveOuts(MBB); 901 for (auto I = std::prev(MBB.end()); I != MBBI; --I) 902 LiveRegs.stepBackward(*I); 903 904 MachineFunction *MF = MBB.getParent(); 905 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 906 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 907 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 908 909 MF->insert(++MBB.getIterator(), LoadCmpBB); 910 MF->insert(++LoadCmpBB->getIterator(), StoreBB); 911 MF->insert(++StoreBB->getIterator(), DoneBB); 912 913 // .Lloadcmp: 914 // ldrexd rDestLo, rDestHi, [rAddr] 915 // cmp rDestLo, rDesiredLo 916 // sbcs rStatus<dead>, rDestHi, rDesiredHi 917 // bne .Ldone 918 LoadCmpBB->addLiveIn(Addr.getReg()); 919 LoadCmpBB->addLiveIn(Dest.getReg()); 920 LoadCmpBB->addLiveIn(Desired.getReg()); 921 addPostLoopLiveIns(LoadCmpBB, LiveRegs); 922 923 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD; 924 MachineInstrBuilder MIB; 925 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD)); 926 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI); 927 MIB.addReg(Addr.getReg()); 928 AddDefaultPred(MIB); 929 930 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; 931 AddDefaultPred(BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 932 .addReg(DestLo, getKillRegState(Dest.isDead())) 933 .addReg(DesiredLo, getKillRegState(Desired.isDead()))); 934 935 unsigned SBCrr = IsThumb ? ARM::t2SBCrr : ARM::SBCrr; 936 MIB = BuildMI(LoadCmpBB, DL, TII->get(SBCrr)) 937 .addReg(StatusReg, RegState::Define | RegState::Dead) 938 .addReg(DestHi, getKillRegState(Dest.isDead())) 939 .addReg(DesiredHi, getKillRegState(Desired.isDead())); 940 AddDefaultPred(MIB); 941 MIB.addReg(ARM::CPSR, RegState::Kill); 942 943 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; 944 BuildMI(LoadCmpBB, DL, TII->get(Bcc)) 945 .addMBB(DoneBB) 946 .addImm(ARMCC::NE) 947 .addReg(ARM::CPSR, RegState::Kill); 948 LoadCmpBB->addSuccessor(DoneBB); 949 LoadCmpBB->addSuccessor(StoreBB); 950 951 // .Lstore: 952 // strexd rStatus, rNewLo, rNewHi, [rAddr] 953 // cmp rStatus, #0 954 // bne .Lloadcmp 955 StoreBB->addLiveIn(Addr.getReg()); 956 StoreBB->addLiveIn(New.getReg()); 957 addPostLoopLiveIns(StoreBB, LiveRegs); 958 959 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD; 960 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), StatusReg); 961 addExclusiveRegPair(MIB, New, 0, IsThumb, TRI); 962 MIB.addOperand(Addr); 963 AddDefaultPred(MIB); 964 965 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; 966 AddDefaultPred(BuildMI(StoreBB, DL, TII->get(CMPri)) 967 .addReg(StatusReg, RegState::Kill) 968 .addImm(0)); 969 BuildMI(StoreBB, DL, TII->get(Bcc)) 970 .addMBB(LoadCmpBB) 971 .addImm(ARMCC::NE) 972 .addReg(ARM::CPSR, RegState::Kill); 973 StoreBB->addSuccessor(LoadCmpBB); 974 StoreBB->addSuccessor(DoneBB); 975 976 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); 977 DoneBB->transferSuccessors(&MBB); 978 addPostLoopLiveIns(DoneBB, LiveRegs); 979 980 MBB.addSuccessor(LoadCmpBB); 981 982 NextMBBI = MBB.end(); 983 MI.eraseFromParent(); 984 return true; 985 } 986 987 988 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, 989 MachineBasicBlock::iterator MBBI, 990 MachineBasicBlock::iterator &NextMBBI) { 991 MachineInstr &MI = *MBBI; 992 unsigned Opcode = MI.getOpcode(); 993 switch (Opcode) { 994 default: 995 return false; 996 997 case ARM::TCRETURNdi: 998 case ARM::TCRETURNri: { 999 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 1000 assert(MBBI->isReturn() && 1001 "Can only insert epilog into returning blocks"); 1002 unsigned RetOpcode = MBBI->getOpcode(); 1003 DebugLoc dl = MBBI->getDebugLoc(); 1004 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>( 1005 MBB.getParent()->getSubtarget().getInstrInfo()); 1006 1007 // Tail call return: adjust the stack pointer and jump to callee. 1008 MBBI = MBB.getLastNonDebugInstr(); 1009 MachineOperand &JumpTarget = MBBI->getOperand(0); 1010 1011 // Jump to label or value in register. 1012 if (RetOpcode == ARM::TCRETURNdi) { 1013 unsigned TCOpcode = 1014 STI->isThumb() 1015 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) 1016 : ARM::TAILJMPd; 1017 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); 1018 if (JumpTarget.isGlobal()) 1019 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 1020 JumpTarget.getTargetFlags()); 1021 else { 1022 assert(JumpTarget.isSymbol()); 1023 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 1024 JumpTarget.getTargetFlags()); 1025 } 1026 1027 // Add the default predicate in Thumb mode. 1028 if (STI->isThumb()) 1029 MIB.addImm(ARMCC::AL).addReg(0); 1030 } else if (RetOpcode == ARM::TCRETURNri) { 1031 BuildMI(MBB, MBBI, dl, 1032 TII.get(STI->isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)) 1033 .addReg(JumpTarget.getReg(), RegState::Kill); 1034 } 1035 1036 auto NewMI = std::prev(MBBI); 1037 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) 1038 NewMI->addOperand(MBBI->getOperand(i)); 1039 1040 // Delete the pseudo instruction TCRETURN. 1041 MBB.erase(MBBI); 1042 MBBI = NewMI; 1043 return true; 1044 } 1045 case ARM::VMOVScc: 1046 case ARM::VMOVDcc: { 1047 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD; 1048 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), 1049 MI.getOperand(1).getReg()) 1050 .addOperand(MI.getOperand(2)) 1051 .addImm(MI.getOperand(3).getImm()) // 'pred' 1052 .addOperand(MI.getOperand(4)); 1053 1054 MI.eraseFromParent(); 1055 return true; 1056 } 1057 case ARM::t2MOVCCr: 1058 case ARM::MOVCCr: { 1059 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; 1060 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 1061 MI.getOperand(1).getReg()) 1062 .addOperand(MI.getOperand(2)) 1063 .addImm(MI.getOperand(3).getImm()) // 'pred' 1064 .addOperand(MI.getOperand(4)) 1065 .addReg(0); // 's' bit 1066 1067 MI.eraseFromParent(); 1068 return true; 1069 } 1070 case ARM::MOVCCsi: { 1071 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 1072 (MI.getOperand(1).getReg())) 1073 .addOperand(MI.getOperand(2)) 1074 .addImm(MI.getOperand(3).getImm()) 1075 .addImm(MI.getOperand(4).getImm()) // 'pred' 1076 .addOperand(MI.getOperand(5)) 1077 .addReg(0); // 's' bit 1078 1079 MI.eraseFromParent(); 1080 return true; 1081 } 1082 case ARM::MOVCCsr: { 1083 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), 1084 (MI.getOperand(1).getReg())) 1085 .addOperand(MI.getOperand(2)) 1086 .addOperand(MI.getOperand(3)) 1087 .addImm(MI.getOperand(4).getImm()) 1088 .addImm(MI.getOperand(5).getImm()) // 'pred' 1089 .addOperand(MI.getOperand(6)) 1090 .addReg(0); // 's' bit 1091 1092 MI.eraseFromParent(); 1093 return true; 1094 } 1095 case ARM::t2MOVCCi16: 1096 case ARM::MOVCCi16: { 1097 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; 1098 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 1099 MI.getOperand(1).getReg()) 1100 .addImm(MI.getOperand(2).getImm()) 1101 .addImm(MI.getOperand(3).getImm()) // 'pred' 1102 .addOperand(MI.getOperand(4)); 1103 MI.eraseFromParent(); 1104 return true; 1105 } 1106 case ARM::t2MOVCCi: 1107 case ARM::MOVCCi: { 1108 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; 1109 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 1110 MI.getOperand(1).getReg()) 1111 .addImm(MI.getOperand(2).getImm()) 1112 .addImm(MI.getOperand(3).getImm()) // 'pred' 1113 .addOperand(MI.getOperand(4)) 1114 .addReg(0); // 's' bit 1115 1116 MI.eraseFromParent(); 1117 return true; 1118 } 1119 case ARM::t2MVNCCi: 1120 case ARM::MVNCCi: { 1121 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; 1122 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 1123 MI.getOperand(1).getReg()) 1124 .addImm(MI.getOperand(2).getImm()) 1125 .addImm(MI.getOperand(3).getImm()) // 'pred' 1126 .addOperand(MI.getOperand(4)) 1127 .addReg(0); // 's' bit 1128 1129 MI.eraseFromParent(); 1130 return true; 1131 } 1132 case ARM::t2MOVCClsl: 1133 case ARM::t2MOVCClsr: 1134 case ARM::t2MOVCCasr: 1135 case ARM::t2MOVCCror: { 1136 unsigned NewOpc; 1137 switch (Opcode) { 1138 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; 1139 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; 1140 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; 1141 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; 1142 default: llvm_unreachable("unexpeced conditional move"); 1143 } 1144 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 1145 MI.getOperand(1).getReg()) 1146 .addOperand(MI.getOperand(2)) 1147 .addImm(MI.getOperand(3).getImm()) 1148 .addImm(MI.getOperand(4).getImm()) // 'pred' 1149 .addOperand(MI.getOperand(5)) 1150 .addReg(0); // 's' bit 1151 MI.eraseFromParent(); 1152 return true; 1153 } 1154 case ARM::Int_eh_sjlj_dispatchsetup: { 1155 MachineFunction &MF = *MI.getParent()->getParent(); 1156 const ARMBaseInstrInfo *AII = 1157 static_cast<const ARMBaseInstrInfo*>(TII); 1158 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 1159 // For functions using a base pointer, we rematerialize it (via the frame 1160 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it 1161 // for us. Otherwise, expand to nothing. 1162 if (RI.hasBasePointer(MF)) { 1163 int32_t NumBytes = AFI->getFramePtrSpillOffset(); 1164 unsigned FramePtr = RI.getFrameRegister(MF); 1165 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) && 1166 "base pointer without frame pointer?"); 1167 1168 if (AFI->isThumb2Function()) { 1169 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 1170 FramePtr, -NumBytes, ARMCC::AL, 0, *TII); 1171 } else if (AFI->isThumbFunction()) { 1172 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 1173 FramePtr, -NumBytes, *TII, RI); 1174 } else { 1175 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 1176 FramePtr, -NumBytes, ARMCC::AL, 0, 1177 *TII); 1178 } 1179 // If there's dynamic realignment, adjust for it. 1180 if (RI.needsStackRealignment(MF)) { 1181 MachineFrameInfo *MFI = MF.getFrameInfo(); 1182 unsigned MaxAlign = MFI->getMaxAlignment(); 1183 assert (!AFI->isThumb1OnlyFunction()); 1184 // Emit bic r6, r6, MaxAlign 1185 assert(MaxAlign <= 256 && "The BIC instruction cannot encode " 1186 "immediates larger than 256 with all lower " 1187 "bits set."); 1188 unsigned bicOpc = AFI->isThumbFunction() ? 1189 ARM::t2BICri : ARM::BICri; 1190 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 1191 TII->get(bicOpc), ARM::R6) 1192 .addReg(ARM::R6, RegState::Kill) 1193 .addImm(MaxAlign-1))); 1194 } 1195 1196 } 1197 MI.eraseFromParent(); 1198 return true; 1199 } 1200 1201 case ARM::MOVsrl_flag: 1202 case ARM::MOVsra_flag: { 1203 // These are just fancy MOVs instructions. 1204 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 1205 MI.getOperand(0).getReg()) 1206 .addOperand(MI.getOperand(1)) 1207 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? 1208 ARM_AM::lsr : ARM_AM::asr), 1209 1))) 1210 .addReg(ARM::CPSR, RegState::Define); 1211 MI.eraseFromParent(); 1212 return true; 1213 } 1214 case ARM::RRX: { 1215 // This encodes as "MOVs Rd, Rm, rrx 1216 MachineInstrBuilder MIB = 1217 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi), 1218 MI.getOperand(0).getReg()) 1219 .addOperand(MI.getOperand(1)) 1220 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))) 1221 .addReg(0); 1222 TransferImpOps(MI, MIB, MIB); 1223 MI.eraseFromParent(); 1224 return true; 1225 } 1226 case ARM::tTPsoft: 1227 case ARM::TPsoft: { 1228 MachineInstrBuilder MIB; 1229 if (Opcode == ARM::tTPsoft) 1230 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1231 TII->get( ARM::tBL)) 1232 .addImm((unsigned)ARMCC::AL).addReg(0) 1233 .addExternalSymbol("__aeabi_read_tp", 0); 1234 else 1235 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1236 TII->get( ARM::BL)) 1237 .addExternalSymbol("__aeabi_read_tp", 0); 1238 1239 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 1240 TransferImpOps(MI, MIB, MIB); 1241 MI.eraseFromParent(); 1242 return true; 1243 } 1244 case ARM::tLDRpci_pic: 1245 case ARM::t2LDRpci_pic: { 1246 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) 1247 ? ARM::tLDRpci : ARM::t2LDRpci; 1248 unsigned DstReg = MI.getOperand(0).getReg(); 1249 bool DstIsDead = MI.getOperand(0).isDead(); 1250 MachineInstrBuilder MIB1 = 1251 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 1252 TII->get(NewLdOpc), DstReg) 1253 .addOperand(MI.getOperand(1))); 1254 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 1255 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1256 TII->get(ARM::tPICADD)) 1257 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 1258 .addReg(DstReg) 1259 .addOperand(MI.getOperand(2)); 1260 TransferImpOps(MI, MIB1, MIB2); 1261 MI.eraseFromParent(); 1262 return true; 1263 } 1264 1265 case ARM::LDRLIT_ga_abs: 1266 case ARM::LDRLIT_ga_pcrel: 1267 case ARM::LDRLIT_ga_pcrel_ldr: 1268 case ARM::tLDRLIT_ga_abs: 1269 case ARM::tLDRLIT_ga_pcrel: { 1270 unsigned DstReg = MI.getOperand(0).getReg(); 1271 bool DstIsDead = MI.getOperand(0).isDead(); 1272 const MachineOperand &MO1 = MI.getOperand(1); 1273 const GlobalValue *GV = MO1.getGlobal(); 1274 bool IsARM = 1275 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs; 1276 bool IsPIC = 1277 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs; 1278 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci; 1279 unsigned PICAddOpc = 1280 IsARM 1281 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 1282 : ARM::tPICADD; 1283 1284 // We need a new const-pool entry to load from. 1285 MachineConstantPool *MCP = MBB.getParent()->getConstantPool(); 1286 unsigned ARMPCLabelIndex = 0; 1287 MachineConstantPoolValue *CPV; 1288 1289 if (IsPIC) { 1290 unsigned PCAdj = IsARM ? 8 : 4; 1291 ARMPCLabelIndex = AFI->createPICLabelUId(); 1292 CPV = ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, 1293 ARMCP::CPValue, PCAdj); 1294 } else 1295 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier); 1296 1297 MachineInstrBuilder MIB = 1298 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg) 1299 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4)); 1300 if (IsARM) 1301 MIB.addImm(0); 1302 AddDefaultPred(MIB); 1303 1304 if (IsPIC) { 1305 MachineInstrBuilder MIB = 1306 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc)) 1307 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 1308 .addReg(DstReg) 1309 .addImm(ARMPCLabelIndex); 1310 1311 if (IsARM) 1312 AddDefaultPred(MIB); 1313 } 1314 1315 MI.eraseFromParent(); 1316 return true; 1317 } 1318 case ARM::MOV_ga_pcrel: 1319 case ARM::MOV_ga_pcrel_ldr: 1320 case ARM::t2MOV_ga_pcrel: { 1321 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode. 1322 unsigned LabelId = AFI->createPICLabelUId(); 1323 unsigned DstReg = MI.getOperand(0).getReg(); 1324 bool DstIsDead = MI.getOperand(0).isDead(); 1325 const MachineOperand &MO1 = MI.getOperand(1); 1326 const GlobalValue *GV = MO1.getGlobal(); 1327 unsigned TF = MO1.getTargetFlags(); 1328 bool isARM = Opcode != ARM::t2MOV_ga_pcrel; 1329 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; 1330 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; 1331 unsigned LO16TF = TF | ARMII::MO_LO16; 1332 unsigned HI16TF = TF | ARMII::MO_HI16; 1333 unsigned PICAddOpc = isARM 1334 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 1335 : ARM::tPICADD; 1336 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1337 TII->get(LO16Opc), DstReg) 1338 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) 1339 .addImm(LabelId); 1340 1341 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg) 1342 .addReg(DstReg) 1343 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) 1344 .addImm(LabelId); 1345 1346 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1347 TII->get(PICAddOpc)) 1348 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 1349 .addReg(DstReg).addImm(LabelId); 1350 if (isARM) { 1351 AddDefaultPred(MIB3); 1352 if (Opcode == ARM::MOV_ga_pcrel_ldr) 1353 MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 1354 } 1355 TransferImpOps(MI, MIB1, MIB3); 1356 MI.eraseFromParent(); 1357 return true; 1358 } 1359 1360 case ARM::MOVi32imm: 1361 case ARM::MOVCCi32imm: 1362 case ARM::t2MOVi32imm: 1363 case ARM::t2MOVCCi32imm: 1364 ExpandMOV32BitImm(MBB, MBBI); 1365 return true; 1366 1367 case ARM::SUBS_PC_LR: { 1368 MachineInstrBuilder MIB = 1369 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) 1370 .addReg(ARM::LR) 1371 .addOperand(MI.getOperand(0)) 1372 .addOperand(MI.getOperand(1)) 1373 .addOperand(MI.getOperand(2)) 1374 .addReg(ARM::CPSR, RegState::Undef); 1375 TransferImpOps(MI, MIB, MIB); 1376 MI.eraseFromParent(); 1377 return true; 1378 } 1379 case ARM::VLDMQIA: { 1380 unsigned NewOpc = ARM::VLDMDIA; 1381 MachineInstrBuilder MIB = 1382 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 1383 unsigned OpIdx = 0; 1384 1385 // Grab the Q register destination. 1386 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 1387 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 1388 1389 // Copy the source register. 1390 MIB.addOperand(MI.getOperand(OpIdx++)); 1391 1392 // Copy the predicate operands. 1393 MIB.addOperand(MI.getOperand(OpIdx++)); 1394 MIB.addOperand(MI.getOperand(OpIdx++)); 1395 1396 // Add the destination operands (D subregs). 1397 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0); 1398 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); 1399 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 1400 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 1401 1402 // Add an implicit def for the super-register. 1403 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 1404 TransferImpOps(MI, MIB, MIB); 1405 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 1406 MI.eraseFromParent(); 1407 return true; 1408 } 1409 1410 case ARM::VSTMQIA: { 1411 unsigned NewOpc = ARM::VSTMDIA; 1412 MachineInstrBuilder MIB = 1413 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 1414 unsigned OpIdx = 0; 1415 1416 // Grab the Q register source. 1417 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 1418 unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 1419 1420 // Copy the destination register. 1421 MIB.addOperand(MI.getOperand(OpIdx++)); 1422 1423 // Copy the predicate operands. 1424 MIB.addOperand(MI.getOperand(OpIdx++)); 1425 MIB.addOperand(MI.getOperand(OpIdx++)); 1426 1427 // Add the source operands (D subregs). 1428 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); 1429 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); 1430 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0) 1431 .addReg(D1, SrcIsKill ? RegState::Kill : 0); 1432 1433 if (SrcIsKill) // Add an implicit kill for the Q register. 1434 MIB->addRegisterKilled(SrcReg, TRI, true); 1435 1436 TransferImpOps(MI, MIB, MIB); 1437 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 1438 MI.eraseFromParent(); 1439 return true; 1440 } 1441 1442 case ARM::VLD2q8Pseudo: 1443 case ARM::VLD2q16Pseudo: 1444 case ARM::VLD2q32Pseudo: 1445 case ARM::VLD2q8PseudoWB_fixed: 1446 case ARM::VLD2q16PseudoWB_fixed: 1447 case ARM::VLD2q32PseudoWB_fixed: 1448 case ARM::VLD2q8PseudoWB_register: 1449 case ARM::VLD2q16PseudoWB_register: 1450 case ARM::VLD2q32PseudoWB_register: 1451 case ARM::VLD3d8Pseudo: 1452 case ARM::VLD3d16Pseudo: 1453 case ARM::VLD3d32Pseudo: 1454 case ARM::VLD1d64TPseudo: 1455 case ARM::VLD1d64TPseudoWB_fixed: 1456 case ARM::VLD3d8Pseudo_UPD: 1457 case ARM::VLD3d16Pseudo_UPD: 1458 case ARM::VLD3d32Pseudo_UPD: 1459 case ARM::VLD3q8Pseudo_UPD: 1460 case ARM::VLD3q16Pseudo_UPD: 1461 case ARM::VLD3q32Pseudo_UPD: 1462 case ARM::VLD3q8oddPseudo: 1463 case ARM::VLD3q16oddPseudo: 1464 case ARM::VLD3q32oddPseudo: 1465 case ARM::VLD3q8oddPseudo_UPD: 1466 case ARM::VLD3q16oddPseudo_UPD: 1467 case ARM::VLD3q32oddPseudo_UPD: 1468 case ARM::VLD4d8Pseudo: 1469 case ARM::VLD4d16Pseudo: 1470 case ARM::VLD4d32Pseudo: 1471 case ARM::VLD1d64QPseudo: 1472 case ARM::VLD1d64QPseudoWB_fixed: 1473 case ARM::VLD4d8Pseudo_UPD: 1474 case ARM::VLD4d16Pseudo_UPD: 1475 case ARM::VLD4d32Pseudo_UPD: 1476 case ARM::VLD4q8Pseudo_UPD: 1477 case ARM::VLD4q16Pseudo_UPD: 1478 case ARM::VLD4q32Pseudo_UPD: 1479 case ARM::VLD4q8oddPseudo: 1480 case ARM::VLD4q16oddPseudo: 1481 case ARM::VLD4q32oddPseudo: 1482 case ARM::VLD4q8oddPseudo_UPD: 1483 case ARM::VLD4q16oddPseudo_UPD: 1484 case ARM::VLD4q32oddPseudo_UPD: 1485 case ARM::VLD3DUPd8Pseudo: 1486 case ARM::VLD3DUPd16Pseudo: 1487 case ARM::VLD3DUPd32Pseudo: 1488 case ARM::VLD3DUPd8Pseudo_UPD: 1489 case ARM::VLD3DUPd16Pseudo_UPD: 1490 case ARM::VLD3DUPd32Pseudo_UPD: 1491 case ARM::VLD4DUPd8Pseudo: 1492 case ARM::VLD4DUPd16Pseudo: 1493 case ARM::VLD4DUPd32Pseudo: 1494 case ARM::VLD4DUPd8Pseudo_UPD: 1495 case ARM::VLD4DUPd16Pseudo_UPD: 1496 case ARM::VLD4DUPd32Pseudo_UPD: 1497 ExpandVLD(MBBI); 1498 return true; 1499 1500 case ARM::VST2q8Pseudo: 1501 case ARM::VST2q16Pseudo: 1502 case ARM::VST2q32Pseudo: 1503 case ARM::VST2q8PseudoWB_fixed: 1504 case ARM::VST2q16PseudoWB_fixed: 1505 case ARM::VST2q32PseudoWB_fixed: 1506 case ARM::VST2q8PseudoWB_register: 1507 case ARM::VST2q16PseudoWB_register: 1508 case ARM::VST2q32PseudoWB_register: 1509 case ARM::VST3d8Pseudo: 1510 case ARM::VST3d16Pseudo: 1511 case ARM::VST3d32Pseudo: 1512 case ARM::VST1d64TPseudo: 1513 case ARM::VST3d8Pseudo_UPD: 1514 case ARM::VST3d16Pseudo_UPD: 1515 case ARM::VST3d32Pseudo_UPD: 1516 case ARM::VST1d64TPseudoWB_fixed: 1517 case ARM::VST1d64TPseudoWB_register: 1518 case ARM::VST3q8Pseudo_UPD: 1519 case ARM::VST3q16Pseudo_UPD: 1520 case ARM::VST3q32Pseudo_UPD: 1521 case ARM::VST3q8oddPseudo: 1522 case ARM::VST3q16oddPseudo: 1523 case ARM::VST3q32oddPseudo: 1524 case ARM::VST3q8oddPseudo_UPD: 1525 case ARM::VST3q16oddPseudo_UPD: 1526 case ARM::VST3q32oddPseudo_UPD: 1527 case ARM::VST4d8Pseudo: 1528 case ARM::VST4d16Pseudo: 1529 case ARM::VST4d32Pseudo: 1530 case ARM::VST1d64QPseudo: 1531 case ARM::VST4d8Pseudo_UPD: 1532 case ARM::VST4d16Pseudo_UPD: 1533 case ARM::VST4d32Pseudo_UPD: 1534 case ARM::VST1d64QPseudoWB_fixed: 1535 case ARM::VST1d64QPseudoWB_register: 1536 case ARM::VST4q8Pseudo_UPD: 1537 case ARM::VST4q16Pseudo_UPD: 1538 case ARM::VST4q32Pseudo_UPD: 1539 case ARM::VST4q8oddPseudo: 1540 case ARM::VST4q16oddPseudo: 1541 case ARM::VST4q32oddPseudo: 1542 case ARM::VST4q8oddPseudo_UPD: 1543 case ARM::VST4q16oddPseudo_UPD: 1544 case ARM::VST4q32oddPseudo_UPD: 1545 ExpandVST(MBBI); 1546 return true; 1547 1548 case ARM::VLD1LNq8Pseudo: 1549 case ARM::VLD1LNq16Pseudo: 1550 case ARM::VLD1LNq32Pseudo: 1551 case ARM::VLD1LNq8Pseudo_UPD: 1552 case ARM::VLD1LNq16Pseudo_UPD: 1553 case ARM::VLD1LNq32Pseudo_UPD: 1554 case ARM::VLD2LNd8Pseudo: 1555 case ARM::VLD2LNd16Pseudo: 1556 case ARM::VLD2LNd32Pseudo: 1557 case ARM::VLD2LNq16Pseudo: 1558 case ARM::VLD2LNq32Pseudo: 1559 case ARM::VLD2LNd8Pseudo_UPD: 1560 case ARM::VLD2LNd16Pseudo_UPD: 1561 case ARM::VLD2LNd32Pseudo_UPD: 1562 case ARM::VLD2LNq16Pseudo_UPD: 1563 case ARM::VLD2LNq32Pseudo_UPD: 1564 case ARM::VLD3LNd8Pseudo: 1565 case ARM::VLD3LNd16Pseudo: 1566 case ARM::VLD3LNd32Pseudo: 1567 case ARM::VLD3LNq16Pseudo: 1568 case ARM::VLD3LNq32Pseudo: 1569 case ARM::VLD3LNd8Pseudo_UPD: 1570 case ARM::VLD3LNd16Pseudo_UPD: 1571 case ARM::VLD3LNd32Pseudo_UPD: 1572 case ARM::VLD3LNq16Pseudo_UPD: 1573 case ARM::VLD3LNq32Pseudo_UPD: 1574 case ARM::VLD4LNd8Pseudo: 1575 case ARM::VLD4LNd16Pseudo: 1576 case ARM::VLD4LNd32Pseudo: 1577 case ARM::VLD4LNq16Pseudo: 1578 case ARM::VLD4LNq32Pseudo: 1579 case ARM::VLD4LNd8Pseudo_UPD: 1580 case ARM::VLD4LNd16Pseudo_UPD: 1581 case ARM::VLD4LNd32Pseudo_UPD: 1582 case ARM::VLD4LNq16Pseudo_UPD: 1583 case ARM::VLD4LNq32Pseudo_UPD: 1584 case ARM::VST1LNq8Pseudo: 1585 case ARM::VST1LNq16Pseudo: 1586 case ARM::VST1LNq32Pseudo: 1587 case ARM::VST1LNq8Pseudo_UPD: 1588 case ARM::VST1LNq16Pseudo_UPD: 1589 case ARM::VST1LNq32Pseudo_UPD: 1590 case ARM::VST2LNd8Pseudo: 1591 case ARM::VST2LNd16Pseudo: 1592 case ARM::VST2LNd32Pseudo: 1593 case ARM::VST2LNq16Pseudo: 1594 case ARM::VST2LNq32Pseudo: 1595 case ARM::VST2LNd8Pseudo_UPD: 1596 case ARM::VST2LNd16Pseudo_UPD: 1597 case ARM::VST2LNd32Pseudo_UPD: 1598 case ARM::VST2LNq16Pseudo_UPD: 1599 case ARM::VST2LNq32Pseudo_UPD: 1600 case ARM::VST3LNd8Pseudo: 1601 case ARM::VST3LNd16Pseudo: 1602 case ARM::VST3LNd32Pseudo: 1603 case ARM::VST3LNq16Pseudo: 1604 case ARM::VST3LNq32Pseudo: 1605 case ARM::VST3LNd8Pseudo_UPD: 1606 case ARM::VST3LNd16Pseudo_UPD: 1607 case ARM::VST3LNd32Pseudo_UPD: 1608 case ARM::VST3LNq16Pseudo_UPD: 1609 case ARM::VST3LNq32Pseudo_UPD: 1610 case ARM::VST4LNd8Pseudo: 1611 case ARM::VST4LNd16Pseudo: 1612 case ARM::VST4LNd32Pseudo: 1613 case ARM::VST4LNq16Pseudo: 1614 case ARM::VST4LNq32Pseudo: 1615 case ARM::VST4LNd8Pseudo_UPD: 1616 case ARM::VST4LNd16Pseudo_UPD: 1617 case ARM::VST4LNd32Pseudo_UPD: 1618 case ARM::VST4LNq16Pseudo_UPD: 1619 case ARM::VST4LNq32Pseudo_UPD: 1620 ExpandLaneOp(MBBI); 1621 return true; 1622 1623 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; 1624 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; 1625 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; 1626 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; 1627 1628 case ARM::CMP_SWAP_8: 1629 if (STI->isThumb()) 1630 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, 1631 ARM::tUXTB, NextMBBI); 1632 else 1633 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, 1634 ARM::UXTB, NextMBBI); 1635 case ARM::CMP_SWAP_16: 1636 if (STI->isThumb()) 1637 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, 1638 ARM::tUXTH, NextMBBI); 1639 else 1640 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, 1641 ARM::UXTH, NextMBBI); 1642 case ARM::CMP_SWAP_32: 1643 if (STI->isThumb()) 1644 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, 1645 NextMBBI); 1646 else 1647 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); 1648 1649 case ARM::CMP_SWAP_64: 1650 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI); 1651 } 1652 } 1653 1654 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { 1655 bool Modified = false; 1656 1657 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 1658 while (MBBI != E) { 1659 MachineBasicBlock::iterator NMBBI = std::next(MBBI); 1660 Modified |= ExpandMI(MBB, MBBI, NMBBI); 1661 MBBI = NMBBI; 1662 } 1663 1664 return Modified; 1665 } 1666 1667 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 1668 STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget()); 1669 TII = STI->getInstrInfo(); 1670 TRI = STI->getRegisterInfo(); 1671 AFI = MF.getInfo<ARMFunctionInfo>(); 1672 1673 bool Modified = false; 1674 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; 1675 ++MFI) 1676 Modified |= ExpandMBB(*MFI); 1677 if (VerifyARMPseudo) 1678 MF.verify(this, "After expanding ARM pseudo instructions."); 1679 return Modified; 1680 } 1681 1682 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction 1683 /// expansion pass. 1684 FunctionPass *llvm::createARMExpandPseudoPass() { 1685 return new ARMExpandPseudo(); 1686 } 1687
