| /art/compiler/utils/arm/ |
| assembler_arm_vixl.h | 77 void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
78 MacroAssembler::func_name(vixl32::DontCare, rd, rn, operand); \
102 void (func_name)(vixl32::Register rd, const vixl32::Operand& operand) { \
103 MacroAssembler::func_name(vixl32::DontCare, rd, operand); \
113 void Rrx(vixl32::Register rd, vixl32::Register rn) {
114 MacroAssembler::Rrx(vixl32::DontCare, rd, rn);
118 void Mul(vixl32::Register rd, vixl32::Register rn, vixl32::Register rm) {
119 MacroAssembler::Mul(vixl32::DontCare, rd, rn, rm);
125 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) {
126 if (rd.Is(rn) && operand.IsPlainRegister())
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| mips64_disassem.c | 180 reg_name[i.RType.rd],
186 db_printf("rotr\t%s,%s,%d", reg_name[i.RType.rd],
191 db_printf("rotrv\t%s,%s,%s", reg_name[i.RType.rd],
202 db_printf("\t%s,%s,%s", reg_name[i.RType.rd],
212 db_printf("\t%s,%s,%s", reg_name[i.RType.rd],
217 if (i.RType.func == OP_JALR && i.RType.rd == 0) {
236 reg_name[i.RType.rd],
248 reg_name[i.RType.rd],
258 reg_name[i.RType.rd],
264 if (i.RType.rd != 31)
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/cris/ |
| rd-bcnst-pic.d | 3 #source: rd-bcnst.s
|
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-i386/ |
| no-plt.exp | 70 {{readelf -Wr libno-plt-1b.rd} \
80 {{readelf -Wr no-plt-1a.rd} {objdump -dwrj.text no-plt-1a.dd}} \
89 {{readelf -Wr no-plt-1b.rd} {objdump -dwrj.text no-plt-1b.dd}} \
98 {{readelf -Wr no-plt-1c.rd} {objdump -dwrj.text no-plt-1c.dd}} \
107 {{readelf -Wr no-plt-1d.rd} {objdump -dwrj.text no-plt-1d.dd}} \
116 {{readelf -Wr no-plt-1e.rd} {objdump -dwrj.text no-plt-1e.dd}} \
125 {{readelf -Wr no-plt-1f.rd} {objdump -dwrj.text no-plt-1f.dd}} \
134 {{readelf -Wr no-plt-1g.rd} {objdump -dwrj.text no-plt-1g.dd}} \
143 {{readelf -Wr no-plt-1h.rd} {objdump -dwrj.text no-plt-1h.dd}} \
152 {{readelf -Wr no-plt-1i.rd} {objdump -dwrj.text no-plt-1i.dd}}
[all...] |
| i386.exp | 29 {{readelf --relocs vxworks1-lib.rd} {objdump -dr vxworks1-lib.dd}
35 {{readelf --relocs vxworks1.rd} {objdump -dr vxworks1.dd}}
133 {{readelf -Ssrl tlspic.rd} {objdump -drj.text tlspic.dd}
140 {{readelf -Ssrl tlspic2.rd} {objdump -drj.text tlspic2.dd}
146 {{readelf -Ssrl tlsdesc.rd} {objdump -drj.text tlsdesc.dd}
154 {{readelf -Ssrl tlsbin.rd} {objdump -drj.text tlsbin.dd}
161 {{readelf -Ssrl tlsbin2.rd} {objdump -drj.text tlsbin2.dd}
167 {{readelf -Ssrl tlsbindesc.rd} {objdump -drj.text tlsbindesc.dd}
173 {{readelf -Ssrl tlsnopic.rd} {objdump -drj.text tlsnopic.dd}
178 {{readelf -Ssrl tlsgdesc.rd} {objdump -drj.text tlsgdesc.dd}
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64.cc | 529 // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
545 // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
3212 Register rd = Register::XRegFromCode(rd_code); local
[all...] |
| assembler-arm64.h | [all...] |
| /external/vixl/tools/ |
| generate_tests.py | 45 - test/aarch32/test-assembler-cond-rd-rn-immediate-a32.cc
46 - test/aarch32/test-assembler-cond-rd-rn-rm-a32.cc
47 - test/aarch32/test-assembler-cond-rd-rn-rm-q-a32.cc
48 - test/aarch32/test-assembler-cond-rd-rn-rm-ge-a32.cc
54 $ cat test/aarch32/traces/sim-cond-rd-rn-immediate-adc-a32.h
88 test/aarch32/config/cond-rd-rn-immediate-a32.json
89 `-> test/aarch32/test-simulator-cond-rd-rn-immediate-a32.cc
90 `-> test/aarch32/test-assembler-cond-rd-rn-immediate-a32.cc
241 "XXX.cond rd rn rm shift #amount":
247 Register rd = ...
[all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.h | 640 const Register& rd,
648 void And(const Register& rd, const Register& rn, const Operand& operand);
649 void Ands(const Register& rd, const Register& rn, const Operand& operand);
650 void Bic(const Register& rd, const Register& rn, const Operand& operand);
651 void Bics(const Register& rd, const Register& rn, const Operand& operand);
652 void Orr(const Register& rd, const Register& rn, const Operand& operand);
653 void Orn(const Register& rd, const Register& rn, const Operand& operand);
654 void Eor(const Register& rd, const Register& rn, const Operand& operand);
655 void Eon(const Register& rd, const Register& rn, const Operand& operand);
657 void LogicalMacro(const Register& rd,
[all...] |
| /external/clang/test/CXX/dcl.decl/dcl.init/dcl.init.ref/ |
| p5-examples.cpp | 6 // CHECK: VarDecl{{.*}}rd 'double &'
8 double &rd = d; local
|
| /external/curl/tests/libtest/ |
| lib503.c | 65 fd_set rd, wr, exc; local
78 FD_ZERO(&rd);
82 multi_fdset(m, &rd, &wr, &exc, &maxfd);
86 select_test(maxfd + 1, &rd, &wr, &exc, &interval);
|
| lib504.c | 42 fd_set rd, wr, exc; local
88 FD_ZERO(&rd);
94 multi_fdset(m, &rd, &wr, &exc, &maxfd);
98 select_test(maxfd + 1, &rd, &wr, &exc, &interval);
|
| lib530.c | 76 fd_set rd, wr, exc; local
96 FD_ZERO(&rd);
100 multi_fdset(m, &rd, &wr, &exc, &maxfd);
104 select_test(maxfd + 1, &rd, &wr, &exc, &interval);
|
| lib533.c | 60 fd_set rd, wr, exc; local
90 FD_ZERO(&rd);
94 multi_fdset(m, &rd, &wr, &exc, &maxfd);
98 select_test(maxfd + 1, &rd, &wr, &exc, &interval);
|
| lib564.c | 58 fd_set rd, wr, exc; local
71 FD_ZERO(&rd);
75 multi_fdset(m, &rd, &wr, &exc, &maxfd);
79 select_test(maxfd + 1, &rd, &wr, &exc, &interval);
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arc/ |
| nps400-2.d | 10 4: 3e6f 7084 schd\.rd
15 18: 3e6f 703f sync\.rd
|
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-x86-64/ |
| no-plt.exp | 68 {{readelf -Wr libno-plt-1b.rd} \
78 {{readelf -Wr no-plt-1a.rd} {objdump -dwrj.text no-plt-1a.dd}} \
87 {{readelf -Wr no-plt-1b.rd} {objdump -dwrj.text no-plt-1b.dd}} \
96 {{readelf -Wr no-plt-1c.rd} {objdump -dwrj.text no-plt-1c.dd}} \
105 {{readelf -Wr no-plt-1d.rd} {objdump -dwrj.text no-plt-1d.dd}} \
114 {{readelf -Wr no-plt-1e.rd} {objdump -dwrj.text no-plt-1e.dd}} \
123 {{readelf -Wr no-plt-1f.rd} {objdump -dwrj.text no-plt-1f.dd}} \
132 {{readelf -Wr no-plt-1g.rd} {objdump -dwrj.text no-plt-1g.dd}} \
|
| x86-64.exp | 55 {{readelf -WSsrl tlspic.rd} {objdump -drj.text\ -Mintel64 tlspic.dd}
62 {{readelf -WSsrl tlspic2.rd} {objdump -drj.text\ -Mintel64 tlspic2.dd}
68 {{readelf -WSsrld tlsdesc.rd} {objdump -drj.text tlsdesc.dd}
76 {{readelf -WSsrl tlsbin.rd} {objdump -drj.text tlsbin.dd}
82 {{readelf -WSsrl tlsbin2.rd} {objdump -drj.text tlsbin2.dd}
88 {{readelf -WSsrl tlsbindesc.rd} {objdump -drj.text tlsbindesc.dd}
94 {{readelf -WSsrl tlsgdesc.rd} {objdump -drj.text\ -Mintel64 tlsgdesc.dd}}
119 {{readelf -SW split-by-file.rd}} "split-by-file.o"}
199 "--64" {pr17709b.s} {{readelf -rW pr17709.rd}} "pr17709"}
205 "--64" { dummy.s } {{readelf {-rW} pr19827.rd}} "pr19827"
[all...] |
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-xtensa/ |
| xtensa.exp | 38 {{readelf -WSsrl tlspic.rd}
47 {{readelf -WSsrl tlsbin.rd}
|
| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 66 void TemplateLoadConst32(Asm* a, GpuRegister rd, int32_t value) {
69 a->Ori(rd, ZERO, value);
72 a->Addiu(rd, ZERO, value);
76 a->Lui(rd, value >> 16);
80 a->Ori(rd, rd, value);
97 void TemplateLoadConst64(Asm* a, Rtype rd, Vtype value) {
105 a->Ori(rd, ZERO, value);
109 a->Daddiu(rd, ZERO, value);
114 a->Lui(rd, value >> 16)
[all...] |
| /external/valgrind/none/tests/arm64/ |
| integer.stdout.exp | 2 add x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000
3 add w3, w4, w5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000
4 adc x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000
5 adc x3, x4, x5 :: rd 0000000000004abf rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 20000000 C
6 adc x3, x4, x5 :: rd ffffffffffffffff rm 0000000000000000, rn ffffffffffffffff, cin 0, nzcv 00000000
7 adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn ffffffffffffffff, cin 1, nzcv 20000000 C
8 adc x3, x4, x5 :: rd 5859704f00000000 rm 3141592700000000, rn 2718172800000000, cin 0, nzcv 00000000
9 adc x3, x4, x5 :: rd 5859704f00000001 rm 3141592700000000, rn 2718172800000000, cin 1, nzcv 20000000 C
10 adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 00000000
11 adc x3, x4, x5 :: rd 0000000000000001 rm 0000000000000000, rn 0000000000000000, cin 1, nzcv 20000000 C
[all...] |
| /external/v8/src/mips64/ |
| assembler-mips64.h | 100 static const int kCpRegister = 23; // cp (s7) is the 23rd register.
722 void jalr(Register rs, Register rd = ra);
731 void addu(Register rd, Register rs, Register rt);
732 void subu(Register rd, Register rs, Register rt);
738 void div(Register rd, Register rs, Register rt);
739 void divu(Register rd, Register rs, Register rt);
740 void ddiv(Register rd, Register rs, Register rt);
741 void ddivu(Register rd, Register rs, Register rt);
742 void mod(Register rd, Register rs, Register rt);
743 void modu(Register rd, Register rs, Register rt)
[all...] |
| assembler-mips64.cc | 342 Register rd; local
343 rd.reg_code = (instr & kRdFieldMask) >> kRdShift;
344 return rd;
603 uint32_t rd = GetRd(instr);
613 rd == static_cast<uint32_t>(ToNumber(zero_reg)) &&
1000 Register rd,
1003 DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));
1005 | (rd.code() << kRdShift) | (sa << kSaShift) | func;
[all...] |
| /external/libvpx/libvpx/vp9/encoder/ |
| vp9_rd.c | 60 // The baseline rd thresholds for breaking out of the rd loop for
226 static void set_block_thresholds(const VP9_COMMON *cm, RD_OPT *rd) {
244 rd->threshes[segment_id][bsize][i] = rd->thresh_mult[i] < thresh_max
245 ? rd->thresh_mult[i] * t / 4
249 rd->threshes[segment_id][bsize][i] =
250 rd->thresh_mult_sub8x8[i] < thresh_max
251 ? rd->thresh_mult_sub8x8[i] * t / 4
262 RD_OPT *const rd = &cpi->rd local
590 RD_OPT *const rd = &cpi->rd; local
647 RD_OPT *const rd = &cpi->rd; local
[all...] |
| /external/python/cpython2/Lib/test/ |
| test_poll.py | 44 rd, wr = os.pipe()
45 p.register(rd)
46 p.modify(rd, select.POLLIN)
48 readers.append(rd)
50 r2w[rd] = wr
51 w2r[wr] = rd
67 rd = random.choice(ready_readers)
68 buf = os.read(rd, MSG_LEN)
71 os.close(r2w[rd]) ; os.close( rd )
[all...] |
